source: rtems/c/src/exec/score/cpu/i960/rtems/score/cpu.h @ 702c5f5

4.104.114.84.9
Last change on this file since 702c5f5 was 702c5f5, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 27, 1999 at 3:29:18 PM

The rxgen960 BSP and i960 RPM support was submitted by Mark Bronson
<mark@…> of RAMIX.

  • Property mode set to 100644
File size: 13.0 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#pragma align 4            /* for GNU C structure alignment */
25
26#include <rtems/score/i960.h>              /* pick up machine definitions */
27#ifndef ASM
28#include <rtems/score/i960types.h>
29#endif
30
31#define CPU_INLINE_ENABLE_DISPATCH       FALSE
32#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
33
34/*
35 *  Use the i960's hardware interrupt stack support and have the
36 *  interrupt manager allocate the memory for it.
37 */
38
39#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
40#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
41#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
42
43/*
44 *  Does the RTEMS invoke the user's ISR with the vector number and
45 *  a pointer to the saved interrupt frame (1) or just the vector
46 *  number (0)?
47 */
48
49#define CPU_ISR_PASSES_FRAME_POINTER 0
50
51/*
52 *  Some family members have no FP (SA/KA/CA/CF), others have it built in
53 *  (KB/MC/MX).  There does not appear to be an external coprocessor
54 *  for this family.
55 */
56
57#if ( I960_HAS_FPU == 1 )
58#define CPU_HARDWARE_FP     TRUE
59#error "Floating point support for i960 family has been implemented!!!"
60#else
61#define CPU_HARDWARE_FP     FALSE
62#endif
63
64#define CPU_ALL_TASKS_ARE_FP             FALSE
65#define CPU_IDLE_TASK_IS_FP              FALSE
66#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
67
68#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
69#define CPU_STACK_GROWS_UP               TRUE
70#define CPU_STRUCTURE_ALIGNMENT          /* __attribute__ ((aligned (16))) */
71
72/*
73 *  Define what is required to specify how the network to host conversion
74 *  routines are handled.
75 */
76
77#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
78#define CPU_BIG_ENDIAN                           TRUE
79#define CPU_LITTLE_ENDIAN                        FALSE
80
81
82/* structures */
83
84/*
85 *  Basic integer context for the i960 family.
86 */
87
88typedef struct {
89  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
90  void       *r1_sp;                  /* (r1)  Stack Pointer */
91  unsigned32  pc;                     /* (pc)  Processor Control */
92  void       *g8;                     /* (g8)  Global Register 8 */
93  void       *g9;                     /* (g9)  Global Register 9 */
94  void       *g10;                    /* (g10) Global Register 10 */
95  void       *g11;                    /* (g11) Global Register 11 */
96  void       *g12;                    /* (g12) Global Register 12 */
97  void       *g13;                    /* (g13) Global Register 13 */
98  unsigned32  g14;                    /* (g14) Global Register 14 */
99  void       *g15_fp;                 /* (g15) Frame Pointer */
100}   Context_Control;
101
102/*
103 *  FP context save area for the i960 Numeric Extension
104 */
105
106typedef struct {
107   unsigned32  fp0_1;                 /* (fp0) first word  */
108   unsigned32  fp0_2;                 /* (fp0) second word */
109   unsigned32  fp0_3;                 /* (fp0) third word  */
110   unsigned32  fp1_1;                 /* (fp1) first word  */
111   unsigned32  fp1_2;                 /* (fp1) second word */
112   unsigned32  fp1_3;                 /* (fp1) third word  */
113   unsigned32  fp2_1;                 /* (fp2) first word  */
114   unsigned32  fp2_2;                 /* (fp2) second word */
115   unsigned32  fp2_3;                 /* (fp2) third word  */
116   unsigned32  fp3_1;                 /* (fp3) first word  */
117   unsigned32  fp3_2;                 /* (fp3) second word */
118   unsigned32  fp3_3;                 /* (fp3) third word  */
119} Context_Control_fp;
120
121/*
122 *  The following structure defines the set of information saved
123 *  on the current stack by RTEMS upon receipt of each interrupt.
124 */
125
126typedef struct {
127  unsigned32   TBD;   /* XXX Fix for this CPU */
128} CPU_Interrupt_frame;
129
130/*
131 *  Call frame for the i960 family.
132 */
133
134typedef struct {
135  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
136  void       *r1_sp;                  /* (r1)  Stack Pointer */
137  void       *r2_rip;                 /* (r2)  Return Instruction Pointer */
138  void       *r3;                     /* (r3)  Local Register 3 */
139  void       *r4;                     /* (r4)  Local Register 4 */
140  void       *r5;                     /* (r5)  Local Register 5 */
141  void       *r6;                     /* (r6)  Local Register 6 */
142  void       *r7;                     /* (r7)  Local Register 7 */
143  void       *r8;                     /* (r8)  Local Register 8 */
144  void       *r9;                     /* (r9)  Local Register 9 */
145  void       *r10;                    /* (r10) Local Register 10 */
146  void       *r11;                    /* (r11) Local Register 11 */
147  void       *r12;                    /* (r12) Local Register 12 */
148  void       *r13;                    /* (r13) Local Register 13 */
149  void       *r14;                    /* (r14) Local Register 14 */
150  void       *r15;                    /* (r15) Local Register 15 */
151  /* XXX Looks like sometimes there is FP stuff here (MC manual)? */
152}   CPU_Call_frame;
153
154/*
155 *  The following table contains the information required to configure
156 *  the i960 specific parameters.
157 */
158
159typedef struct {
160  void       (*pretasking_hook)( void );
161  void       (*predriver_hook)( void );
162  void       (*postdriver_hook)( void );
163  void       (*idle_task)( void );
164  boolean      do_zero_of_workspace;
165  unsigned32   idle_task_stack_size;
166  unsigned32   interrupt_stack_size;
167  unsigned32   extra_mpci_receive_server_stack;
168  void *     (*stack_allocate_hook)( unsigned32 );
169  void       (*stack_free_hook)( void* );
170  /* end of fields required on all CPUs */
171
172  i960_PRCB *Prcb;
173}   rtems_cpu_table;
174
175/* variables */
176
177SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
178SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
179
180/* constants */
181
182/*
183 *  This defines the number of levels and the mask used to pick those
184 *  bits out of a thread mode.
185 */
186
187#define CPU_MODES_INTERRUPT_LEVEL  0x0000001f  /* interrupt level in mode */
188#define CPU_MODES_INTERRUPT_MASK   0x0000001f  /* interrupt level in mode */
189
190/*
191 *  context size area for floating point
192 */
193
194#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
195
196/*
197 *  extra stack required by the MPCI receive server thread
198 */
199
200#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE)
201
202/*
203 *  i960 family supports 256 distinct vectors.
204 */
205
206#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
207#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
208
209/*
210 *  Minimum size of a thread's stack.
211 *
212 *  NOTE:  See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK
213 */
214
215#define CPU_STACK_MINIMUM_SIZE          2048
216
217/*
218 *  i960 is pretty tolerant of alignment but some CPU models do
219 *  better with different default aligments so we use what the
220 *  CPU model selected in rtems/score/i960.h.
221 */
222
223#define CPU_ALIGNMENT                   I960_CPU_ALIGNMENT
224#define CPU_HEAP_ALIGNMENT              CPU_ALIGNMENT
225#define CPU_PARTITION_ALIGNMENT         CPU_ALIGNMENT
226
227/*
228 * i960ca stack requires 16 byte alignment
229 *
230 *  NOTE:  This factor may need to be family member dependent.
231 */
232
233#define CPU_STACK_ALIGNMENT        16
234
235/* macros */
236
237/*
238 *  ISR handler macros
239 *
240 *  These macros perform the following functions:
241 *     + disable all maskable CPU interrupts
242 *     + restore previous interrupt level (enable)
243 *     + temporarily restore interrupts (flash)
244 *     + set a particular level
245 */
246
247#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level )
248#define _CPU_ISR_Enable( _level )  i960_enable_interrupts( _level )
249#define _CPU_ISR_Flash( _level )   i960_flash_interrupts( _level )
250
251#define _CPU_ISR_Set_level( newlevel ) \
252  { \
253    unsigned32 _mask = 0; \
254    unsigned32 _level = (newlevel); \
255    \
256    __asm__ volatile ( "ldconst 0x1f0000,%0; \
257                    modpc   0,%0,%1"     : "=d" (_mask), "=d" (_level) \
258                                         : "0"  (_mask), "1" (_level) \
259    ); \
260  }
261
262unsigned32 _CPU_ISR_Get_level( void );
263
264/* ISR handler section macros */
265
266/*
267 *  Context handler macros
268 *
269 *  These macros perform the following functions:
270 *     + initialize a context area
271 *     + restart the current thread
272 *     + calculate the initial pointer into a FP context area
273 *     + initialize an FP context area
274 */
275
276#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
277                                  _isr, _entry, _is_fp ) \
278 { CPU_Call_frame *_texit_frame; \
279   unsigned32 _mask; \
280   unsigned32 _base_pc; \
281   unsigned32  _stack_tmp; \
282   void       *_stack; \
283   \
284  _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \
285  _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
286  _stack = (void *) _stack_tmp; \
287   \
288   __asm__ volatile ( "flushreg" : : );   /* flush register cache */ \
289   \
290   (_the_context)->r0_pfp = _stack; \
291   (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \
292   (_the_context)->r1_sp  = _stack + (2 * sizeof(CPU_Call_frame)); \
293   __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \
294                  "modpc   0,0,%1 ; " \
295                  "andnot  %0,%1,%1 ; " \
296                  : "=d" (_mask), "=d" (_base_pc) : ); \
297   (_the_context)->pc     = _base_pc | ((_isr) << 16); \
298   (_the_context)->g14    = 0; \
299   \
300   _texit_frame         = (CPU_Call_frame *)_stack; \
301   _texit_frame->r0_pfp = NULL; \
302   _texit_frame->r1_sp  = (_the_context)->g15_fp; \
303   _texit_frame->r2_rip = (_entry); \
304 }
305
306#define _CPU_Context_Restart_self( _the_context ) \
307   _CPU_Context_restore( (_the_context) );
308
309#define _CPU_Context_Fp_start( _base, _offset )         NULL
310
311#define _CPU_Context_Initialize_fp( _fp_area )
312
313/* end of Context handler macros */
314
315/*
316 *  Fatal Error manager macros
317 *
318 *  These macros perform the following functions:
319 *    + disable interrupts and halt the CPU
320 */
321
322#define _CPU_Fatal_halt( _errorcode ) \
323  { unsigned32 _mask, _level; \
324    unsigned32 _error = (_errorcode); \
325    \
326    __asm__ volatile ( "ldconst 0x1f0000,%0 ; \
327                    mov     %0,%1 ; \
328                    modpc   0,%0,%1 ; \
329                    mov     %2,g0 ; \
330            self:   b       self " \
331                    : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \
332  }
333
334/* end of Fatal Error Manager macros */
335
336/*
337 *  Bitfield handler macros
338 *
339 *  These macros perform the following functions:
340 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
341 */
342
343#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
344#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
345
346#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
347  { unsigned32 _search = (_value); \
348    \
349    (_output) = 0; /* to prevent warnings */ \
350    __asm__ volatile ( "scanbit   %0,%1  " \
351                    : "=d" (_search), "=d" (_output) \
352                    : "0"  (_search), "1"  (_output) ); \
353  }
354
355/* end of Bitfield handler macros */
356
357/*
358 *  Priority handler macros
359 *
360 *  These macros perform the following functions:
361 *    + return a mask with the bit for this major/minor portion of
362 *      of thread priority set.
363 *    + translate the bit number returned by "Bitfield_find_first_bit"
364 *      into an index into the thread ready chain bit maps
365 */
366
367#define _CPU_Priority_Mask( _bit_number ) \
368   ( 0x8000 >> (_bit_number) )
369
370#define _CPU_Priority_bits_index( _priority ) \
371   ( 15 - (_priority) )
372
373/* end of Priority handler macros */
374
375/* functions */
376
377/*
378 *  _CPU_Initialize
379 *
380 *  This routine performs CPU dependent initialization.
381 */
382
383void _CPU_Initialize(
384  rtems_cpu_table  *cpu_table,
385  void      (*thread_dispatch)
386);
387
388/*
389 *  _CPU_ISR_install_raw_handler
390 *
391 *  This routine installs a "raw" interrupt handler directly into the
392 *  processor's vector table.
393 */
394 
395void _CPU_ISR_install_raw_handler(
396  unsigned32  vector,
397  proc_ptr    new_handler,
398  proc_ptr   *old_handler
399);
400
401/*
402 *  _CPU_ISR_install_vector
403 *
404 *  This routine installs an interrupt vector.
405 */
406
407void _CPU_ISR_install_vector(
408  unsigned32  vector,
409  proc_ptr    new_handler,
410  proc_ptr   *old_handler
411);
412
413/*
414 *  _CPU_Install_interrupt_stack
415 *
416 *  This routine installs the hardware interrupt stack pointer.
417 */
418
419void _CPU_Install_interrupt_stack( void );
420
421/*
422 *  _CPU_Context_switch
423 *
424 *  This routine switches from the run context to the heir context.
425 */
426
427void _CPU_Context_switch(
428  Context_Control  *run,
429  Context_Control  *heir
430);
431
432/*
433 *  _CPU_Context_restore
434 *
435 *  This routine is generally used only to restart self in an
436 *  efficient manner and avoid stack conflicts.
437 */
438
439void _CPU_Context_restore(
440  Context_Control *new_context
441);
442
443/*
444 *  _CPU_Context_save_fp
445 *
446 *  This routine saves the floating point context passed to it.
447 */
448
449void _CPU_Context_save_fp(
450  void        **fp_context_ptr
451);
452
453/*
454 *  _CPU_Context_restore_fp
455 *
456 *  This routine restores the floating point context passed to it.
457 */
458
459void _CPU_Context_restore_fp(
460  void        **fp_context_ptr
461);
462
463#ifdef __cplusplus
464}
465#endif
466
467#endif
468/* end of include file */
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