source: rtems/c/src/exec/score/cpu/i960/rtems/score/cpu.h @ 08311cc3

4.104.114.84.95
Last change on this file since 08311cc3 was 08311cc3, checked in by Joel Sherrill <joel.sherrill@…>, on 11/17/99 at 17:51:34

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __CPU_h
17#define __CPU_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#pragma align 4            /* for GNU C structure alignment */
24
25#include <rtems/score/i960.h>              /* pick up machine definitions */
26#ifndef ASM
27#include <rtems/score/i960types.h>
28#endif
29
30#define CPU_INLINE_ENABLE_DISPATCH       FALSE
31#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
32
33/*
34 *  Use the i960's hardware interrupt stack support and have the
35 *  interrupt manager allocate the memory for it.
36 */
37
38#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
39#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
40#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
41
42/*
43 *  Does the RTEMS invoke the user's ISR with the vector number and
44 *  a pointer to the saved interrupt frame (1) or just the vector
45 *  number (0)?
46 */
47
48#define CPU_ISR_PASSES_FRAME_POINTER 0
49
50/*
51 *  Some family members have no FP (SA/KA/CA/CF), others have it built in
52 *  (KB/MC/MX).  There does not appear to be an external coprocessor
53 *  for this family.
54 */
55
56#if ( I960_HAS_FPU == 1 )
57#define CPU_HARDWARE_FP     TRUE
58#error "Floating point support for i960 family has been implemented!!!"
59#else
60#define CPU_HARDWARE_FP     FALSE
61#endif
62
63#define CPU_ALL_TASKS_ARE_FP             FALSE
64#define CPU_IDLE_TASK_IS_FP              FALSE
65#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
66
67#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
68#define CPU_STACK_GROWS_UP               TRUE
69#define CPU_STRUCTURE_ALIGNMENT          /* __attribute__ ((aligned (16))) */
70
71/*
72 *  Define what is required to specify how the network to host conversion
73 *  routines are handled.
74 */
75
76#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
77#define CPU_BIG_ENDIAN                           TRUE
78#define CPU_LITTLE_ENDIAN                        FALSE
79
80
81/* structures */
82
83/*
84 *  Basic integer context for the i960 family.
85 */
86
87typedef struct {
88  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
89  void       *r1_sp;                  /* (r1)  Stack Pointer */
90  unsigned32  pc;                     /* (pc)  Processor Control */
91  void       *g8;                     /* (g8)  Global Register 8 */
92  void       *g9;                     /* (g9)  Global Register 9 */
93  void       *g10;                    /* (g10) Global Register 10 */
94  void       *g11;                    /* (g11) Global Register 11 */
95  void       *g12;                    /* (g12) Global Register 12 */
96  void       *g13;                    /* (g13) Global Register 13 */
97  unsigned32  g14;                    /* (g14) Global Register 14 */
98  void       *g15_fp;                 /* (g15) Frame Pointer */
99}   Context_Control;
100
101/*
102 *  FP context save area for the i960 Numeric Extension
103 */
104
105typedef struct {
106   unsigned32  fp0_1;                 /* (fp0) first word  */
107   unsigned32  fp0_2;                 /* (fp0) second word */
108   unsigned32  fp0_3;                 /* (fp0) third word  */
109   unsigned32  fp1_1;                 /* (fp1) first word  */
110   unsigned32  fp1_2;                 /* (fp1) second word */
111   unsigned32  fp1_3;                 /* (fp1) third word  */
112   unsigned32  fp2_1;                 /* (fp2) first word  */
113   unsigned32  fp2_2;                 /* (fp2) second word */
114   unsigned32  fp2_3;                 /* (fp2) third word  */
115   unsigned32  fp3_1;                 /* (fp3) first word  */
116   unsigned32  fp3_2;                 /* (fp3) second word */
117   unsigned32  fp3_3;                 /* (fp3) third word  */
118} Context_Control_fp;
119
120/*
121 *  The following structure defines the set of information saved
122 *  on the current stack by RTEMS upon receipt of each interrupt.
123 */
124
125typedef struct {
126  unsigned32   TBD;   /* XXX Fix for this CPU */
127} CPU_Interrupt_frame;
128
129/*
130 *  Call frame for the i960 family.
131 */
132
133typedef struct {
134  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
135  void       *r1_sp;                  /* (r1)  Stack Pointer */
136  void       *r2_rip;                 /* (r2)  Return Instruction Pointer */
137  void       *r3;                     /* (r3)  Local Register 3 */
138  void       *r4;                     /* (r4)  Local Register 4 */
139  void       *r5;                     /* (r5)  Local Register 5 */
140  void       *r6;                     /* (r6)  Local Register 6 */
141  void       *r7;                     /* (r7)  Local Register 7 */
142  void       *r8;                     /* (r8)  Local Register 8 */
143  void       *r9;                     /* (r9)  Local Register 9 */
144  void       *r10;                    /* (r10) Local Register 10 */
145  void       *r11;                    /* (r11) Local Register 11 */
146  void       *r12;                    /* (r12) Local Register 12 */
147  void       *r13;                    /* (r13) Local Register 13 */
148  void       *r14;                    /* (r14) Local Register 14 */
149  void       *r15;                    /* (r15) Local Register 15 */
150  /* XXX Looks like sometimes there is FP stuff here (MC manual)? */
151}   CPU_Call_frame;
152
153/*
154 *  The following table contains the information required to configure
155 *  the i960 specific parameters.
156 */
157
158typedef struct {
159  void       (*pretasking_hook)( void );
160  void       (*predriver_hook)( void );
161  void       (*postdriver_hook)( void );
162  void       (*idle_task)( void );
163  boolean      do_zero_of_workspace;
164  unsigned32   idle_task_stack_size;
165  unsigned32   interrupt_stack_size;
166  unsigned32   extra_mpci_receive_server_stack;
167  void *     (*stack_allocate_hook)( unsigned32 );
168  void       (*stack_free_hook)( void* );
169  /* end of fields required on all CPUs */
170
171  i960_PRCB *Prcb;
172}   rtems_cpu_table;
173
174/*
175 *  Macros to access required entires in the CPU Table are in
176 *  the file rtems/system.h.
177 */
178
179/*
180 *  Macros to access i960 specific additions to the CPU Table
181 */
182
183#define rtems_cpu_configuration_get_prcb() \
184   (_CPU_Table.Prcb)
185
186/* variables */
187
188SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
189SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
190
191/* constants */
192
193/*
194 *  This defines the number of levels and the mask used to pick those
195 *  bits out of a thread mode.
196 */
197
198#define CPU_MODES_INTERRUPT_LEVEL  0x0000001f  /* interrupt level in mode */
199#define CPU_MODES_INTERRUPT_MASK   0x0000001f  /* interrupt level in mode */
200
201/*
202 *  context size area for floating point
203 */
204
205#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
206
207/*
208 *  extra stack required by the MPCI receive server thread
209 */
210
211#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE)
212
213/*
214 *  i960 family supports 256 distinct vectors.
215 */
216
217#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
218#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
219
220/*
221 *  Minimum size of a thread's stack.
222 *
223 *  NOTE:  See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK
224 */
225
226#define CPU_STACK_MINIMUM_SIZE          2048
227
228/*
229 *  i960 is pretty tolerant of alignment but some CPU models do
230 *  better with different default aligments so we use what the
231 *  CPU model selected in rtems/score/i960.h.
232 */
233
234#define CPU_ALIGNMENT                   I960_CPU_ALIGNMENT
235#define CPU_HEAP_ALIGNMENT              CPU_ALIGNMENT
236#define CPU_PARTITION_ALIGNMENT         CPU_ALIGNMENT
237
238/*
239 * i960ca stack requires 16 byte alignment
240 *
241 *  NOTE:  This factor may need to be family member dependent.
242 */
243
244#define CPU_STACK_ALIGNMENT        16
245
246/* macros */
247
248/*
249 *  ISR handler macros
250 *
251 *  These macros perform the following functions:
252 *     + disable all maskable CPU interrupts
253 *     + restore previous interrupt level (enable)
254 *     + temporarily restore interrupts (flash)
255 *     + set a particular level
256 */
257
258#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level )
259#define _CPU_ISR_Enable( _level )  i960_enable_interrupts( _level )
260#define _CPU_ISR_Flash( _level )   i960_flash_interrupts( _level )
261
262#define _CPU_ISR_Set_level( newlevel ) \
263  { \
264    unsigned32 _mask = 0; \
265    unsigned32 _level = (newlevel); \
266    \
267    __asm__ volatile ( "ldconst 0x1f0000,%0; \
268                    modpc   0,%0,%1"     : "=d" (_mask), "=d" (_level) \
269                                         : "0"  (_mask), "1" (_level) \
270    ); \
271  }
272
273unsigned32 _CPU_ISR_Get_level( void );
274
275/* ISR handler section macros */
276
277/*
278 *  Context handler macros
279 *
280 *  These macros perform the following functions:
281 *     + initialize a context area
282 *     + restart the current thread
283 *     + calculate the initial pointer into a FP context area
284 *     + initialize an FP context area
285 */
286
287#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
288                                  _isr, _entry, _is_fp ) \
289 { CPU_Call_frame *_texit_frame; \
290   unsigned32 _mask; \
291   unsigned32 _base_pc; \
292   unsigned32  _stack_tmp; \
293   void       *_stack; \
294   \
295  _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \
296  _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
297  _stack = (void *) _stack_tmp; \
298   \
299   __asm__ volatile ( "flushreg" : : );   /* flush register cache */ \
300   \
301   (_the_context)->r0_pfp = _stack; \
302   (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \
303   (_the_context)->r1_sp  = _stack + (2 * sizeof(CPU_Call_frame)); \
304   __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \
305                  "modpc   0,0,%1 ; " \
306                  "andnot  %0,%1,%1 ; " \
307                  : "=d" (_mask), "=d" (_base_pc) : ); \
308   (_the_context)->pc     = _base_pc | ((_isr) << 16); \
309   (_the_context)->g14    = 0; \
310   \
311   _texit_frame         = (CPU_Call_frame *)_stack; \
312   _texit_frame->r0_pfp = NULL; \
313   _texit_frame->r1_sp  = (_the_context)->g15_fp; \
314   _texit_frame->r2_rip = (_entry); \
315 }
316
317#define _CPU_Context_Restart_self( _the_context ) \
318   _CPU_Context_restore( (_the_context) );
319
320#define _CPU_Context_Fp_start( _base, _offset )         NULL
321
322#define _CPU_Context_Initialize_fp( _fp_area )
323
324/* end of Context handler macros */
325
326/*
327 *  Fatal Error manager macros
328 *
329 *  These macros perform the following functions:
330 *    + disable interrupts and halt the CPU
331 */
332
333#define _CPU_Fatal_halt( _errorcode ) \
334  { unsigned32 _mask, _level; \
335    unsigned32 _error = (_errorcode); \
336    \
337    __asm__ volatile ( "ldconst 0x1f0000,%0 ; \
338                    mov     %0,%1 ; \
339                    modpc   0,%0,%1 ; \
340                    mov     %2,g0 ; \
341            self:   b       self " \
342                    : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \
343  }
344
345/* end of Fatal Error Manager macros */
346
347/*
348 *  Bitfield handler macros
349 *
350 *  These macros perform the following functions:
351 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
352 */
353
354#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
355#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
356
357#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
358  { unsigned32 _search = (_value); \
359    \
360    (_output) = 0; /* to prevent warnings */ \
361    __asm__ volatile ( "scanbit   %0,%1  " \
362                    : "=d" (_search), "=d" (_output) \
363                    : "0"  (_search), "1"  (_output) ); \
364  }
365
366/* end of Bitfield handler macros */
367
368/*
369 *  Priority handler macros
370 *
371 *  These macros perform the following functions:
372 *    + return a mask with the bit for this major/minor portion of
373 *      of thread priority set.
374 *    + translate the bit number returned by "Bitfield_find_first_bit"
375 *      into an index into the thread ready chain bit maps
376 */
377
378#define _CPU_Priority_Mask( _bit_number ) \
379   ( 0x8000 >> (_bit_number) )
380
381#define _CPU_Priority_bits_index( _priority ) \
382   ( 15 - (_priority) )
383
384/* end of Priority handler macros */
385
386/* functions */
387
388/*
389 *  _CPU_Initialize
390 *
391 *  This routine performs CPU dependent initialization.
392 */
393
394void _CPU_Initialize(
395  rtems_cpu_table  *cpu_table,
396  void      (*thread_dispatch)
397);
398
399/*
400 *  _CPU_ISR_install_raw_handler
401 *
402 *  This routine installs a "raw" interrupt handler directly into the
403 *  processor's vector table.
404 */
405 
406void _CPU_ISR_install_raw_handler(
407  unsigned32  vector,
408  proc_ptr    new_handler,
409  proc_ptr   *old_handler
410);
411
412/*
413 *  _CPU_ISR_install_vector
414 *
415 *  This routine installs an interrupt vector.
416 */
417
418void _CPU_ISR_install_vector(
419  unsigned32  vector,
420  proc_ptr    new_handler,
421  proc_ptr   *old_handler
422);
423
424/*
425 *  _CPU_Install_interrupt_stack
426 *
427 *  This routine installs the hardware interrupt stack pointer.
428 */
429
430void _CPU_Install_interrupt_stack( void );
431
432/*
433 *  _CPU_Context_switch
434 *
435 *  This routine switches from the run context to the heir context.
436 */
437
438void _CPU_Context_switch(
439  Context_Control  *run,
440  Context_Control  *heir
441);
442
443/*
444 *  _CPU_Context_restore
445 *
446 *  This routine is generally used only to restart self in an
447 *  efficient manner and avoid stack conflicts.
448 */
449
450void _CPU_Context_restore(
451  Context_Control *new_context
452);
453
454/*
455 *  _CPU_Context_save_fp
456 *
457 *  This routine saves the floating point context passed to it.
458 */
459
460void _CPU_Context_save_fp(
461  void        **fp_context_ptr
462);
463
464/*
465 *  _CPU_Context_restore_fp
466 *
467 *  This routine restores the floating point context passed to it.
468 */
469
470void _CPU_Context_restore_fp(
471  void        **fp_context_ptr
472);
473
474#ifdef __cplusplus
475}
476#endif
477
478#endif
479/* end of include file */
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