| 1 | /* |
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| 2 | * i960RP Related Definitions. |
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| 3 | * |
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| 4 | * NOTE: There is some commonality with the JX series which is |
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| 5 | * not currently supported by RTEMS. |
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| 6 | * |
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| 7 | * $Id$ |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __I960RP_h |
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| 11 | #define __I960RP_h |
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| 12 | |
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| 13 | /*----------------------------------------------------------*/ |
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| 14 | /* Example 6. Include File (evrp.h) */ |
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| 15 | /*----------------------------------------------------------*/ |
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| 16 | /* Define JX Core memory mapped register addresses */ |
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| 17 | /* Common to Jx and RP: */ |
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| 18 | #define DLMCON_ADDR 0xff008100 |
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| 19 | #define LMAR0_ADDR 0xff008108 |
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| 20 | #define LMMR0_ADDR 0xff00810c |
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| 21 | #define LMAR1_ADDR 0xff008110 |
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| 22 | #define LMMR1_ADDR 0xff008114 |
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| 23 | #define IPB0_ADDR 0xff008400 |
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| 24 | #define IPB1_ADDR 0xff008404 |
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| 25 | #define DAB0_ADDR 0xff008420 |
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| 26 | #define DAB1_ADDR 0xff008424 |
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| 27 | #define BPCON_ADDR 0xff008440 |
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| 28 | #define IPND_ADDR 0xff008500 |
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| 29 | #define IMSK_ADDR 0xff008504 |
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| 30 | #define ICON_ADDR 0xff008510 |
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| 31 | #define IMAP0_ADDR 0xff008520 |
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| 32 | #define IMAP1_ADDR 0xff008524 |
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| 33 | #define IMAP2_ADDR 0xff008528 |
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| 34 | #define PMCON0_ADDR 0xff008600 |
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| 35 | #define PMCON2_ADDR 0xff008608 |
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| 36 | #define PMCON4_ADDR 0xff008610 |
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| 37 | #define PMCON6_ADDR 0xff008618 |
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| 38 | #define PMCON8_ADDR 0xff008620 |
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| 39 | #define PMCON10_ADDR 0xff008628 |
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| 40 | #define PMCON12_ADDR 0xff008630 |
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| 41 | #define PMCON14_ADDR 0xff008638 |
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| 42 | #define BCON_ADDR 0xff0086fc |
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| 43 | #define PRCB_ADDR 0xff008700 |
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| 44 | #define ISP_ADDR 0xff008704 |
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| 45 | #define SSP_ADDR 0xff008708 |
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| 46 | #define DEVID_ADDR 0xff008710 |
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| 47 | #define TRR0_ADDR 0xff000300 |
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| 48 | #define TCR0_ADDR 0xff000304 |
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| 49 | #define TMR0_ADDR 0xff000308 |
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| 50 | #define TRR1_ADDR 0xff000310 |
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| 51 | #define TCR1_ADDR 0xff000314 |
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| 52 | #define TMR1_ADDR 0xff000318 |
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| 53 | |
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| 54 | /* RP-only addresses: */ |
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| 55 | /* RP MMRs */ |
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| 56 | |
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| 57 | /* PCI-to-PCI Bridge Unit 0000 1000H through 0000 10FFH */ |
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| 58 | #define VIDR_ADDR 0x00001000 |
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| 59 | #define DIDR_ADDR 0x00001002 |
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| 60 | #define PCMDR_ADDR 0x00001004 |
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| 61 | #define PSR_ADDR 0x00001006 |
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| 62 | #define RIDR_ADDR 0x00001008 |
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| 63 | #define CCR_ADDR 0x00001009 |
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| 64 | #define CLSR_ADDR 0x0000100C |
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| 65 | #define PLTR_ADDR 0x0000100D |
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| 66 | #define HTR_ADDR 0x0000100E |
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| 67 | /* Reserved 0x0000100F through 0x00001017 */ |
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| 68 | #define PBNR_ADDR 0x00001018 |
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| 69 | #define SBNR_ADDR 0x00001019 |
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| 70 | #define SUBBNR_ADDR 0x0000101A |
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| 71 | #define SLTR_ADDR 0x0000101B |
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| 72 | #define IOBR_ADDR 0x0000101C |
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| 73 | #define IOLR_ADDR 0x0000101D |
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| 74 | #define SSR_ADDR 0x0000101E |
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| 75 | #define MBR_ADDR 0x00001020 |
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| 76 | #define MLR_ADDR 0x00001022 |
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| 77 | #define PMBR_ADDR 0x00001024 |
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| 78 | #define PMLR_ADDR 0x00001026 |
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| 79 | /* Reserved 0x00001028 through 0x00001033 */ |
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| 80 | #define BSVIR_ADDR 0x00001034 |
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| 81 | #define BSIR_ADDR 0x00001036 |
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| 82 | /* Reserved 0x00001038 through 0x0000103D */ |
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| 83 | #define BCR_ADDR 0x0000103E |
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| 84 | #define EBCR_ADDR 0x00001040 |
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| 85 | #define SISR_ADDR 0x00001042 |
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| 86 | #define PBISR_ADDR 0x00001044 |
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| 87 | #define SBISR_ADDR 0x00001048 |
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| 88 | #define SACR_ADDR 0x0000104C |
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| 89 | #define PIRSR_ADDR 0x00001050 |
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| 90 | #define SIOBR_ADDR 0x00001054 |
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| 91 | #define SIOLR_ADDR 0x00001055 |
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| 92 | #define SMBR_ADDR 0x00001058 |
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| 93 | #define SMLR_ADDR 0x0000105A |
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| 94 | #define SDER_ADDR 0x0000105C |
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| 95 | /* Reserved 0x0000105E through 0x000011FFH */ |
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| 96 | |
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| 97 | /* Address Translation Unit 0000 1200H through 0000 12FFH */ |
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| 98 | #define ATUVID_ADDR 0x00001200 |
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| 99 | #define ATUDID_ADDR 0x00001202 |
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| 100 | #define PATUCMD_ADDR 0x00001204 |
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| 101 | #define PATUSR_ADDR 0x00001206 |
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| 102 | #define ATURID_ADDR 0x00001208 |
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| 103 | #define ATUCCR_ADDR 0x00001209 |
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| 104 | #define ATUCLSR_ADDR 0x0000120C |
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| 105 | #define ATULT_ADDR 0x0000120D |
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| 106 | #define ATUHTR_ADDR 0x0000120E |
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| 107 | #define ATUBISTR_ADDR 0x0000120F |
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| 108 | #define PIABAR_ADDR 0x00001210 |
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| 109 | /* Reserved 0x00001214 */ |
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| 110 | /* Reserved 0x00001218 */ |
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| 111 | /* Reserved 0x0000121C */ |
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| 112 | /* Reserved 0x00001220 */ |
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| 113 | /* Reserved 0x00001224 */ |
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| 114 | /* Reserved 0x00001228 */ |
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| 115 | #define ASVIR_ADDR 0x0000122C |
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| 116 | #define ASIR_ADDR 0x0000122E |
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| 117 | #define ERBAR_ADDR 0x00001230 |
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| 118 | /* Reserved 0x00001234 */ |
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| 119 | /* Reserved 0x00001238 */ |
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| 120 | #define ATUILR_ADDR 0x0000123C |
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| 121 | #define ATUIPR_ADDR 0x0000123D |
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| 122 | #define ATUMGNT_ADDR 0x0000123E |
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| 123 | #define ATUMLAT_ADDR 0x0000123F |
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| 124 | #define PIALR_ADDR 0x00001240 |
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| 125 | #define PIATVR_ADDR 0x00001244 |
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| 126 | #define SIABAR_ADDR 0x00001248 |
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| 127 | #define SIALR_ADDR 0x0000124C |
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| 128 | #define SIATVR_ADDR 0x00001250 |
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| 129 | #define POMWVR_ADDR 0x00001254 |
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| 130 | /* Reserved 0x00001258 */ |
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| 131 | #define POIOWVR_ADDR 0x0000125C |
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| 132 | #define PODWVR_ADDR 0x00001260 |
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| 133 | #define POUDR_ADDR 0x00001264 |
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| 134 | #define SOMWVR_ADDR 0x00001268 |
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| 135 | #define SOIOWVR_ADDR 0x0000126C |
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| 136 | /* Reserved 0x00001270 */ |
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| 137 | #define ERLR_ADDR 0x00001274 |
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| 138 | #define ERTVR_ADDR 0x00001278 |
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| 139 | /* Reserved 0x0000127C */ |
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| 140 | /* Reserved 0x00001280 */ |
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| 141 | /* Reserved 0x00001284 */ |
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| 142 | #define ATUCR_ADDR 0x00001288 |
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| 143 | /* Reserved 0x0000128C */ |
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| 144 | #define PATUISR_ADDR 0x00001290 |
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| 145 | #define SATUISR_ADDR 0x00001294 |
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| 146 | #define SATUCMD_ADDR 0x00001298 |
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| 147 | #define SATUSR_ADDR 0x0000129A |
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| 148 | #define SODWVR_ADDR 0x0000129C |
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| 149 | #define SOUDR_ADDR 0x000012A0 |
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| 150 | #define POCCAR_ADDR 0x000012A4 |
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| 151 | #define SOCCAR_ADDR 0x000012A8 |
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| 152 | #define POCCDR_ADDR 0x000012AC |
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| 153 | #define SOCCDR_ADDR 0x000012B0 |
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| 154 | /* Reserved 0x000012B4 through 0x000012FF */ |
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| 155 | |
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| 156 | /* Messaging Unit 0000 1300H through 0000 13FFH */ |
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| 157 | #define ARSR_ADDR 0x00001300 |
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| 158 | /* Reserved 0x00001304 */ |
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| 159 | #define AWR_ADDR 0x00001308 |
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| 160 | /* Reserved 0x0000130C */ |
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| 161 | #define IMR0_ADDR 0x00001310 |
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| 162 | #define IMR1_ADDR 0x00001314 |
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| 163 | #define OMR0_ADDR 0x00001318 |
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| 164 | #define OMR1_ADDR 0x0000131C |
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| 165 | #define IDR_ADDR 0x00001320 |
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| 166 | #define IISR_ADDR 0x00001324 |
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| 167 | #define IIMR_ADDR 0x00001328 |
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| 168 | #define ODR_ADDR 0x0000132C |
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| 169 | #define OISR_ADDR 0x00001330 |
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| 170 | #define OIMR_ADDR 0x00001334 |
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| 171 | /* Reserved 0x00001338 through 0x0000134F */ |
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| 172 | #define MUCR_ADDR 0x00001350 |
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| 173 | #define QBAR_ADDR 0x00001354 |
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| 174 | /* Reserved 0x00001358 */ |
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| 175 | /* Reserved 0x0000135C */ |
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| 176 | #define IFHPR_ADDR 0x00001360 |
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| 177 | #define IFTPR_ADDR 0x00001364 |
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| 178 | #define IPHPR_ADDR 0x00001368 |
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| 179 | #define IPTPR_ADDR 0x0000136C |
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| 180 | #define OFHPR_ADDR 0x00001370 |
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| 181 | #define OFTPR_ADDR 0x00001374 |
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| 182 | #define OPHPR_ADDR 0x00001378 |
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| 183 | #define OPTPR_ADDR 0x0000137C |
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| 184 | #define IAR_ADDR 0x00001380 |
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| 185 | /* Reserved 0x00001384 through 0x000013FF */ |
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| 186 | |
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| 187 | /* DMA Controller 0000 1400H through 0000 14FFH */ |
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| 188 | #define CCR0_ADDR 0x00001400 |
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| 189 | #define CSR0_ADDR 0x00001404 |
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| 190 | /* Reserved 0x00001408 */ |
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| 191 | #define DAR0_ADDR 0x0000140C |
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| 192 | #define NDAR0_ADDR 0x00001410 |
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| 193 | #define PADR0_ADDR 0x00001414 |
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| 194 | #define PUADR0_ADDR 0x00001418 |
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| 195 | #define LADR0_ADDR 0x0000141C |
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| 196 | #define BCR0_ADDR 0x00001420 |
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| 197 | #define DCR0_ADDR 0x00001424 |
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| 198 | /* Reserved 0x00001428 through 0x0000143F */ |
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| 199 | #define CCR1_ADDR 0x00001440 |
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| 200 | #define CSR1_ADDR 0x00001444 |
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| 201 | /* Reserved 0x00001448 */ |
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| 202 | #define DAR1_ADDR 0x0000144C |
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| 203 | #define NDAR1_ADDR 0x00001450 |
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| 204 | #define PADR1_ADDR 0x00001454 |
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| 205 | #define PUADR1_ADDR 0x00001458 |
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| 206 | #define LADR1_ADDR 0x0000145C |
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| 207 | #define BCR1_ADDR 0x00001460 |
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| 208 | #define DCR1_ADDR 0x00001464 |
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| 209 | /* Reserved 0x00001468 through 0x0000147F */ |
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| 210 | #define CCR2_ADDR 0x00001480 |
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| 211 | #define CSR2_ADDR 0x00001484 |
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| 212 | /* Reserved 0x00001488 */ |
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| 213 | #define DAR2_ADDR 0x0000148C |
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| 214 | #define NDAR2_ADDR 0x00001490 |
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| 215 | #define PADR2_ADDR 0x00001494 |
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| 216 | #define PUADR2_ADDR 0x00001498 |
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| 217 | #define LADR2_ADDR 0x0000149C |
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| 218 | #define BCR2_ADDR 0x000014A0 |
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| 219 | #define DCR2_ADDR 0x000014A4 |
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| 220 | /* Reserved 0x000014A8 through 0x000014FF */ |
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| 221 | |
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| 222 | /* Memory Controller 0000 1500H through 0000 15FFH */ |
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| 223 | #define MBCR_ADDR 0x00001500 |
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| 224 | #define MBBAR0_ADDR 0x00001504 |
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| 225 | #define MBRWS0_ADDR 0x00001508 |
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| 226 | #define MBWWS0_ADDR 0x0000150C |
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| 227 | #define MBBAR1_ADDR 0x00001510 |
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| 228 | #define MBRWS1_ADDR 0x00001514 |
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| 229 | #define MBWWS1_ADDR 0x00001518 |
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| 230 | #define DBCR_ADDR 0x0000151C |
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| 231 | #define DBAR_ADDR 0x00001520 |
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| 232 | #define DRWS_ADDR 0x00001524 |
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| 233 | #define DWWS_ADDR 0x00001528 |
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| 234 | #define DRIR_ADDR 0x0000152C |
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| 235 | #define DPER_ADDR 0x00001530 |
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| 236 | #define BMER_ADDR 0x00001534 |
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| 237 | #define MEAR_ADDR 0x00001538 |
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| 238 | #define LPISR_ADDR 0x0000153C |
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| 239 | /* Reserved 0x00001540 through 0x000015FF */ |
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| 240 | |
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| 241 | /* Local Bus Arbitration Unit 0000 1600H through 0000 167FH |
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| 242 | */ |
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| 243 | #define LBACR_ADDR 0x00001600 |
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| 244 | #define LBALCR_ADDR 0x00001604 |
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| 245 | /* Reserved 0x00001608 through 0x0000167F */ |
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| 246 | |
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| 247 | /* I2C Bus Interface Unit 0000 1680H through 0000 16FFH */ |
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| 248 | #define ICR_ADDR 0x00001680 |
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| 249 | #define ISR_ADDR 0x00001684 |
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| 250 | #define ISAR_ADDR 0x00001688 |
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| 251 | #define IDBR_ADDR 0x0000168C |
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| 252 | #define ICCR_ADDR 0x00001690 |
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| 253 | /* Reserved 0x00001694 through 0x000016FF */ |
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| 254 | |
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| 255 | /* PCI And Peripheral Interrupt Controller 0000 1700H through |
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| 256 | 0000 177FH */ |
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| 257 | #define NISR_ADDR 0x00001700 |
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| 258 | #define X7ISR_ADDR 0x00001704 |
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| 259 | #define X6ISR_ADDR 0x00001708 |
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| 260 | #define PDDIR_ADDR 0x00001710 |
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| 261 | /* Reserved 0x00001714 through 0x0000177F */ |
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| 262 | |
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| 263 | /* APIC Bus Interface Unit 0000 1780H through 0000 17FFH */ |
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| 264 | #define APICIDR_ADDR 0x00001780 |
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| 265 | #define APICARBID_ADDR 0x00001784 |
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| 266 | #define EVR_ADDR 0x00001788 |
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| 267 | #define IMR_ADDR 0x0000178C |
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| 268 | #define APICCSR_ADDR 0x00001790 |
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| 269 | /* Reserved 0x00001794 through 0x000017FF */ |
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| 270 | |
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| 271 | /* Byte order bit for region configuration */ |
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| 272 | /* Set to Little Endian for the 80960RP*/ |
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| 273 | #define I960RP_BYTE_ORDER I960RP_BIG_ENDIAN(0) |
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| 274 | #define I960RP_BUS_WIDTH(bw) ((bw==16)?(1<<22):(0)) | ((bw==32)?(2<<22):(0)) |
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| 275 | #define I960RP_BIG_ENDIAN(on) ((on)?(0x1<<31):0) |
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| 276 | #define I960RP_BYTE_N(n,data) (((unsigned)(data) >> (n*8)) & 0xFF) |
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| 277 | #define I960RP_BUS_WIDTH_8 0 |
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| 278 | #define I960RP_BUS_WIDTH_16 (1<<22) |
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| 279 | #define I960RP_BUS_WIDTH_32 (1<<23) |
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| 280 | |
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| 281 | |
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| 282 | /* ATU Register Definitions */ |
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| 283 | |
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| 284 | #define ATUCR_SECOUTEN 0x4 |
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| 285 | #define ATUCR_PRIOUTEN 0x2 |
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| 286 | #define ATUCR_DADRSELEN 0x100 |
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| 287 | #define ATUCR_SECDADREN 0x80 |
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| 288 | #define AUTCR_SECERRINTEN 0x20 |
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| 289 | #define AUTCR_PRIERRINTEN 0x10 |
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| 290 | |
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| 291 | #define ATUSCMD_IOEN 0x1 |
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| 292 | #define ATUSCMD_MEMEN 0x2 |
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| 293 | #define ATUSCMD_BUSMSTEN 0x4 |
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| 294 | |
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| 295 | #define ATUPCMD_IOEN 0x1 |
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| 296 | #define ATUPCMD_MEMEN 0x2 |
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| 297 | #define ATUPCMD_BUSMSTEN 0x4 |
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| 298 | |
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| 299 | /* EBCR Register Definitions */ |
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| 300 | #define EBCR_CCR_MASK 0x4 |
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| 301 | |
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| 302 | #define rp_readreg32( x) ( *((unsigned int *) x)) |
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| 303 | #define rp_writereg32( x, v) ( *((unsigned int *) x) = v) |
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| 304 | #define rp_readreg16( x) ( *((unsigned short *) x)) |
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| 305 | #define rp_writereg16( x, v) ( *((unsigned short *) x) = v) |
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| 306 | #define rp_readreg8( x) ( *((unsigned char *) x)) |
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| 307 | #define rp_writereg8( x, v) ( *((unsigned char *) x) = v) |
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| 308 | |
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| 309 | |
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| 310 | /* i960 Memory Map values */ |
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| 311 | |
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| 312 | #define RP_PRI_IO_WIND_BASE 0x90000000 |
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| 313 | #define RP_SEC_IO_WIND_BASE 0x90010000 |
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| 314 | #define RP_SEC_MEM_WIND_BASE 0x88000000 |
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| 315 | #define RP_PRI_MEM_WIND_BASE 0x80000000 |
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| 316 | |
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| 317 | #endif |
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| 318 | /* end of include file */ |
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