source: rtems/c/src/exec/score/cpu/i960/i960RP.h @ ae7325bd

4.104.114.84.95
Last change on this file since ae7325bd was ae7325bd, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 27, 1999 at 5:25:53 PM

rxgen960 now compiles -- may not link.

  • Property mode set to 100644
File size: 9.5 KB
Line 
1/*
2 *  i960RP Related Definitions.
3 *
4 *  NOTE:  There is some commonality with the JX series which is
5 *         not currently supported by RTEMS.
6 *
7 *  $Id$
8 */
9
10#ifndef __I960RP_h
11#define __I960RP_h
12
13/*----------------------------------------------------------*/
14/*  Example 6. Include File (evrp.h)                        */
15/*----------------------------------------------------------*/
16/* Define JX Core memory mapped register addresses */
17/* Common to Jx and RP: */
18#define    DLMCON_ADDR    0xff008100
19#define    LMAR0_ADDR     0xff008108
20#define    LMMR0_ADDR     0xff00810c
21#define    LMAR1_ADDR     0xff008110
22#define    LMMR1_ADDR     0xff008114
23#define    IPB0_ADDR      0xff008400
24#define    IPB1_ADDR      0xff008404
25#define    DAB0_ADDR      0xff008420
26#define    DAB1_ADDR      0xff008424
27#define    BPCON_ADDR     0xff008440
28#define    IPND_ADDR      0xff008500
29#define    IMSK_ADDR      0xff008504
30#define    ICON_ADDR      0xff008510
31#define    IMAP0_ADDR     0xff008520
32#define    IMAP1_ADDR     0xff008524
33#define    IMAP2_ADDR     0xff008528
34#define    PMCON0_ADDR    0xff008600
35#define    PMCON2_ADDR    0xff008608
36#define    PMCON4_ADDR    0xff008610
37#define    PMCON6_ADDR    0xff008618
38#define    PMCON8_ADDR    0xff008620
39#define    PMCON10_ADDR   0xff008628
40#define    PMCON12_ADDR   0xff008630
41#define    PMCON14_ADDR   0xff008638
42#define    BCON_ADDR      0xff0086fc
43#define    PRCB_ADDR      0xff008700
44#define    ISP_ADDR       0xff008704
45#define    SSP_ADDR       0xff008708
46#define    DEVID_ADDR     0xff008710
47#define    TRR0_ADDR      0xff000300
48#define    TCR0_ADDR      0xff000304
49#define    TMR0_ADDR      0xff000308
50#define    TRR1_ADDR      0xff000310
51#define    TCR1_ADDR      0xff000314
52#define    TMR1_ADDR      0xff000318
53
54/* RP-only addresses: */
55/* RP MMRs */
56
57/* PCI-to-PCI Bridge Unit 0000 1000H through 0000 10FFH */
58#define VIDR_ADDR 0x00001000
59#define DIDR_ADDR 0x00001002
60#define PCMDR_ADDR 0x00001004
61#define PSR_ADDR 0x00001006
62#define RIDR_ADDR 0x00001008
63#define CCR_ADDR 0x00001009
64#define CLSR_ADDR 0x0000100C
65#define PLTR_ADDR 0x0000100D
66#define HTR_ADDR 0x0000100E
67/* Reserved 0x0000100F through  0x00001017 */
68#define PBNR_ADDR 0x00001018
69#define SBNR_ADDR 0x00001019
70#define SUBBNR_ADDR 0x0000101A
71#define SLTR_ADDR 0x0000101B
72#define IOBR_ADDR 0x0000101C
73#define IOLR_ADDR 0x0000101D
74#define SSR_ADDR 0x0000101E
75#define MBR_ADDR 0x00001020
76#define MLR_ADDR 0x00001022
77#define PMBR_ADDR 0x00001024
78#define PMLR_ADDR 0x00001026
79/* Reserved 0x00001028 through 0x00001033 */
80#define BSVIR_ADDR 0x00001034
81#define BSIR_ADDR 0x00001036
82/* Reserved 0x00001038 through 0x0000103D */
83#define BCR_ADDR 0x0000103E
84#define EBCR_ADDR 0x00001040
85#define SISR_ADDR 0x00001042
86#define PBISR_ADDR 0x00001044
87#define SBISR_ADDR 0x00001048
88#define SACR_ADDR 0x0000104C
89#define PIRSR_ADDR 0x00001050
90#define SIOBR_ADDR 0x00001054
91#define SIOLR_ADDR 0x00001055
92#define SMBR_ADDR 0x00001058
93#define SMLR_ADDR 0x0000105A
94#define SDER_ADDR 0x0000105C
95/* Reserved 0x0000105E through 0x000011FFH */
96
97/* Address Translation Unit 0000 1200H through 0000 12FFH */
98#define ATUVID_ADDR 0x00001200
99#define ATUDID_ADDR 0x00001202
100#define PATUCMD_ADDR 0x00001204
101#define PATUSR_ADDR 0x00001206
102#define ATURID_ADDR 0x00001208
103#define ATUCCR_ADDR 0x00001209
104#define ATUCLSR_ADDR 0x0000120C
105#define ATULT_ADDR 0x0000120D
106#define ATUHTR_ADDR 0x0000120E
107#define ATUBISTR_ADDR 0x0000120F
108#define PIABAR_ADDR 0x00001210
109/* Reserved 0x00001214 */
110/* Reserved 0x00001218 */
111/* Reserved 0x0000121C */
112/* Reserved 0x00001220 */
113/* Reserved 0x00001224 */
114/* Reserved 0x00001228 */
115#define ASVIR_ADDR 0x0000122C
116#define ASIR_ADDR 0x0000122E
117#define ERBAR_ADDR 0x00001230
118/* Reserved 0x00001234 */
119/* Reserved 0x00001238 */
120#define ATUILR_ADDR 0x0000123C
121#define ATUIPR_ADDR 0x0000123D
122#define ATUMGNT_ADDR 0x0000123E
123#define ATUMLAT_ADDR 0x0000123F
124#define PIALR_ADDR 0x00001240
125#define PIATVR_ADDR 0x00001244
126#define SIABAR_ADDR 0x00001248
127#define SIALR_ADDR 0x0000124C
128#define SIATVR_ADDR 0x00001250
129#define POMWVR_ADDR 0x00001254
130/* Reserved 0x00001258 */
131#define POIOWVR_ADDR 0x0000125C
132#define PODWVR_ADDR 0x00001260
133#define POUDR_ADDR 0x00001264
134#define SOMWVR_ADDR 0x00001268
135#define SOIOWVR_ADDR 0x0000126C
136/* Reserved 0x00001270 */
137#define ERLR_ADDR 0x00001274
138#define ERTVR_ADDR 0x00001278
139/* Reserved 0x0000127C */
140/* Reserved 0x00001280 */
141/* Reserved 0x00001284 */
142#define ATUCR_ADDR 0x00001288
143/* Reserved 0x0000128C */
144#define PATUISR_ADDR 0x00001290
145#define SATUISR_ADDR 0x00001294
146#define SATUCMD_ADDR 0x00001298
147#define SATUSR_ADDR 0x0000129A
148#define SODWVR_ADDR 0x0000129C
149#define SOUDR_ADDR 0x000012A0
150#define POCCAR_ADDR 0x000012A4
151#define SOCCAR_ADDR 0x000012A8
152#define POCCDR_ADDR 0x000012AC
153#define SOCCDR_ADDR 0x000012B0
154/* Reserved 0x000012B4 through 0x000012FF */
155
156/* Messaging Unit 0000 1300H through 0000 13FFH */
157#define ARSR_ADDR 0x00001300
158/* Reserved 0x00001304 */
159#define AWR_ADDR 0x00001308
160/* Reserved 0x0000130C */
161#define IMR0_ADDR 0x00001310
162#define IMR1_ADDR 0x00001314
163#define OMR0_ADDR 0x00001318
164#define OMR1_ADDR 0x0000131C
165#define IDR_ADDR 0x00001320
166#define IISR_ADDR 0x00001324
167#define IIMR_ADDR 0x00001328
168#define ODR_ADDR 0x0000132C
169#define OISR_ADDR 0x00001330
170#define OIMR_ADDR 0x00001334
171/* Reserved 0x00001338 through 0x0000134F */
172#define MUCR_ADDR 0x00001350
173#define QBAR_ADDR 0x00001354
174/* Reserved 0x00001358 */
175/* Reserved 0x0000135C */
176#define IFHPR_ADDR 0x00001360
177#define IFTPR_ADDR 0x00001364
178#define IPHPR_ADDR 0x00001368
179#define IPTPR_ADDR 0x0000136C
180#define OFHPR_ADDR 0x00001370
181#define OFTPR_ADDR 0x00001374
182#define OPHPR_ADDR 0x00001378
183#define OPTPR_ADDR 0x0000137C
184#define IAR_ADDR 0x00001380
185/* Reserved 0x00001384 through 0x000013FF */
186
187/* DMA Controller 0000 1400H through 0000 14FFH */
188#define CCR0_ADDR 0x00001400
189#define CSR0_ADDR 0x00001404
190/* Reserved 0x00001408 */
191#define DAR0_ADDR 0x0000140C
192#define NDAR0_ADDR 0x00001410
193#define PADR0_ADDR 0x00001414
194#define PUADR0_ADDR 0x00001418
195#define LADR0_ADDR 0x0000141C
196#define BCR0_ADDR 0x00001420
197#define DCR0_ADDR 0x00001424
198/* Reserved 0x00001428 through 0x0000143F */
199#define CCR1_ADDR 0x00001440
200#define CSR1_ADDR 0x00001444
201/* Reserved 0x00001448 */
202#define DAR1_ADDR 0x0000144C
203#define NDAR1_ADDR 0x00001450
204#define PADR1_ADDR 0x00001454
205#define PUADR1_ADDR 0x00001458
206#define LADR1_ADDR 0x0000145C
207#define BCR1_ADDR 0x00001460
208#define DCR1_ADDR 0x00001464
209/* Reserved 0x00001468 through 0x0000147F */
210#define CCR2_ADDR 0x00001480
211#define CSR2_ADDR 0x00001484
212/* Reserved 0x00001488 */
213#define DAR2_ADDR 0x0000148C
214#define NDAR2_ADDR 0x00001490
215#define PADR2_ADDR 0x00001494
216#define PUADR2_ADDR 0x00001498
217#define LADR2_ADDR 0x0000149C
218#define BCR2_ADDR 0x000014A0
219#define DCR2_ADDR 0x000014A4
220/* Reserved 0x000014A8 through 0x000014FF */
221
222/* Memory Controller 0000 1500H through 0000 15FFH */
223#define MBCR_ADDR 0x00001500
224#define MBBAR0_ADDR 0x00001504
225#define MBRWS0_ADDR 0x00001508
226#define MBWWS0_ADDR 0x0000150C
227#define MBBAR1_ADDR 0x00001510
228#define MBRWS1_ADDR 0x00001514
229#define MBWWS1_ADDR 0x00001518
230#define DBCR_ADDR 0x0000151C
231#define DBAR_ADDR 0x00001520
232#define DRWS_ADDR 0x00001524
233#define DWWS_ADDR 0x00001528
234#define DRIR_ADDR 0x0000152C
235#define DPER_ADDR 0x00001530
236#define BMER_ADDR 0x00001534
237#define MEAR_ADDR 0x00001538
238#define LPISR_ADDR 0x0000153C
239/* Reserved 0x00001540 through 0x000015FF */
240
241/* Local Bus Arbitration Unit 0000 1600H through 0000 167FH
242*/
243#define LBACR_ADDR 0x00001600
244#define LBALCR_ADDR 0x00001604
245/* Reserved 0x00001608 through 0x0000167F */
246
247/* I2C Bus Interface Unit 0000 1680H through 0000 16FFH */
248#define ICR_ADDR 0x00001680
249#define ISR_ADDR 0x00001684
250#define ISAR_ADDR 0x00001688
251#define IDBR_ADDR 0x0000168C
252#define ICCR_ADDR 0x00001690
253/* Reserved 0x00001694 through 0x000016FF */
254
255/* PCI And Peripheral Interrupt Controller 0000 1700H through
2560000 177FH */
257#define NISR_ADDR 0x00001700
258#define X7ISR_ADDR 0x00001704
259#define X6ISR_ADDR 0x00001708
260#define PDDIR_ADDR 0x00001710
261/* Reserved 0x00001714 through 0x0000177F */
262
263/* APIC Bus Interface Unit 0000 1780H through 0000 17FFH */
264#define APICIDR_ADDR 0x00001780
265#define APICARBID_ADDR 0x00001784
266#define EVR_ADDR 0x00001788
267#define IMR_ADDR 0x0000178C
268#define APICCSR_ADDR 0x00001790
269/* Reserved 0x00001794 through 0x000017FF  */
270
271/* Byte order bit for region configuration */
272/* Set to Little Endian for the 80960RP*/
273#define I960RP_BYTE_ORDER I960RP_BIG_ENDIAN(0)
274#define I960RP_BUS_WIDTH(bw)  ((bw==16)?(1<<22):(0)) | ((bw==32)?(2<<22):(0))
275#define I960RP_BIG_ENDIAN(on) ((on)?(0x1<<31):0)
276#define I960RP_BYTE_N(n,data)  (((unsigned)(data) >> (n*8)) & 0xFF)
277#define I960RP_BUS_WIDTH_8 0
278#define I960RP_BUS_WIDTH_16 (1<<22)
279#define I960RP_BUS_WIDTH_32 (1<<23)
280
281
282/* ATU Register Definitions */
283
284#define ATUCR_SECOUTEN 0x4
285#define ATUCR_PRIOUTEN 0x2
286#define ATUCR_DADRSELEN  0x100
287#define ATUCR_SECDADREN  0x80
288#define AUTCR_SECERRINTEN 0x20
289#define AUTCR_PRIERRINTEN 0x10
290
291#define ATUSCMD_IOEN 0x1
292#define ATUSCMD_MEMEN 0x2
293#define ATUSCMD_BUSMSTEN 0x4
294
295#define ATUPCMD_IOEN 0x1
296#define ATUPCMD_MEMEN 0x2
297#define ATUPCMD_BUSMSTEN 0x4
298
299/* EBCR Register Definitions */
300#define EBCR_CCR_MASK   0x4
301
302#define rp_readreg32( x) ( *((unsigned int *) x))
303#define rp_writereg32( x, v) ( *((unsigned int *) x) = v)
304#define rp_readreg16( x) ( *((unsigned short *) x))
305#define rp_writereg16( x, v) ( *((unsigned short *) x) = v)
306#define rp_readreg8( x) ( *((unsigned char *) x))
307#define rp_writereg8( x, v) ( *((unsigned char *) x) = v)
308
309
310/* i960 Memory Map values */
311
312#define RP_PRI_IO_WIND_BASE     0x90000000
313#define RP_SEC_IO_WIND_BASE     0x90010000
314#define RP_SEC_MEM_WIND_BASE    0x88000000
315#define RP_PRI_MEM_WIND_BASE    0x80000000
316
317#endif
318/* end of include file */
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