1 | /* i960.h |
---|
2 | * |
---|
3 | * This include file contains information pertaining to the Intel |
---|
4 | * i960 processor family. |
---|
5 | * |
---|
6 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
---|
7 | * On-Line Applications Research Corporation (OAR). |
---|
8 | * All rights assigned to U.S. Government, 1994. |
---|
9 | * |
---|
10 | * This material may be reproduced by or for the U.S. Government pursuant |
---|
11 | * to the copyright license under the clause at DFARS 252.227-7013. This |
---|
12 | * notice must appear in all copies of this file and its derivatives. |
---|
13 | * |
---|
14 | * $Id$ |
---|
15 | */ |
---|
16 | |
---|
17 | #ifndef __i960_h |
---|
18 | #define __i960_h |
---|
19 | |
---|
20 | #ifdef __cplusplus |
---|
21 | extern "C" { |
---|
22 | #endif |
---|
23 | |
---|
24 | /* |
---|
25 | * The following define the CPU Family and Model within the family |
---|
26 | * |
---|
27 | * NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced |
---|
28 | * with the name of the appropriate macro for this target CPU. |
---|
29 | */ |
---|
30 | |
---|
31 | #ifdef i960 |
---|
32 | #undef i960 |
---|
33 | #endif |
---|
34 | #define i960 |
---|
35 | |
---|
36 | #ifdef REPLACE_THIS_WITH_THE_CPU_MODEL |
---|
37 | #undef REPLACE_THIS_WITH_THE_CPU_MODEL |
---|
38 | #endif |
---|
39 | #define REPLACE_THIS_WITH_THE_CPU_MODEL |
---|
40 | |
---|
41 | #ifdef REPLACE_THIS_WITH_THE_BSP |
---|
42 | #undef REPLACE_THIS_WITH_THE_BSP |
---|
43 | #endif |
---|
44 | #define REPLACE_THIS_WITH_THE_BSP |
---|
45 | |
---|
46 | /* |
---|
47 | * This file contains the information required to build |
---|
48 | * RTEMS for a particular member of the Intel i960 |
---|
49 | * family. It does this by setting variables to indicate |
---|
50 | * which implementation dependent features are present |
---|
51 | * in a particular member of the family. |
---|
52 | * |
---|
53 | * NOTE: For now i960 is really the i960ca. eventually need |
---|
54 | * to put in at least support for FPU. |
---|
55 | */ |
---|
56 | |
---|
57 | #if defined(i960ca) |
---|
58 | |
---|
59 | #define CPU_MODEL_NAME "i960ca" |
---|
60 | #define I960_HAS_FPU 0 |
---|
61 | |
---|
62 | #else |
---|
63 | |
---|
64 | #error "Unsupported CPU Model" |
---|
65 | |
---|
66 | #endif |
---|
67 | |
---|
68 | /* |
---|
69 | * Define the name of the CPU family. |
---|
70 | */ |
---|
71 | |
---|
72 | #define CPU_NAME "Intel i960" |
---|
73 | |
---|
74 | #ifndef ASM |
---|
75 | |
---|
76 | /* |
---|
77 | * XXX should have an ifdef here and have stuff for the other |
---|
78 | * XXX family members... |
---|
79 | */ |
---|
80 | |
---|
81 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
---|
82 | |
---|
83 | /* i960CA control structures */ |
---|
84 | |
---|
85 | /* Intel i960CA Control Table */ |
---|
86 | |
---|
87 | typedef struct { |
---|
88 | /* Control Group 0 */ |
---|
89 | unsigned int ipb0; /* IP breakpoint 0 */ |
---|
90 | unsigned int ipb1; /* IP breakpoint 1 */ |
---|
91 | unsigned int dab0; /* data address breakpoint 0 */ |
---|
92 | unsigned int dab1; /* data address breakpoint 1 */ |
---|
93 | /* Control Group 1 */ |
---|
94 | unsigned int imap0; /* interrupt map 0 */ |
---|
95 | unsigned int imap1; /* interrupt map 1 */ |
---|
96 | unsigned int imap2; /* interrupt map 2 */ |
---|
97 | unsigned int icon; /* interrupt control */ |
---|
98 | /* Control Group 2 */ |
---|
99 | unsigned int mcon0; /* memory region 0 configuration */ |
---|
100 | unsigned int mcon1; /* memory region 1 configuration */ |
---|
101 | unsigned int mcon2; /* memory region 2 configuration */ |
---|
102 | unsigned int mcon3; /* memory region 3 configuration */ |
---|
103 | /* Control Group 3 */ |
---|
104 | unsigned int mcon4; /* memory region 4 configuration */ |
---|
105 | unsigned int mcon5; /* memory region 5 configuration */ |
---|
106 | unsigned int mcon6; /* memory region 6 configuration */ |
---|
107 | unsigned int mcon7; /* memory region 7 configuration */ |
---|
108 | /* Control Group 4 */ |
---|
109 | unsigned int mcon8; /* memory region 8 configuration */ |
---|
110 | unsigned int mcon9; /* memory region 9 configuration */ |
---|
111 | unsigned int mcon10; /* memory region 10 configuration */ |
---|
112 | unsigned int mcon11; /* memory region 11 configuration */ |
---|
113 | /* Control Group 5 */ |
---|
114 | unsigned int mcon12; /* memory region 12 configuration */ |
---|
115 | unsigned int mcon13; /* memory region 13 configuration */ |
---|
116 | unsigned int mcon14; /* memory region 14 configuration */ |
---|
117 | unsigned int mcon15; /* memory region 15 configuration */ |
---|
118 | /* Control Group 6 */ |
---|
119 | unsigned int bpcon; /* breakpoint control */ |
---|
120 | unsigned int tc; /* trace control */ |
---|
121 | unsigned int bcon; /* bus configuration control */ |
---|
122 | unsigned int reserved; /* reserved */ |
---|
123 | } i960ca_control_table; |
---|
124 | |
---|
125 | /* Intel i960CA Processor Control Block */ |
---|
126 | |
---|
127 | typedef struct { |
---|
128 | unsigned int *fault_tbl; /* fault table base address */ |
---|
129 | i960ca_control_table |
---|
130 | *control_tbl; /* control table base address */ |
---|
131 | unsigned int initial_ac; /* AC register initial value */ |
---|
132 | unsigned int fault_config; /* fault configuration word */ |
---|
133 | void **intr_tbl; /* interrupt table base address */ |
---|
134 | void *sys_proc_tbl; /* system procedure table |
---|
135 | base address */ |
---|
136 | unsigned int reserved; /* reserved */ |
---|
137 | unsigned int *intr_stack; /* interrupt stack pointer */ |
---|
138 | unsigned int ins_cache_cfg; /* instruction cache |
---|
139 | configuration word */ |
---|
140 | unsigned int reg_cache_cfg; /* register cache configuration word */ |
---|
141 | } i960ca_PRCB; |
---|
142 | |
---|
143 | #endif |
---|
144 | |
---|
145 | /* |
---|
146 | * Interrupt Level Routines |
---|
147 | */ |
---|
148 | |
---|
149 | #define i960_disable_interrupts( oldlevel ) \ |
---|
150 | { (oldlevel) = 0x1f0000; \ |
---|
151 | asm volatile ( "modpc 0,%1,%1" \ |
---|
152 | : "=d" ((oldlevel)) \ |
---|
153 | : "0" ((oldlevel)) ); \ |
---|
154 | } |
---|
155 | |
---|
156 | #define i960_enable_interrupts( oldlevel ) \ |
---|
157 | { unsigned int _mask = 0x1f0000; \ |
---|
158 | asm volatile ( "modpc 0,%0,%1" \ |
---|
159 | : "=d" (_mask), "=d" ((oldlevel)) \ |
---|
160 | : "0" (_mask), "1" ((oldlevel)) ); \ |
---|
161 | } |
---|
162 | |
---|
163 | #define i960_flash_interrupts( oldlevel ) \ |
---|
164 | { unsigned int _mask = 0x1f0000; \ |
---|
165 | asm volatile ( "modpc 0,%0,%1 ; \ |
---|
166 | mov %0,%1 ; \ |
---|
167 | modpc 0,%0,%1" \ |
---|
168 | : "=d" (_mask), "=d" ((oldlevel)) \ |
---|
169 | : "0" (_mask), "1" ((oldlevel)) ); \ |
---|
170 | } |
---|
171 | |
---|
172 | #define i960_get_interrupt_level( _level ) \ |
---|
173 | { \ |
---|
174 | i960_disable_interrupts( _level ); \ |
---|
175 | i960_enable_interrupts( _level ); \ |
---|
176 | (_level) = ((_level) & 0x1f0000) >> 16; \ |
---|
177 | } while ( 0 ) |
---|
178 | |
---|
179 | #define i960_atomic_modify( mask, addr, prev ) \ |
---|
180 | { register unsigned int _mask = (mask); \ |
---|
181 | register unsigned int *_addr = (unsigned int *)(addr); \ |
---|
182 | asm volatile( "atmod %0,%1,%1" \ |
---|
183 | : "=d" (_addr), "=d" (_mask) \ |
---|
184 | : "0" (_addr), "1" (_mask) ); \ |
---|
185 | (prev) = _mask; \ |
---|
186 | } |
---|
187 | |
---|
188 | |
---|
189 | #define atomic_modify( _mask, _address, _previous ) \ |
---|
190 | i960_atomic_modify( _mask, _address, _previous ) |
---|
191 | |
---|
192 | #define i960_enable_tracing() \ |
---|
193 | { register unsigned int _pc = 0x1; \ |
---|
194 | asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \ |
---|
195 | } |
---|
196 | |
---|
197 | #define i960_unmask_intr( xint ) \ |
---|
198 | { register unsigned int _mask= (1<<(xint)); \ |
---|
199 | asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \ |
---|
200 | } |
---|
201 | |
---|
202 | #define i960_mask_intr( xint ) \ |
---|
203 | { register unsigned int _mask= (1<<(xint)); \ |
---|
204 | asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \ |
---|
205 | } |
---|
206 | |
---|
207 | #define i960_clear_intr( xint ) \ |
---|
208 | { register unsigned int _xint=(xint); \ |
---|
209 | asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \ |
---|
210 | bbs %0,sf0, loop_til_cleared" \ |
---|
211 | : "=d" (_xint) : "0" (_xint) ); \ |
---|
212 | } |
---|
213 | |
---|
214 | #define i960_reload_ctl_group( group ) \ |
---|
215 | { register int _cmd = ((group)|0x400) ; \ |
---|
216 | asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \ |
---|
217 | } |
---|
218 | |
---|
219 | #define i960_cause_intr( intr ) \ |
---|
220 | { register int _intr = (intr); \ |
---|
221 | asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \ |
---|
222 | } |
---|
223 | |
---|
224 | #define i960_soft_reset( prcb ) \ |
---|
225 | { register i960ca_PRCB *_prcb = (prcb); \ |
---|
226 | register unsigned int *_next=0; \ |
---|
227 | register unsigned int _cmd = 0x30000; \ |
---|
228 | asm volatile( "lda next,%1; \ |
---|
229 | sysctl %0,%1,%2; \ |
---|
230 | next: mov g0,g0" \ |
---|
231 | : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ |
---|
232 | : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ |
---|
233 | } |
---|
234 | |
---|
235 | static inline unsigned int i960_pend_intrs() |
---|
236 | { register unsigned int _intr=0; |
---|
237 | asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) ); |
---|
238 | return ( _intr ); |
---|
239 | } |
---|
240 | |
---|
241 | static inline unsigned int i960_mask_intrs() |
---|
242 | { register unsigned int _intr=0; |
---|
243 | asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) ); |
---|
244 | return( _intr ); |
---|
245 | } |
---|
246 | |
---|
247 | static inline unsigned int i960_get_fp() |
---|
248 | { register unsigned int _fp=0; |
---|
249 | asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) ); |
---|
250 | return ( _fp ); |
---|
251 | } |
---|
252 | |
---|
253 | /* |
---|
254 | * The following routine swaps the endian format of an unsigned int. |
---|
255 | * It must be static because it is referenced indirectly. |
---|
256 | * |
---|
257 | * This version is based on code presented in Vol. 4, No. 4 of |
---|
258 | * Insight 960. It is certainly something you wouldn't think |
---|
259 | * of on your own. |
---|
260 | */ |
---|
261 | |
---|
262 | static inline unsigned int CPU_swap_u32( |
---|
263 | unsigned int value |
---|
264 | ) |
---|
265 | { |
---|
266 | register unsigned int to_swap = value; |
---|
267 | register unsigned int temp = 0xFF00FF00; |
---|
268 | register unsigned int swapped = 0; |
---|
269 | |
---|
270 | /* to_swap swapped */ |
---|
271 | asm volatile ( "rotate 16,%0,%2 ;" /* 0x12345678 0x56781234 */ |
---|
272 | "modify %1,%0,%2 ;" /* 0x12345678 0x12785634 */ |
---|
273 | "rotate 8,%2,%2" /* 0x12345678 0x78563412 */ |
---|
274 | : "=r" (to_swap), "=r" (temp), "=r" (swapped) |
---|
275 | : "0" (to_swap), "1" (temp), "2" (swapped) |
---|
276 | ); |
---|
277 | return( swapped ); |
---|
278 | } |
---|
279 | |
---|
280 | #ifdef __cplusplus |
---|
281 | } |
---|
282 | #endif |
---|
283 | |
---|
284 | #endif /* !ASM */ |
---|
285 | |
---|
286 | #endif |
---|
287 | /* end of include file */ |
---|