source: rtems/c/src/exec/score/cpu/i960/i960.h @ 541dfb2

4.104.114.84.95
Last change on this file since 541dfb2 was 541dfb2, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 29, 1997 at 12:22:24 AM

Removed definitions which are now in targopts.h. This eliminates the
need for the "sed'ing" of this file. This should be a significant win
when addressing non-unix host and non-gnu toolsets.

  • Property mode set to 100644
File size: 8.6 KB
Line 
1/*  i960.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __i960_h
18#define __i960_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  This file contains the information required to build
26 *  RTEMS for a particular member of the Intel i960
27 *  family.  It does this by setting variables to indicate
28 *  which implementation dependent features are present
29 *  in a particular member of the family.
30 *
31 *  NOTE: For now i960 is really the i960ca.  eventually need
32 *        to put in at least support for FPU.
33 */
34
35#if defined(i960ca)
36
37#define CPU_MODEL_NAME  "i960ca"
38#define I960_HAS_FPU 0
39
40#else
41
42#error "Unsupported CPU Model"
43
44#endif
45
46/*
47 *  Define the name of the CPU family.
48 */
49
50#define CPU_NAME "Intel i960"
51
52#ifndef ASM
53
54/*
55 * XXX    should have an ifdef here and have stuff for the other
56 * XXX    family members...
57 */
58 
59#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
60 
61/* i960CA control structures */
62 
63/* Intel i960CA Control Table */
64 
65typedef struct {
66                            /* Control Group 0 */
67  unsigned int ipb0;              /* IP breakpoint 0 */
68  unsigned int ipb1;              /* IP breakpoint 1 */
69  unsigned int dab0;              /* data address breakpoint 0 */
70  unsigned int dab1;              /* data address breakpoint 1 */
71                            /* Control Group 1 */
72  unsigned int imap0;             /* interrupt map 0 */
73  unsigned int imap1;             /* interrupt map 1 */
74  unsigned int imap2;             /* interrupt map 2 */
75  unsigned int icon;              /* interrupt control */
76                            /* Control Group 2 */
77  unsigned int mcon0;             /* memory region 0 configuration */
78  unsigned int mcon1;             /* memory region 1 configuration */
79  unsigned int mcon2;             /* memory region 2 configuration */
80  unsigned int mcon3;             /* memory region 3 configuration */
81                            /* Control Group 3 */
82  unsigned int mcon4;             /* memory region 4 configuration */
83  unsigned int mcon5;             /* memory region 5 configuration */
84  unsigned int mcon6;             /* memory region 6 configuration */
85  unsigned int mcon7;             /* memory region 7 configuration */
86                            /* Control Group 4 */
87  unsigned int mcon8;             /* memory region 8 configuration */
88  unsigned int mcon9;             /* memory region 9 configuration */
89  unsigned int mcon10;            /* memory region 10 configuration */
90  unsigned int mcon11;            /* memory region 11 configuration */
91                            /* Control Group 5 */
92  unsigned int mcon12;            /* memory region 12 configuration */
93  unsigned int mcon13;            /* memory region 13 configuration */
94  unsigned int mcon14;            /* memory region 14 configuration */
95  unsigned int mcon15;            /* memory region 15 configuration */
96                            /* Control Group 6 */
97  unsigned int bpcon;             /* breakpoint control */
98  unsigned int tc;                /* trace control */
99  unsigned int bcon;              /* bus configuration control */
100  unsigned int reserved;          /* reserved */
101}   i960ca_control_table;
102 
103/* Intel i960CA Processor Control Block */
104 
105typedef struct {
106  unsigned int    *fault_tbl;     /* fault table base address */
107  i960ca_control_table
108                  *control_tbl;   /* control table base address */
109  unsigned int     initial_ac;    /* AC register initial value */
110  unsigned int     fault_config;  /* fault configuration word */
111  void           **intr_tbl;      /* interrupt table base address */
112  void            *sys_proc_tbl;  /* system procedure table
113                                     base address */
114  unsigned int     reserved;      /* reserved */
115  unsigned int    *intr_stack;    /* interrupt stack pointer */
116  unsigned int     ins_cache_cfg; /* instruction cache
117                                     configuration word */
118  unsigned int     reg_cache_cfg; /* register cache configuration word */
119}   i960ca_PRCB;
120 
121#endif
122
123/*
124 *  Interrupt Level Routines
125 */
126
127#define i960_disable_interrupts( oldlevel ) \
128  { (oldlevel) = 0x1f0000; \
129    asm volatile ( "modpc   0,%1,%1" \
130                       : "=d" ((oldlevel)) \
131                       : "0"  ((oldlevel)) ); \
132  }
133
134#define i960_enable_interrupts( oldlevel ) \
135  { unsigned int _mask = 0x1f0000; \
136    asm volatile ( "modpc   0,%0,%1" \
137                       : "=d" (_mask), "=d" ((oldlevel)) \
138                       : "0"  (_mask), "1"  ((oldlevel)) ); \
139  }
140
141#define i960_flash_interrupts( oldlevel ) \
142  { unsigned int _mask = 0x1f0000; \
143    asm volatile ( "modpc   0,%0,%1 ; \
144                    mov     %0,%1 ; \
145                    modpc   0,%0,%1"  \
146                       : "=d" (_mask), "=d" ((oldlevel)) \
147                       : "0"  (_mask), "1"  ((oldlevel)) ); \
148  }
149
150#define i960_get_interrupt_level( _level ) \
151  { \
152    i960_disable_interrupts( _level ); \
153    i960_enable_interrupts( _level ); \
154    (_level) = ((_level) & 0x1f0000) >> 16; \
155  } while ( 0 )
156
157#define i960_atomic_modify( mask, addr, prev ) \
158 { register unsigned int  _mask = (mask); \
159   register unsigned int *_addr = (unsigned int *)(addr); \
160   asm volatile( "atmod  %0,%1,%1" \
161                  : "=d" (_addr), "=d" (_mask) \
162                  : "0"  (_addr), "1"  (_mask) ); \
163   (prev) = _mask; \
164 }
165
166
167#define atomic_modify( _mask, _address, _previous ) \
168  i960_atomic_modify( _mask, _address, _previous )
169
170#define i960_enable_tracing() \
171 { register unsigned int _pc = 0x1; \
172   asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \
173 }
174
175#define i960_unmask_intr( xint ) \
176 { register unsigned int _mask= (1<<(xint)); \
177   asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
178 }
179
180#define i960_mask_intr( xint ) \
181 { register unsigned int _mask= (1<<(xint)); \
182   asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
183 }
184
185#define i960_clear_intr( xint ) \
186 { register unsigned int _xint=(xint); \
187asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \
188                  bbs    %0,sf0, loop_til_cleared" \
189                  : "=d" (_xint) : "0" (_xint) ); \
190 }
191
192#define i960_reload_ctl_group( group ) \
193 { register int _cmd = ((group)|0x400) ; \
194   asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
195 }
196
197#define i960_cause_intr( intr ) \
198 { register int _intr = (intr); \
199   asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
200 }
201
202#define i960_soft_reset( prcb ) \
203 { register i960ca_PRCB *_prcb = (prcb); \
204   register unsigned int         *_next=0; \
205   register unsigned int          _cmd  = 0x30000; \
206   asm volatile( "lda    next,%1; \
207                  sysctl %0,%1,%2; \
208            next: mov    g0,g0" \
209                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
210                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
211 }
212
213static inline unsigned int i960_pend_intrs()
214{ register unsigned int _intr=0;
215  asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
216  return ( _intr );
217}
218
219static inline unsigned int i960_mask_intrs()
220{ register unsigned int _intr=0;
221  asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
222  return( _intr );
223}
224
225static inline unsigned int i960_get_fp()
226{ register unsigned int _fp=0;
227  asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
228  return ( _fp );
229}
230
231/*
232 *  The following routine swaps the endian format of an unsigned int.
233 *  It must be static because it is referenced indirectly.
234 *
235 *  This version is based on code presented in Vol. 4, No. 4 of
236 *  Insight 960.  It is certainly something you wouldn't think
237 *  of on your own.
238 */
239
240static inline unsigned int CPU_swap_u32(
241  unsigned int value
242)
243{
244  register unsigned int to_swap = value;
245  register unsigned int temp    = 0xFF00FF00;
246  register unsigned int swapped = 0;
247
248                                            /*  to_swap      swapped  */
249  asm volatile ( "rotate  16,%0,%2 ;"       /* 0x12345678  0x56781234 */
250                 "modify  %1,%0,%2 ;"       /* 0x12345678  0x12785634 */
251                 "rotate  8,%2,%2"          /* 0x12345678  0x78563412 */
252                 : "=r" (to_swap), "=r" (temp), "=r" (swapped)
253                 : "0" (to_swap), "1" (temp), "2" (swapped)
254               );
255  return( swapped );
256}
257
258#ifdef __cplusplus
259}
260#endif
261
262#endif /* !ASM */
263
264#endif
265/* end of include file */
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