[ac7d5ef0] | 1 | /* i960.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the Intel |
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| 4 | * i960 processor family. |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * All rights assigned to U.S. Government, 1994. |
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| 9 | * |
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| 10 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 11 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 12 | * notice must appear in all copies of this file and its derivatives. |
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| 13 | * |
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| 14 | * $Id$ |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef __i960_h |
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| 18 | #define __i960_h |
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| 19 | |
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| 20 | #ifdef __cplusplus |
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| 21 | extern "C" { |
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| 22 | #endif |
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| 23 | |
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| 24 | /* |
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| 25 | * This file contains the information required to build |
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| 26 | * RTEMS for a particular member of the Intel i960 |
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| 27 | * family. It does this by setting variables to indicate |
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| 28 | * which implementation dependent features are present |
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| 29 | * in a particular member of the family. |
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| 30 | * |
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| 31 | * NOTE: For now i960 is really the i960ca. eventually need |
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| 32 | * to put in at least support for FPU. |
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| 33 | */ |
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| 34 | |
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| 35 | #if defined(i960ca) |
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| 36 | |
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[5e9b32b] | 37 | #define CPU_MODEL_NAME "i960ca" |
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[ac7d5ef0] | 38 | #define I960_HAS_FPU 0 |
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| 39 | |
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| 40 | #else |
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| 41 | |
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| 42 | #error "Unsupported CPU Model" |
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| 43 | |
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| 44 | #endif |
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| 45 | |
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| 46 | /* |
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| 47 | * Define the name of the CPU family. |
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| 48 | */ |
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| 49 | |
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| 50 | #define CPU_NAME "Intel i960" |
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| 51 | |
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| 52 | #ifndef ASM |
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| 53 | |
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| 54 | /* |
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| 55 | * XXX should have an ifdef here and have stuff for the other |
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| 56 | * XXX family members... |
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| 57 | */ |
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[88d594a] | 58 | |
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[ac7d5ef0] | 59 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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[88d594a] | 60 | |
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[ac7d5ef0] | 61 | /* i960CA control structures */ |
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[88d594a] | 62 | |
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[ac7d5ef0] | 63 | /* Intel i960CA Control Table */ |
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[88d594a] | 64 | |
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[ac7d5ef0] | 65 | typedef struct { |
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| 66 | /* Control Group 0 */ |
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| 67 | unsigned int ipb0; /* IP breakpoint 0 */ |
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| 68 | unsigned int ipb1; /* IP breakpoint 1 */ |
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| 69 | unsigned int dab0; /* data address breakpoint 0 */ |
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| 70 | unsigned int dab1; /* data address breakpoint 1 */ |
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| 71 | /* Control Group 1 */ |
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| 72 | unsigned int imap0; /* interrupt map 0 */ |
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| 73 | unsigned int imap1; /* interrupt map 1 */ |
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| 74 | unsigned int imap2; /* interrupt map 2 */ |
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| 75 | unsigned int icon; /* interrupt control */ |
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| 76 | /* Control Group 2 */ |
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| 77 | unsigned int mcon0; /* memory region 0 configuration */ |
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| 78 | unsigned int mcon1; /* memory region 1 configuration */ |
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| 79 | unsigned int mcon2; /* memory region 2 configuration */ |
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| 80 | unsigned int mcon3; /* memory region 3 configuration */ |
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| 81 | /* Control Group 3 */ |
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| 82 | unsigned int mcon4; /* memory region 4 configuration */ |
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| 83 | unsigned int mcon5; /* memory region 5 configuration */ |
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| 84 | unsigned int mcon6; /* memory region 6 configuration */ |
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| 85 | unsigned int mcon7; /* memory region 7 configuration */ |
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| 86 | /* Control Group 4 */ |
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| 87 | unsigned int mcon8; /* memory region 8 configuration */ |
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| 88 | unsigned int mcon9; /* memory region 9 configuration */ |
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| 89 | unsigned int mcon10; /* memory region 10 configuration */ |
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| 90 | unsigned int mcon11; /* memory region 11 configuration */ |
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| 91 | /* Control Group 5 */ |
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| 92 | unsigned int mcon12; /* memory region 12 configuration */ |
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| 93 | unsigned int mcon13; /* memory region 13 configuration */ |
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| 94 | unsigned int mcon14; /* memory region 14 configuration */ |
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| 95 | unsigned int mcon15; /* memory region 15 configuration */ |
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| 96 | /* Control Group 6 */ |
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| 97 | unsigned int bpcon; /* breakpoint control */ |
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| 98 | unsigned int tc; /* trace control */ |
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| 99 | unsigned int bcon; /* bus configuration control */ |
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| 100 | unsigned int reserved; /* reserved */ |
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| 101 | } i960ca_control_table; |
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[88d594a] | 102 | |
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[ac7d5ef0] | 103 | /* Intel i960CA Processor Control Block */ |
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[88d594a] | 104 | |
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[ac7d5ef0] | 105 | typedef struct { |
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| 106 | unsigned int *fault_tbl; /* fault table base address */ |
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| 107 | i960ca_control_table |
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| 108 | *control_tbl; /* control table base address */ |
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| 109 | unsigned int initial_ac; /* AC register initial value */ |
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| 110 | unsigned int fault_config; /* fault configuration word */ |
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| 111 | void **intr_tbl; /* interrupt table base address */ |
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| 112 | void *sys_proc_tbl; /* system procedure table |
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| 113 | base address */ |
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| 114 | unsigned int reserved; /* reserved */ |
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| 115 | unsigned int *intr_stack; /* interrupt stack pointer */ |
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| 116 | unsigned int ins_cache_cfg; /* instruction cache |
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| 117 | configuration word */ |
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| 118 | unsigned int reg_cache_cfg; /* register cache configuration word */ |
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| 119 | } i960ca_PRCB; |
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[88d594a] | 120 | |
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[ac7d5ef0] | 121 | #endif |
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| 122 | |
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[88d594a] | 123 | /* |
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| 124 | * Interrupt Level Routines |
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| 125 | */ |
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[ac7d5ef0] | 126 | |
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| 127 | #define i960_disable_interrupts( oldlevel ) \ |
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| 128 | { (oldlevel) = 0x1f0000; \ |
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| 129 | asm volatile ( "modpc 0,%1,%1" \ |
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| 130 | : "=d" ((oldlevel)) \ |
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| 131 | : "0" ((oldlevel)) ); \ |
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| 132 | } |
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| 133 | |
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| 134 | #define i960_enable_interrupts( oldlevel ) \ |
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| 135 | { unsigned int _mask = 0x1f0000; \ |
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| 136 | asm volatile ( "modpc 0,%0,%1" \ |
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| 137 | : "=d" (_mask), "=d" ((oldlevel)) \ |
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| 138 | : "0" (_mask), "1" ((oldlevel)) ); \ |
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| 139 | } |
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| 140 | |
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| 141 | #define i960_flash_interrupts( oldlevel ) \ |
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| 142 | { unsigned int _mask = 0x1f0000; \ |
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| 143 | asm volatile ( "modpc 0,%0,%1 ; \ |
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| 144 | mov %0,%1 ; \ |
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| 145 | modpc 0,%0,%1" \ |
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| 146 | : "=d" (_mask), "=d" ((oldlevel)) \ |
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| 147 | : "0" (_mask), "1" ((oldlevel)) ); \ |
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| 148 | } |
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| 149 | |
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[3a4ae6c] | 150 | #define i960_get_interrupt_level( _level ) \ |
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| 151 | { \ |
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| 152 | i960_disable_interrupts( _level ); \ |
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| 153 | i960_enable_interrupts( _level ); \ |
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| 154 | (_level) = ((_level) & 0x1f0000) >> 16; \ |
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| 155 | } while ( 0 ) |
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| 156 | |
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[ac7d5ef0] | 157 | #define i960_atomic_modify( mask, addr, prev ) \ |
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| 158 | { register unsigned int _mask = (mask); \ |
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| 159 | register unsigned int *_addr = (unsigned int *)(addr); \ |
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| 160 | asm volatile( "atmod %0,%1,%1" \ |
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| 161 | : "=d" (_addr), "=d" (_mask) \ |
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| 162 | : "0" (_addr), "1" (_mask) ); \ |
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| 163 | (prev) = _mask; \ |
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| 164 | } |
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| 165 | |
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| 166 | |
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| 167 | #define atomic_modify( _mask, _address, _previous ) \ |
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| 168 | i960_atomic_modify( _mask, _address, _previous ) |
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| 169 | |
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| 170 | #define i960_enable_tracing() \ |
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[88d594a] | 171 | { register unsigned int _pc = 0x1; \ |
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[ac7d5ef0] | 172 | asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \ |
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| 173 | } |
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| 174 | |
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| 175 | #define i960_unmask_intr( xint ) \ |
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[88d594a] | 176 | { register unsigned int _mask= (1<<(xint)); \ |
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[ac7d5ef0] | 177 | asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \ |
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| 178 | } |
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| 179 | |
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| 180 | #define i960_mask_intr( xint ) \ |
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[88d594a] | 181 | { register unsigned int _mask= (1<<(xint)); \ |
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[ac7d5ef0] | 182 | asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \ |
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| 183 | } |
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| 184 | |
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| 185 | #define i960_clear_intr( xint ) \ |
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[88d594a] | 186 | { register unsigned int _xint=(xint); \ |
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[3a4ae6c] | 187 | asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \ |
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| 188 | bbs %0,sf0, loop_til_cleared" \ |
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[ac7d5ef0] | 189 | : "=d" (_xint) : "0" (_xint) ); \ |
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| 190 | } |
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| 191 | |
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| 192 | #define i960_reload_ctl_group( group ) \ |
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| 193 | { register int _cmd = ((group)|0x400) ; \ |
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| 194 | asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \ |
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| 195 | } |
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| 196 | |
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| 197 | #define i960_cause_intr( intr ) \ |
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| 198 | { register int _intr = (intr); \ |
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| 199 | asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \ |
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| 200 | } |
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| 201 | |
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| 202 | #define i960_soft_reset( prcb ) \ |
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| 203 | { register i960ca_PRCB *_prcb = (prcb); \ |
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[88d594a] | 204 | register unsigned int *_next=0; \ |
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| 205 | register unsigned int _cmd = 0x30000; \ |
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[ac7d5ef0] | 206 | asm volatile( "lda next,%1; \ |
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| 207 | sysctl %0,%1,%2; \ |
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| 208 | next: mov g0,g0" \ |
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| 209 | : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ |
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| 210 | : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ |
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| 211 | } |
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| 212 | |
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[88d594a] | 213 | static inline unsigned int i960_pend_intrs() |
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| 214 | { register unsigned int _intr=0; |
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[ac7d5ef0] | 215 | asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) ); |
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| 216 | return ( _intr ); |
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| 217 | } |
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| 218 | |
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[88d594a] | 219 | static inline unsigned int i960_mask_intrs() |
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| 220 | { register unsigned int _intr=0; |
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[ac7d5ef0] | 221 | asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) ); |
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| 222 | return( _intr ); |
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| 223 | } |
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| 224 | |
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[88d594a] | 225 | static inline unsigned int i960_get_fp() |
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| 226 | { register unsigned int _fp=0; |
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[ac7d5ef0] | 227 | asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) ); |
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| 228 | return ( _fp ); |
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| 229 | } |
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| 230 | |
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| 231 | /* |
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| 232 | * The following routine swaps the endian format of an unsigned int. |
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| 233 | * It must be static because it is referenced indirectly. |
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| 234 | * |
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| 235 | * This version is based on code presented in Vol. 4, No. 4 of |
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| 236 | * Insight 960. It is certainly something you wouldn't think |
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| 237 | * of on your own. |
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| 238 | */ |
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| 239 | |
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| 240 | static inline unsigned int CPU_swap_u32( |
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| 241 | unsigned int value |
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| 242 | ) |
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| 243 | { |
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| 244 | register unsigned int to_swap = value; |
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| 245 | register unsigned int temp = 0xFF00FF00; |
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| 246 | register unsigned int swapped = 0; |
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| 247 | |
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| 248 | /* to_swap swapped */ |
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| 249 | asm volatile ( "rotate 16,%0,%2 ;" /* 0x12345678 0x56781234 */ |
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| 250 | "modify %1,%0,%2 ;" /* 0x12345678 0x12785634 */ |
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| 251 | "rotate 8,%2,%2" /* 0x12345678 0x78563412 */ |
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| 252 | : "=r" (to_swap), "=r" (temp), "=r" (swapped) |
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| 253 | : "0" (to_swap), "1" (temp), "2" (swapped) |
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| 254 | ); |
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| 255 | return( swapped ); |
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| 256 | } |
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| 257 | |
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| 258 | #ifdef __cplusplus |
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| 259 | } |
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| 260 | #endif |
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| 261 | |
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| 262 | #endif /* !ASM */ |
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| 263 | |
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| 264 | #endif |
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| 265 | /* end of include file */ |
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