source: rtems/c/src/exec/score/cpu/i960/cpu.h @ b9181082

4.104.114.84.95
Last change on this file since b9181082 was b9181082, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 29, 1997 at 12:13:00 AM

Added include of targopts.h.

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#pragma align 4            /* for GNU C structure alignment */
25
26#include <rtems/score/i960.h>              /* pick up machine definitions */
27#ifndef ASM
28#include <rtems/score/i960types.h>
29#endif
30
31#define CPU_INLINE_ENABLE_DISPATCH       FALSE
32#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
33
34/*
35 *  Use the i960's hardware interrupt stack support and have the
36 *  interrupt manager allocate the memory for it.
37 */
38
39#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
40#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
41#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
42
43/*
44 *  Some family members have no FP (SA/KA/CA/CF), others have it built in
45 *  (KB/MC/MX).  There does not appear to be an external coprocessor
46 *  for this family.
47 */
48
49#if ( I960_HAS_FPU == 1 )
50#define CPU_HARDWARE_FP     TRUE
51#error "Floating point support for i960 family has been implemented!!!"
52#else
53#define CPU_HARDWARE_FP     FALSE
54#endif
55
56#define CPU_ALL_TASKS_ARE_FP             FALSE
57#define CPU_IDLE_TASK_IS_FP              FALSE
58#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
59
60#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
61#define CPU_STACK_GROWS_UP               TRUE
62#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
63
64/* structures */
65
66/*
67 *  Basic integer context for the i960 family.
68 */
69
70typedef struct {
71  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
72  void       *r1_sp;                  /* (r1)  Stack Pointer */
73  unsigned32  pc;                     /* (pc)  Processor Control */
74  void       *g8;                     /* (g8)  Global Register 8 */
75  void       *g9;                     /* (g9)  Global Register 9 */
76  void       *g10;                    /* (g10) Global Register 10 */
77  void       *g11;                    /* (g11) Global Register 11 */
78  void       *g12;                    /* (g12) Global Register 12 */
79  void       *g13;                    /* (g13) Global Register 13 */
80  unsigned32  g14;                    /* (g14) Global Register 14 */
81  void       *g15_fp;                 /* (g15) Frame Pointer */
82}   Context_Control;
83
84/*
85 *  FP context save area for the i960 Numeric Extension
86 */
87
88typedef struct {
89   unsigned32  fp0_1;                 /* (fp0) first word  */
90   unsigned32  fp0_2;                 /* (fp0) second word */
91   unsigned32  fp0_3;                 /* (fp0) third word  */
92   unsigned32  fp1_1;                 /* (fp1) first word  */
93   unsigned32  fp1_2;                 /* (fp1) second word */
94   unsigned32  fp1_3;                 /* (fp1) third word  */
95   unsigned32  fp2_1;                 /* (fp2) first word  */
96   unsigned32  fp2_2;                 /* (fp2) second word */
97   unsigned32  fp2_3;                 /* (fp2) third word  */
98   unsigned32  fp3_1;                 /* (fp3) first word  */
99   unsigned32  fp3_2;                 /* (fp3) second word */
100   unsigned32  fp3_3;                 /* (fp3) third word  */
101} Context_Control_fp;
102
103/*
104 *  The following structure defines the set of information saved
105 *  on the current stack by RTEMS upon receipt of each interrupt.
106 */
107
108typedef struct {
109  unsigned32   TBD;   /* XXX Fix for this CPU */
110} CPU_Interrupt_frame;
111
112/*
113 *  Call frame for the i960 family.
114 */
115
116typedef struct {
117  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
118  void       *r1_sp;                  /* (r1)  Stack Pointer */
119  void       *r2_rip;                 /* (r2)  Return Instruction Pointer */
120  void       *r3;                     /* (r3)  Local Register 3 */
121  void       *r4;                     /* (r4)  Local Register 4 */
122  void       *r5;                     /* (r5)  Local Register 5 */
123  void       *r6;                     /* (r6)  Local Register 6 */
124  void       *r7;                     /* (r7)  Local Register 7 */
125  void       *r8;                     /* (r8)  Local Register 8 */
126  void       *r9;                     /* (r9)  Local Register 9 */
127  void       *r10;                    /* (r10) Local Register 10 */
128  void       *r11;                    /* (r11) Local Register 11 */
129  void       *r12;                    /* (r12) Local Register 12 */
130  void       *r13;                    /* (r13) Local Register 13 */
131  void       *r14;                    /* (r14) Local Register 14 */
132  void       *r15;                    /* (r15) Local Register 15 */
133  /* XXX Looks like sometimes there is FP stuff here (MC manual)? */
134}   CPU_Call_frame;
135
136/*
137 *  The following table contains the information required to configure
138 *  the i960 specific parameters.
139 */
140
141typedef struct {
142  void       (*pretasking_hook)( void );
143  void       (*predriver_hook)( void );
144  void       (*postdriver_hook)( void );
145  void       (*idle_task)( void );
146  boolean      do_zero_of_workspace;
147  unsigned32   interrupt_stack_size;
148  unsigned32   extra_mpci_receive_server_stack;
149  void *     (*stack_allocate_hook)( unsigned32 );
150  void       (*stack_free_hook)( void* );
151  /* end of fields required on all CPUs */
152
153#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
154  i960ca_PRCB *Prcb;
155#endif
156}   rtems_cpu_table;
157
158/* variables */
159
160SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
161SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
162
163/* constants */
164
165/*
166 *  This defines the number of levels and the mask used to pick those
167 *  bits out of a thread mode.
168 */
169
170#define CPU_MODES_INTERRUPT_LEVEL  0x0000001f  /* interrupt level in mode */
171#define CPU_MODES_INTERRUPT_MASK   0x0000001f  /* interrupt level in mode */
172
173/*
174 *  context size area for floating point
175 */
176
177#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
178
179/*
180 *  extra stack required by the MPCI receive server thread
181 */
182
183#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE)
184
185/*
186 *  i960 family supports 256 distinct vectors.
187 */
188
189#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
190#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
191
192/*
193 *  Minimum size of a thread's stack.
194 *
195 *  NOTE:  See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK
196 */
197
198#define CPU_STACK_MINIMUM_SIZE          2048
199
200/*
201 *  i960 is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
202 */
203
204#define CPU_ALIGNMENT                   4
205#define CPU_HEAP_ALIGNMENT              CPU_ALIGNMENT
206#define CPU_PARTITION_ALIGNMENT         CPU_ALIGNMENT
207
208/*
209 * i960ca stack requires 16 byte alignment
210 *
211 *  NOTE:  This factor may need to be family member dependent.
212 */
213
214#define CPU_STACK_ALIGNMENT        16
215
216/* macros */
217
218/*
219 *  ISR handler macros
220 *
221 *  These macros perform the following functions:
222 *     + disable all maskable CPU interrupts
223 *     + restore previous interrupt level (enable)
224 *     + temporarily restore interrupts (flash)
225 *     + set a particular level
226 */
227
228#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level )
229#define _CPU_ISR_Enable( _level )  i960_enable_interrupts( _level )
230#define _CPU_ISR_Flash( _level )   i960_flash_interrupts( _level )
231
232#define _CPU_ISR_Set_level( newlevel ) \
233  { \
234    unsigned32 _mask, _level=(newlevel); \
235    \
236    __asm__ volatile ( "ldconst 0x1f0000,%0; \
237                    modpc   0,%0,%1"     : "=d" (_mask), "=d" (_level) \
238                                         : "0"  (_mask), "1" (_level) \
239    ); \
240  }
241
242unsigned32 _CPU_ISR_Get_level( void );
243
244/* ISR handler section macros */
245
246/*
247 *  Context handler macros
248 *
249 *  These macros perform the following functions:
250 *     + initialize a context area
251 *     + restart the current thread
252 *     + calculate the initial pointer into a FP context area
253 *     + initialize an FP context area
254 */
255
256#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
257                                  _isr, _entry, _is_fp ) \
258 { CPU_Call_frame *_texit_frame; \
259   unsigned32 _mask; \
260   unsigned32 _base_pc; \
261   unsigned32  _stack_tmp; \
262   void       *_stack; \
263   \
264  _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \
265  _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
266  _stack = (void *) _stack_tmp; \
267   \
268   __asm__ volatile ( "flushreg" : : );   /* flush register cache */ \
269   \
270   (_the_context)->r0_pfp = _stack; \
271   (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \
272   (_the_context)->r1_sp  = _stack + (2 * sizeof(CPU_Call_frame)); \
273   __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \
274                  "modpc   0,0,%1 ; " \
275                  "andnot  %0,%1,%1 ; " \
276                  : "=d" (_mask), "=d" (_base_pc) : ); \
277   (_the_context)->pc     = _base_pc | ((_isr) << 16); \
278   (_the_context)->g14    = 0; \
279   \
280   _texit_frame         = (CPU_Call_frame *)_stack; \
281   _texit_frame->r0_pfp = NULL; \
282   _texit_frame->r1_sp  = (_the_context)->g15_fp; \
283   _texit_frame->r2_rip = (_entry); \
284 }
285
286#define _CPU_Context_Restart_self( _the_context ) \
287   _CPU_Context_restore( (_the_context) );
288
289#define _CPU_Context_Fp_start( _base, _offset )         NULL
290
291#define _CPU_Context_Initialize_fp( _fp_area )
292
293/* end of Context handler macros */
294
295/*
296 *  Fatal Error manager macros
297 *
298 *  These macros perform the following functions:
299 *    + disable interrupts and halt the CPU
300 */
301
302#define _CPU_Fatal_halt( _errorcode ) \
303  { unsigned32 _mask, _level; \
304    unsigned32 _error = (_errorcode); \
305    \
306    __asm__ volatile ( "ldconst 0x1f0000,%0 ; \
307                    mov     %0,%1 ; \
308                    modpc   0,%0,%1 ; \
309                    mov     %2,g0 ; \
310            self:   b       self " \
311                    : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \
312  }
313
314/* end of Fatal Error Manager macros */
315
316/*
317 *  Bitfield handler macros
318 *
319 *  These macros perform the following functions:
320 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
321 */
322
323#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
324#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
325
326#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
327  { unsigned32 _search = (_value); \
328    \
329    __asm__ volatile ( "scanbit   %0,%1  " \
330                    : "=d" (_search), "=d" (_output) \
331                    : "0"  (_search), "1"  (_output) ); \
332  }
333
334/* end of Bitfield handler macros */
335
336/*
337 *  Priority handler macros
338 *
339 *  These macros perform the following functions:
340 *    + return a mask with the bit for this major/minor portion of
341 *      of thread priority set.
342 *    + translate the bit number returned by "Bitfield_find_first_bit"
343 *      into an index into the thread ready chain bit maps
344 */
345
346#define _CPU_Priority_Mask( _bit_number ) \
347   ( 0x8000 >> (_bit_number) )
348
349#define _CPU_Priority_bits_index( _priority ) \
350   ( 15 - (_priority) )
351
352/* end of Priority handler macros */
353
354/* functions */
355
356/*
357 *  _CPU_Initialize
358 *
359 *  This routine performs CPU dependent initialization.
360 */
361
362void _CPU_Initialize(
363  rtems_cpu_table  *cpu_table,
364  void      (*thread_dispatch)
365);
366
367/*
368 *  _CPU_ISR_install_raw_handler
369 *
370 *  This routine installs a "raw" interrupt handler directly into the
371 *  processor's vector table.
372 */
373 
374void _CPU_ISR_install_raw_handler(
375  unsigned32  vector,
376  proc_ptr    new_handler,
377  proc_ptr   *old_handler
378);
379
380/*
381 *  _CPU_ISR_install_vector
382 *
383 *  This routine installs an interrupt vector.
384 */
385
386void _CPU_ISR_install_vector(
387  unsigned32  vector,
388  proc_ptr    new_handler,
389  proc_ptr   *old_handler
390);
391
392/*
393 *  _CPU_Install_interrupt_stack
394 *
395 *  This routine installs the hardware interrupt stack pointer.
396 */
397
398void _CPU_Install_interrupt_stack( void );
399
400/*
401 *  _CPU_Context_switch
402 *
403 *  This routine switches from the run context to the heir context.
404 */
405
406void _CPU_Context_switch(
407  Context_Control  *run,
408  Context_Control  *heir
409);
410
411/*
412 *  _CPU_Context_restore
413 *
414 *  This routine is generallu used only to restart self in an
415 *  efficient manner and avoid stack conflicts.
416 */
417
418void _CPU_Context_restore(
419  Context_Control *new_context
420);
421
422/*
423 *  _CPU_Context_save_fp
424 *
425 *  This routine saves the floating point context passed to it.
426 */
427
428void _CPU_Context_save_fp(
429  void        **fp_context_ptr
430);
431
432/*
433 *  _CPU_Context_restore_fp
434 *
435 *  This routine restores the floating point context passed to it.
436 */
437
438void _CPU_Context_restore_fp(
439  void        **fp_context_ptr
440);
441
442#ifdef __cplusplus
443}
444#endif
445
446#endif
447/* end of include file */
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