1 | /* cpu.h |
---|
2 | * |
---|
3 | * This include file contains information pertaining to the Intel |
---|
4 | * i960 processor family. |
---|
5 | * |
---|
6 | * COPYRIGHT (c) 1989-1997. |
---|
7 | * On-Line Applications Research Corporation (OAR). |
---|
8 | * Copyright assigned to U.S. Government, 1994. |
---|
9 | * |
---|
10 | * The license and distribution terms for this file may be |
---|
11 | * found in the file LICENSE in this distribution or at |
---|
12 | * http://www.OARcorp.com/rtems/license.html. |
---|
13 | * |
---|
14 | * $Id$ |
---|
15 | */ |
---|
16 | |
---|
17 | #ifndef __CPU_h |
---|
18 | #define __CPU_h |
---|
19 | |
---|
20 | #ifdef __cplusplus |
---|
21 | extern "C" { |
---|
22 | #endif |
---|
23 | |
---|
24 | #pragma align 4 /* for GNU C structure alignment */ |
---|
25 | |
---|
26 | #include <rtems/score/i960.h> /* pick up machine definitions */ |
---|
27 | #ifndef ASM |
---|
28 | #include <rtems/score/i960types.h> |
---|
29 | #endif |
---|
30 | |
---|
31 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
---|
32 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
---|
33 | |
---|
34 | /* |
---|
35 | * Use the i960's hardware interrupt stack support and have the |
---|
36 | * interrupt manager allocate the memory for it. |
---|
37 | */ |
---|
38 | |
---|
39 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
---|
40 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
---|
41 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
---|
42 | |
---|
43 | /* |
---|
44 | * Some family members have no FP (SA/KA/CA/CF), others have it built in |
---|
45 | * (KB/MC/MX). There does not appear to be an external coprocessor |
---|
46 | * for this family. |
---|
47 | */ |
---|
48 | |
---|
49 | #if ( I960_HAS_FPU == 1 ) |
---|
50 | #define CPU_HARDWARE_FP TRUE |
---|
51 | #error "Floating point support for i960 family has been implemented!!!" |
---|
52 | #else |
---|
53 | #define CPU_HARDWARE_FP FALSE |
---|
54 | #endif |
---|
55 | |
---|
56 | #define CPU_ALL_TASKS_ARE_FP FALSE |
---|
57 | #define CPU_IDLE_TASK_IS_FP FALSE |
---|
58 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
---|
59 | |
---|
60 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
---|
61 | #define CPU_STACK_GROWS_UP TRUE |
---|
62 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) |
---|
63 | |
---|
64 | /* |
---|
65 | * Define what is required to specify how the network to host conversion |
---|
66 | * routines are handled. |
---|
67 | */ |
---|
68 | |
---|
69 | #define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
---|
70 | #define CPU_BIG_ENDIAN TRUE |
---|
71 | #define CPU_LITTLE_ENDIAN FALSE |
---|
72 | |
---|
73 | |
---|
74 | /* structures */ |
---|
75 | |
---|
76 | /* |
---|
77 | * Basic integer context for the i960 family. |
---|
78 | */ |
---|
79 | |
---|
80 | typedef struct { |
---|
81 | void *r0_pfp; /* (r0) Previous Frame Pointer */ |
---|
82 | void *r1_sp; /* (r1) Stack Pointer */ |
---|
83 | unsigned32 pc; /* (pc) Processor Control */ |
---|
84 | void *g8; /* (g8) Global Register 8 */ |
---|
85 | void *g9; /* (g9) Global Register 9 */ |
---|
86 | void *g10; /* (g10) Global Register 10 */ |
---|
87 | void *g11; /* (g11) Global Register 11 */ |
---|
88 | void *g12; /* (g12) Global Register 12 */ |
---|
89 | void *g13; /* (g13) Global Register 13 */ |
---|
90 | unsigned32 g14; /* (g14) Global Register 14 */ |
---|
91 | void *g15_fp; /* (g15) Frame Pointer */ |
---|
92 | } Context_Control; |
---|
93 | |
---|
94 | /* |
---|
95 | * FP context save area for the i960 Numeric Extension |
---|
96 | */ |
---|
97 | |
---|
98 | typedef struct { |
---|
99 | unsigned32 fp0_1; /* (fp0) first word */ |
---|
100 | unsigned32 fp0_2; /* (fp0) second word */ |
---|
101 | unsigned32 fp0_3; /* (fp0) third word */ |
---|
102 | unsigned32 fp1_1; /* (fp1) first word */ |
---|
103 | unsigned32 fp1_2; /* (fp1) second word */ |
---|
104 | unsigned32 fp1_3; /* (fp1) third word */ |
---|
105 | unsigned32 fp2_1; /* (fp2) first word */ |
---|
106 | unsigned32 fp2_2; /* (fp2) second word */ |
---|
107 | unsigned32 fp2_3; /* (fp2) third word */ |
---|
108 | unsigned32 fp3_1; /* (fp3) first word */ |
---|
109 | unsigned32 fp3_2; /* (fp3) second word */ |
---|
110 | unsigned32 fp3_3; /* (fp3) third word */ |
---|
111 | } Context_Control_fp; |
---|
112 | |
---|
113 | /* |
---|
114 | * The following structure defines the set of information saved |
---|
115 | * on the current stack by RTEMS upon receipt of each interrupt. |
---|
116 | */ |
---|
117 | |
---|
118 | typedef struct { |
---|
119 | unsigned32 TBD; /* XXX Fix for this CPU */ |
---|
120 | } CPU_Interrupt_frame; |
---|
121 | |
---|
122 | /* |
---|
123 | * Call frame for the i960 family. |
---|
124 | */ |
---|
125 | |
---|
126 | typedef struct { |
---|
127 | void *r0_pfp; /* (r0) Previous Frame Pointer */ |
---|
128 | void *r1_sp; /* (r1) Stack Pointer */ |
---|
129 | void *r2_rip; /* (r2) Return Instruction Pointer */ |
---|
130 | void *r3; /* (r3) Local Register 3 */ |
---|
131 | void *r4; /* (r4) Local Register 4 */ |
---|
132 | void *r5; /* (r5) Local Register 5 */ |
---|
133 | void *r6; /* (r6) Local Register 6 */ |
---|
134 | void *r7; /* (r7) Local Register 7 */ |
---|
135 | void *r8; /* (r8) Local Register 8 */ |
---|
136 | void *r9; /* (r9) Local Register 9 */ |
---|
137 | void *r10; /* (r10) Local Register 10 */ |
---|
138 | void *r11; /* (r11) Local Register 11 */ |
---|
139 | void *r12; /* (r12) Local Register 12 */ |
---|
140 | void *r13; /* (r13) Local Register 13 */ |
---|
141 | void *r14; /* (r14) Local Register 14 */ |
---|
142 | void *r15; /* (r15) Local Register 15 */ |
---|
143 | /* XXX Looks like sometimes there is FP stuff here (MC manual)? */ |
---|
144 | } CPU_Call_frame; |
---|
145 | |
---|
146 | /* |
---|
147 | * The following table contains the information required to configure |
---|
148 | * the i960 specific parameters. |
---|
149 | */ |
---|
150 | |
---|
151 | typedef struct { |
---|
152 | void (*pretasking_hook)( void ); |
---|
153 | void (*predriver_hook)( void ); |
---|
154 | void (*postdriver_hook)( void ); |
---|
155 | void (*idle_task)( void ); |
---|
156 | boolean do_zero_of_workspace; |
---|
157 | unsigned32 interrupt_stack_size; |
---|
158 | unsigned32 extra_mpci_receive_server_stack; |
---|
159 | void * (*stack_allocate_hook)( unsigned32 ); |
---|
160 | void (*stack_free_hook)( void* ); |
---|
161 | /* end of fields required on all CPUs */ |
---|
162 | |
---|
163 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
---|
164 | i960ca_PRCB *Prcb; |
---|
165 | #endif |
---|
166 | } rtems_cpu_table; |
---|
167 | |
---|
168 | /* variables */ |
---|
169 | |
---|
170 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
---|
171 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
---|
172 | |
---|
173 | /* constants */ |
---|
174 | |
---|
175 | /* |
---|
176 | * This defines the number of levels and the mask used to pick those |
---|
177 | * bits out of a thread mode. |
---|
178 | */ |
---|
179 | |
---|
180 | #define CPU_MODES_INTERRUPT_LEVEL 0x0000001f /* interrupt level in mode */ |
---|
181 | #define CPU_MODES_INTERRUPT_MASK 0x0000001f /* interrupt level in mode */ |
---|
182 | |
---|
183 | /* |
---|
184 | * context size area for floating point |
---|
185 | */ |
---|
186 | |
---|
187 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
188 | |
---|
189 | /* |
---|
190 | * extra stack required by the MPCI receive server thread |
---|
191 | */ |
---|
192 | |
---|
193 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE) |
---|
194 | |
---|
195 | /* |
---|
196 | * i960 family supports 256 distinct vectors. |
---|
197 | */ |
---|
198 | |
---|
199 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
---|
200 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
---|
201 | |
---|
202 | /* |
---|
203 | * Minimum size of a thread's stack. |
---|
204 | * |
---|
205 | * NOTE: See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK |
---|
206 | */ |
---|
207 | |
---|
208 | #define CPU_STACK_MINIMUM_SIZE 2048 |
---|
209 | |
---|
210 | /* |
---|
211 | * i960 is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
---|
212 | */ |
---|
213 | |
---|
214 | #define CPU_ALIGNMENT 4 |
---|
215 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
216 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
217 | |
---|
218 | /* |
---|
219 | * i960ca stack requires 16 byte alignment |
---|
220 | * |
---|
221 | * NOTE: This factor may need to be family member dependent. |
---|
222 | */ |
---|
223 | |
---|
224 | #define CPU_STACK_ALIGNMENT 16 |
---|
225 | |
---|
226 | /* macros */ |
---|
227 | |
---|
228 | /* |
---|
229 | * ISR handler macros |
---|
230 | * |
---|
231 | * These macros perform the following functions: |
---|
232 | * + disable all maskable CPU interrupts |
---|
233 | * + restore previous interrupt level (enable) |
---|
234 | * + temporarily restore interrupts (flash) |
---|
235 | * + set a particular level |
---|
236 | */ |
---|
237 | |
---|
238 | #define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level ) |
---|
239 | #define _CPU_ISR_Enable( _level ) i960_enable_interrupts( _level ) |
---|
240 | #define _CPU_ISR_Flash( _level ) i960_flash_interrupts( _level ) |
---|
241 | |
---|
242 | #define _CPU_ISR_Set_level( newlevel ) \ |
---|
243 | { \ |
---|
244 | unsigned32 _mask = 0; \ |
---|
245 | unsigned32 _level = (newlevel); \ |
---|
246 | \ |
---|
247 | __asm__ volatile ( "ldconst 0x1f0000,%0; \ |
---|
248 | modpc 0,%0,%1" : "=d" (_mask), "=d" (_level) \ |
---|
249 | : "0" (_mask), "1" (_level) \ |
---|
250 | ); \ |
---|
251 | } |
---|
252 | |
---|
253 | unsigned32 _CPU_ISR_Get_level( void ); |
---|
254 | |
---|
255 | /* ISR handler section macros */ |
---|
256 | |
---|
257 | /* |
---|
258 | * Context handler macros |
---|
259 | * |
---|
260 | * These macros perform the following functions: |
---|
261 | * + initialize a context area |
---|
262 | * + restart the current thread |
---|
263 | * + calculate the initial pointer into a FP context area |
---|
264 | * + initialize an FP context area |
---|
265 | */ |
---|
266 | |
---|
267 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
---|
268 | _isr, _entry, _is_fp ) \ |
---|
269 | { CPU_Call_frame *_texit_frame; \ |
---|
270 | unsigned32 _mask; \ |
---|
271 | unsigned32 _base_pc; \ |
---|
272 | unsigned32 _stack_tmp; \ |
---|
273 | void *_stack; \ |
---|
274 | \ |
---|
275 | _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \ |
---|
276 | _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \ |
---|
277 | _stack = (void *) _stack_tmp; \ |
---|
278 | \ |
---|
279 | __asm__ volatile ( "flushreg" : : ); /* flush register cache */ \ |
---|
280 | \ |
---|
281 | (_the_context)->r0_pfp = _stack; \ |
---|
282 | (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \ |
---|
283 | (_the_context)->r1_sp = _stack + (2 * sizeof(CPU_Call_frame)); \ |
---|
284 | __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \ |
---|
285 | "modpc 0,0,%1 ; " \ |
---|
286 | "andnot %0,%1,%1 ; " \ |
---|
287 | : "=d" (_mask), "=d" (_base_pc) : ); \ |
---|
288 | (_the_context)->pc = _base_pc | ((_isr) << 16); \ |
---|
289 | (_the_context)->g14 = 0; \ |
---|
290 | \ |
---|
291 | _texit_frame = (CPU_Call_frame *)_stack; \ |
---|
292 | _texit_frame->r0_pfp = NULL; \ |
---|
293 | _texit_frame->r1_sp = (_the_context)->g15_fp; \ |
---|
294 | _texit_frame->r2_rip = (_entry); \ |
---|
295 | } |
---|
296 | |
---|
297 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
298 | _CPU_Context_restore( (_the_context) ); |
---|
299 | |
---|
300 | #define _CPU_Context_Fp_start( _base, _offset ) NULL |
---|
301 | |
---|
302 | #define _CPU_Context_Initialize_fp( _fp_area ) |
---|
303 | |
---|
304 | /* end of Context handler macros */ |
---|
305 | |
---|
306 | /* |
---|
307 | * Fatal Error manager macros |
---|
308 | * |
---|
309 | * These macros perform the following functions: |
---|
310 | * + disable interrupts and halt the CPU |
---|
311 | */ |
---|
312 | |
---|
313 | #define _CPU_Fatal_halt( _errorcode ) \ |
---|
314 | { unsigned32 _mask, _level; \ |
---|
315 | unsigned32 _error = (_errorcode); \ |
---|
316 | \ |
---|
317 | __asm__ volatile ( "ldconst 0x1f0000,%0 ; \ |
---|
318 | mov %0,%1 ; \ |
---|
319 | modpc 0,%0,%1 ; \ |
---|
320 | mov %2,g0 ; \ |
---|
321 | self: b self " \ |
---|
322 | : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \ |
---|
323 | } |
---|
324 | |
---|
325 | /* end of Fatal Error Manager macros */ |
---|
326 | |
---|
327 | /* |
---|
328 | * Bitfield handler macros |
---|
329 | * |
---|
330 | * These macros perform the following functions: |
---|
331 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
---|
332 | */ |
---|
333 | |
---|
334 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
---|
335 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
---|
336 | |
---|
337 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
338 | { unsigned32 _search = (_value); \ |
---|
339 | \ |
---|
340 | (_output) = 0; /* to prevent warnings */ \ |
---|
341 | __asm__ volatile ( "scanbit %0,%1 " \ |
---|
342 | : "=d" (_search), "=d" (_output) \ |
---|
343 | : "0" (_search), "1" (_output) ); \ |
---|
344 | } |
---|
345 | |
---|
346 | /* end of Bitfield handler macros */ |
---|
347 | |
---|
348 | /* |
---|
349 | * Priority handler macros |
---|
350 | * |
---|
351 | * These macros perform the following functions: |
---|
352 | * + return a mask with the bit for this major/minor portion of |
---|
353 | * of thread priority set. |
---|
354 | * + translate the bit number returned by "Bitfield_find_first_bit" |
---|
355 | * into an index into the thread ready chain bit maps |
---|
356 | */ |
---|
357 | |
---|
358 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
359 | ( 0x8000 >> (_bit_number) ) |
---|
360 | |
---|
361 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
362 | ( 15 - (_priority) ) |
---|
363 | |
---|
364 | /* end of Priority handler macros */ |
---|
365 | |
---|
366 | /* functions */ |
---|
367 | |
---|
368 | /* |
---|
369 | * _CPU_Initialize |
---|
370 | * |
---|
371 | * This routine performs CPU dependent initialization. |
---|
372 | */ |
---|
373 | |
---|
374 | void _CPU_Initialize( |
---|
375 | rtems_cpu_table *cpu_table, |
---|
376 | void (*thread_dispatch) |
---|
377 | ); |
---|
378 | |
---|
379 | /* |
---|
380 | * _CPU_ISR_install_raw_handler |
---|
381 | * |
---|
382 | * This routine installs a "raw" interrupt handler directly into the |
---|
383 | * processor's vector table. |
---|
384 | */ |
---|
385 | |
---|
386 | void _CPU_ISR_install_raw_handler( |
---|
387 | unsigned32 vector, |
---|
388 | proc_ptr new_handler, |
---|
389 | proc_ptr *old_handler |
---|
390 | ); |
---|
391 | |
---|
392 | /* |
---|
393 | * _CPU_ISR_install_vector |
---|
394 | * |
---|
395 | * This routine installs an interrupt vector. |
---|
396 | */ |
---|
397 | |
---|
398 | void _CPU_ISR_install_vector( |
---|
399 | unsigned32 vector, |
---|
400 | proc_ptr new_handler, |
---|
401 | proc_ptr *old_handler |
---|
402 | ); |
---|
403 | |
---|
404 | /* |
---|
405 | * _CPU_Install_interrupt_stack |
---|
406 | * |
---|
407 | * This routine installs the hardware interrupt stack pointer. |
---|
408 | */ |
---|
409 | |
---|
410 | void _CPU_Install_interrupt_stack( void ); |
---|
411 | |
---|
412 | /* |
---|
413 | * _CPU_Context_switch |
---|
414 | * |
---|
415 | * This routine switches from the run context to the heir context. |
---|
416 | */ |
---|
417 | |
---|
418 | void _CPU_Context_switch( |
---|
419 | Context_Control *run, |
---|
420 | Context_Control *heir |
---|
421 | ); |
---|
422 | |
---|
423 | /* |
---|
424 | * _CPU_Context_restore |
---|
425 | * |
---|
426 | * This routine is generally used only to restart self in an |
---|
427 | * efficient manner and avoid stack conflicts. |
---|
428 | */ |
---|
429 | |
---|
430 | void _CPU_Context_restore( |
---|
431 | Context_Control *new_context |
---|
432 | ); |
---|
433 | |
---|
434 | /* |
---|
435 | * _CPU_Context_save_fp |
---|
436 | * |
---|
437 | * This routine saves the floating point context passed to it. |
---|
438 | */ |
---|
439 | |
---|
440 | void _CPU_Context_save_fp( |
---|
441 | void **fp_context_ptr |
---|
442 | ); |
---|
443 | |
---|
444 | /* |
---|
445 | * _CPU_Context_restore_fp |
---|
446 | * |
---|
447 | * This routine restores the floating point context passed to it. |
---|
448 | */ |
---|
449 | |
---|
450 | void _CPU_Context_restore_fp( |
---|
451 | void **fp_context_ptr |
---|
452 | ); |
---|
453 | |
---|
454 | #ifdef __cplusplus |
---|
455 | } |
---|
456 | #endif |
---|
457 | |
---|
458 | #endif |
---|
459 | /* end of include file */ |
---|