source: rtems/c/src/exec/score/cpu/i960/cpu.h @ 75f09e5

4.104.114.84.95
Last change on this file since 75f09e5 was 75f09e5, checked in by Joel Sherrill <joel.sherrill@…>, on 02/21/96 at 14:43:34

Dispersal of internal thread handler resulted in IDLE thread becoming
part of the Thread Handler. This required the name of the optional
CPU dependent IDLE thread implementation to change.

  • Property mode set to 100644
File size: 12.3 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#pragma align 4            /* for GNU C structure alignment */
25
26#include <rtems/score/i960.h>
27#ifndef ASM
28#include <rtems/score/i960types.h>
29#endif
30
31#define CPU_INLINE_ENABLE_DISPATCH       FALSE
32#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
33
34/*
35 *  Use the i960's hardware interrupt stack support and have the
36 *  interrupt manager allocate the memory for it.
37 */
38
39#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
40#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
41#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
42
43/*
44 *  Some family members have no FP (SA/KA/CA/CF), others have it built in
45 *  (KB/MC/MX).  There does not appear to be an external coprocessor
46 *  for this family.
47 */
48
49#if ( I960_HAS_FPU == 1 )
50#define CPU_HARDWARE_FP     TRUE
51#error "Floating point support for i960 family has been implemented!!!"
52#else
53#define CPU_HARDWARE_FP     FALSE
54#endif
55
56#define CPU_ALL_TASKS_ARE_FP             FALSE
57#define CPU_IDLE_TASK_IS_FP              FALSE
58#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
59
60#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
61#define CPU_STACK_GROWS_UP               TRUE
62#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
63
64/* structures */
65
66/*
67 *  Basic integer context for the i960 family.
68 */
69
70typedef struct {
71  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
72  void       *r1_sp;                  /* (r1)  Stack Pointer */
73  unsigned32  pc;                     /* (pc)  Processor Control */
74  void       *g8;                     /* (g8)  Global Register 8 */
75  void       *g9;                     /* (g9)  Global Register 9 */
76  void       *g10;                    /* (g10) Global Register 10 */
77  void       *g11;                    /* (g11) Global Register 11 */
78  void       *g12;                    /* (g12) Global Register 12 */
79  void       *g13;                    /* (g13) Global Register 13 */
80  unsigned32  g14;                    /* (g14) Global Register 14 */
81  void       *g15_fp;                 /* (g15) Frame Pointer */
82}   Context_Control;
83
84/*
85 *  FP context save area for the i960 Numeric Extension
86 */
87
88typedef struct {
89   unsigned32  fp0_1;                 /* (fp0) first word  */
90   unsigned32  fp0_2;                 /* (fp0) second word */
91   unsigned32  fp0_3;                 /* (fp0) third word  */
92   unsigned32  fp1_1;                 /* (fp1) first word  */
93   unsigned32  fp1_2;                 /* (fp1) second word */
94   unsigned32  fp1_3;                 /* (fp1) third word  */
95   unsigned32  fp2_1;                 /* (fp2) first word  */
96   unsigned32  fp2_2;                 /* (fp2) second word */
97   unsigned32  fp2_3;                 /* (fp2) third word  */
98   unsigned32  fp3_1;                 /* (fp3) first word  */
99   unsigned32  fp3_2;                 /* (fp3) second word */
100   unsigned32  fp3_3;                 /* (fp3) third word  */
101} Context_Control_fp;
102
103/*
104 *  The following structure defines the set of information saved
105 *  on the current stack by RTEMS upon receipt of each interrupt.
106 */
107
108typedef struct {
109  unsigned32   TBD;   /* XXX Fix for this CPU */
110} CPU_Interrupt_frame;
111
112/*
113 *  Call frame for the i960 family.
114 */
115
116typedef struct {
117  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
118  void       *r1_sp;                  /* (r1)  Stack Pointer */
119  void       *r2_rip;                 /* (r2)  Return Instruction Pointer */
120  void       *r3;                     /* (r3)  Local Register 3 */
121  void       *r4;                     /* (r4)  Local Register 4 */
122  void       *r5;                     /* (r5)  Local Register 5 */
123  void       *r6;                     /* (r6)  Local Register 6 */
124  void       *r7;                     /* (r7)  Local Register 7 */
125  void       *r8;                     /* (r8)  Local Register 8 */
126  void       *r9;                     /* (r9)  Local Register 9 */
127  void       *r10;                    /* (r10) Local Register 10 */
128  void       *r11;                    /* (r11) Local Register 11 */
129  void       *r12;                    /* (r12) Local Register 12 */
130  void       *r13;                    /* (r13) Local Register 13 */
131  void       *r14;                    /* (r14) Local Register 14 */
132  void       *r15;                    /* (r15) Local Register 15 */
133  /* XXX Looks like sometimes there is FP stuff here (MC manual)? */
134}   CPU_Call_frame;
135
136/*
137 *  The following table contains the information required to configure
138 *  the i960 specific parameters.
139 */
140
141typedef struct {
142  void       (*pretasking_hook)( void );
143  void       (*predriver_hook)( void );
144  void       (*postdriver_hook)( void );
145  void       (*idle_task)( void );
146  boolean      do_zero_of_workspace;
147  unsigned32   interrupt_stack_size;
148  unsigned32   extra_mpci_receive_server_stack;
149#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
150  i960ca_PRCB *Prcb;
151#endif
152}   rtems_cpu_table;
153
154/* variables */
155
156EXTERN void               *_CPU_Interrupt_stack_low;
157EXTERN void               *_CPU_Interrupt_stack_high;
158
159/* constants */
160
161/*
162 *  This defines the number of levels and the mask used to pick those
163 *  bits out of a thread mode.
164 */
165
166#define CPU_MODES_INTERRUPT_LEVEL  0x0000001f  /* interrupt level in mode */
167#define CPU_MODES_INTERRUPT_MASK   0x0000001f  /* interrupt level in mode */
168
169/*
170 *  context size area for floating point
171 */
172
173#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
174
175/*
176 *  extra stack required by the MPCI receive server thread
177 */
178
179#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE)
180
181/*
182 *  i960 family supports 256 distinct vectors.
183 */
184
185#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
186#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
187
188/*
189 *  Minimum size of a thread's stack.
190 *
191 *  NOTE:  See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK
192 */
193
194#define CPU_STACK_MINIMUM_SIZE          2048
195
196/*
197 *  i960 is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
198 */
199
200#define CPU_ALIGNMENT                   4
201#define CPU_HEAP_ALIGNMENT              CPU_ALIGNMENT
202#define CPU_PARTITION_ALIGNMENT         CPU_ALIGNMENT
203
204/*
205 * i960ca stack requires 16 byte alignment
206 *
207 *  NOTE:  This factor may need to be family member dependent.
208 */
209
210#define CPU_STACK_ALIGNMENT        16
211
212/* macros */
213
214/*
215 *  ISR handler macros
216 *
217 *  These macros perform the following functions:
218 *     + disable all maskable CPU interrupts
219 *     + restore previous interrupt level (enable)
220 *     + temporarily restore interrupts (flash)
221 *     + set a particular level
222 */
223
224#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level )
225#define _CPU_ISR_Enable( _level )  i960_enable_interrupts( _level )
226#define _CPU_ISR_Flash( _level )   i960_flash_interrupts( _level )
227
228#define _CPU_ISR_Set_level( newlevel ) \
229  { \
230    unsigned32 _mask, _level=(newlevel); \
231    \
232    __asm__ volatile ( "ldconst 0x1f0000,%0; \
233                    modpc   0,%0,%1"     : "=d" (_mask), "=d" (_level) \
234                                         : "0"  (_mask), "1" (_level) \
235    ); \
236  }
237
238unsigned32 _CPU_ISR_Get_level( void );
239
240/* ISR handler section macros */
241
242/*
243 *  Context handler macros
244 *
245 *  These macros perform the following functions:
246 *     + initialize a context area
247 *     + restart the current thread
248 *     + calculate the initial pointer into a FP context area
249 *     + initialize an FP context area
250 */
251
252#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
253                                  _isr, _entry, _is_fp ) \
254 { CPU_Call_frame *_texit_frame; \
255   unsigned32 _mask; \
256   unsigned32 _base_pc; \
257   unsigned32  _stack_tmp; \
258   void       *_stack; \
259   \
260  _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \
261  _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
262  _stack = (void *) _stack_tmp; \
263   \
264   __asm__ volatile ( "flushreg" : : );   /* flush register cache */ \
265   \
266   (_the_context)->r0_pfp = _stack; \
267   (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \
268   (_the_context)->r1_sp  = _stack + (2 * sizeof(CPU_Call_frame)); \
269   __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \
270                  "modpc   0,0,%1 ; " \
271                  "andnot  %0,%1,%1 ; " \
272                  : "=d" (_mask), "=d" (_base_pc) : ); \
273   (_the_context)->pc     = _base_pc | ((_isr) << 16); \
274   (_the_context)->g14    = 0; \
275   \
276   _texit_frame         = (CPU_Call_frame *)_stack; \
277   _texit_frame->r0_pfp = NULL; \
278   _texit_frame->r1_sp  = (_the_context)->g15_fp; \
279   _texit_frame->r2_rip = (_entry); \
280 }
281
282#define _CPU_Context_Restart_self( _the_context ) \
283   _CPU_Context_restore( (_the_context) );
284
285#define _CPU_Context_Fp_start( _base, _offset )         NULL
286
287#define _CPU_Context_Initialize_fp( _fp_area )
288
289/* end of Context handler macros */
290
291/*
292 *  Fatal Error manager macros
293 *
294 *  These macros perform the following functions:
295 *    + disable interrupts and halt the CPU
296 */
297
298#define _CPU_Fatal_halt( _errorcode ) \
299  { unsigned32 _mask, _level; \
300    unsigned32 _error = (_errorcode); \
301    \
302    __asm__ volatile ( "ldconst 0x1f0000,%0 ; \
303                    mov     %0,%1 ; \
304                    modpc   0,%0,%1 ; \
305                    mov     %2,g0 ; \
306            self:   b       self " \
307                    : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \
308  }
309
310/* end of Fatal Error Manager macros */
311
312/*
313 *  Bitfield handler macros
314 *
315 *  These macros perform the following functions:
316 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
317 */
318
319#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
320#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
321
322#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
323  { unsigned32 _search = (_value); \
324    \
325    __asm__ volatile ( "scanbit   %0,%1  " \
326                    : "=d" (_search), "=d" (_output) \
327                    : "0"  (_search), "1"  (_output) ); \
328  }
329
330/* end of Bitfield handler macros */
331
332/*
333 *  Priority handler macros
334 *
335 *  These macros perform the following functions:
336 *    + return a mask with the bit for this major/minor portion of
337 *      of thread priority set.
338 *    + translate the bit number returned by "Bitfield_find_first_bit"
339 *      into an index into the thread ready chain bit maps
340 */
341
342#define _CPU_Priority_Mask( _bit_number ) \
343   ( 0x8000 >> (_bit_number) )
344
345#define _CPU_Priority_bits_index( _priority ) \
346   ( 15 - (_priority) )
347
348/* end of Priority handler macros */
349
350/* functions */
351
352/*
353 *  _CPU_Initialize
354 *
355 *  This routine performs CPU dependent initialization.
356 */
357
358void _CPU_Initialize(
359  rtems_cpu_table  *cpu_table,
360  void      (*thread_dispatch)
361);
362
363/*
364 *  _CPU_ISR_install_raw_handler
365 *
366 *  This routine installs a "raw" interrupt handler directly into the
367 *  processor's vector table.
368 */
369 
370void _CPU_ISR_install_raw_handler(
371  unsigned32  vector,
372  proc_ptr    new_handler,
373  proc_ptr   *old_handler
374);
375
376/*
377 *  _CPU_ISR_install_vector
378 *
379 *  This routine installs an interrupt vector.
380 */
381
382void _CPU_ISR_install_vector(
383  unsigned32  vector,
384  proc_ptr    new_handler,
385  proc_ptr   *old_handler
386);
387
388/*
389 *  _CPU_Install_interrupt_stack
390 *
391 *  This routine installs the hardware interrupt stack pointer.
392 */
393
394void _CPU_Install_interrupt_stack( void );
395
396/*
397 *  _CPU_Context_switch
398 *
399 *  This routine switches from the run context to the heir context.
400 */
401
402void _CPU_Context_switch(
403  Context_Control  *run,
404  Context_Control  *heir
405);
406
407/*
408 *  _CPU_Context_restore
409 *
410 *  This routine is generallu used only to restart self in an
411 *  efficient manner and avoid stack conflicts.
412 */
413
414void _CPU_Context_restore(
415  Context_Control *new_context
416);
417
418/*
419 *  _CPU_Context_save_fp
420 *
421 *  This routine saves the floating point context passed to it.
422 */
423
424void _CPU_Context_save_fp(
425  void        **fp_context_ptr
426);
427
428/*
429 *  _CPU_Context_restore_fp
430 *
431 *  This routine restores the floating point context passed to it.
432 */
433
434void _CPU_Context_restore_fp(
435  void        **fp_context_ptr
436);
437
438#ifdef __cplusplus
439}
440#endif
441
442#endif
443/* end of include file */
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