1 | /* cpu.h |
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2 | * |
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3 | * This include file contains information pertaining to the Intel |
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4 | * i960 processor family. |
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5 | * |
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6 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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7 | * On-Line Applications Research Corporation (OAR). |
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8 | * All rights assigned to U.S. Government, 1994. |
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9 | * |
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10 | * This material may be reproduced by or for the U.S. Government pursuant |
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11 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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12 | * notice must appear in all copies of this file and its derivatives. |
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13 | * |
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14 | * $Id$ |
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15 | */ |
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16 | |
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17 | #ifndef __CPU_h |
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18 | #define __CPU_h |
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19 | |
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20 | #ifdef __cplusplus |
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21 | extern "C" { |
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22 | #endif |
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23 | |
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24 | #pragma align 4 /* for GNU C structure alignment */ |
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25 | |
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26 | #include <rtems/i960.h> |
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27 | #ifndef ASM |
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28 | #include <rtems/i960types.h> |
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29 | #endif |
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30 | |
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31 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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32 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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33 | |
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34 | /* |
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35 | * Use the i960's hardware interrupt stack support and have the |
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36 | * interrupt manager allocate the memory for it. |
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37 | */ |
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38 | |
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39 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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40 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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41 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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42 | |
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43 | /* |
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44 | * Some family members have no FP (SA/KA/CA/CF), others have it built in |
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45 | * (KB/MC/MX). There does not appear to be an external coprocessor |
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46 | * for this family. |
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47 | */ |
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48 | |
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49 | #if ( I960_HAS_FPU == 1 ) |
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50 | #define CPU_HARDWARE_FP TRUE |
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51 | #error "Floating point support for i960 family has been implemented!!!" |
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52 | #else |
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53 | #define CPU_HARDWARE_FP FALSE |
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54 | #endif |
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55 | |
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56 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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57 | #define CPU_IDLE_TASK_IS_FP FALSE |
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58 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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59 | |
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60 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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61 | #define CPU_STACK_GROWS_UP TRUE |
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62 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) |
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63 | |
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64 | /* structures */ |
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65 | |
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66 | /* |
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67 | * Basic integer context for the i960 family. |
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68 | */ |
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69 | |
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70 | typedef struct { |
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71 | void *r0_pfp; /* (r0) Previous Frame Pointer */ |
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72 | void *r1_sp; /* (r1) Stack Pointer */ |
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73 | unsigned32 pc; /* (pc) Processor Control */ |
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74 | void *g8; /* (g8) Global Register 8 */ |
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75 | void *g9; /* (g9) Global Register 9 */ |
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76 | void *g10; /* (g10) Global Register 10 */ |
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77 | void *g11; /* (g11) Global Register 11 */ |
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78 | void *g12; /* (g12) Global Register 12 */ |
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79 | void *g13; /* (g13) Global Register 13 */ |
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80 | unsigned32 g14; /* (g14) Global Register 14 */ |
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81 | void *g15_fp; /* (g15) Frame Pointer */ |
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82 | } Context_Control; |
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83 | |
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84 | /* |
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85 | * FP context save area for the i960 Numeric Extension |
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86 | */ |
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87 | |
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88 | typedef struct { |
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89 | unsigned32 fp0_1; /* (fp0) first word */ |
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90 | unsigned32 fp0_2; /* (fp0) second word */ |
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91 | unsigned32 fp0_3; /* (fp0) third word */ |
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92 | unsigned32 fp1_1; /* (fp1) first word */ |
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93 | unsigned32 fp1_2; /* (fp1) second word */ |
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94 | unsigned32 fp1_3; /* (fp1) third word */ |
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95 | unsigned32 fp2_1; /* (fp2) first word */ |
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96 | unsigned32 fp2_2; /* (fp2) second word */ |
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97 | unsigned32 fp2_3; /* (fp2) third word */ |
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98 | unsigned32 fp3_1; /* (fp3) first word */ |
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99 | unsigned32 fp3_2; /* (fp3) second word */ |
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100 | unsigned32 fp3_3; /* (fp3) third word */ |
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101 | } Context_Control_fp; |
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102 | |
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103 | /* |
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104 | * The following structure defines the set of information saved |
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105 | * on the current stack by RTEMS upon receipt of each interrupt. |
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106 | */ |
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107 | |
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108 | typedef struct { |
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109 | unsigned32 TBD; /* XXX Fix for this CPU */ |
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110 | } CPU_Interrupt_frame; |
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111 | |
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112 | /* |
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113 | * Call frame for the i960 family. |
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114 | */ |
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115 | |
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116 | typedef struct { |
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117 | void *r0_pfp; /* (r0) Previous Frame Pointer */ |
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118 | void *r1_sp; /* (r1) Stack Pointer */ |
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119 | void *r2_rip; /* (r2) Return Instruction Pointer */ |
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120 | void *r3; /* (r3) Local Register 3 */ |
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121 | void *r4; /* (r4) Local Register 4 */ |
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122 | void *r5; /* (r5) Local Register 5 */ |
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123 | void *r6; /* (r6) Local Register 6 */ |
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124 | void *r7; /* (r7) Local Register 7 */ |
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125 | void *r8; /* (r8) Local Register 8 */ |
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126 | void *r9; /* (r9) Local Register 9 */ |
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127 | void *r10; /* (r10) Local Register 10 */ |
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128 | void *r11; /* (r11) Local Register 11 */ |
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129 | void *r12; /* (r12) Local Register 12 */ |
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130 | void *r13; /* (r13) Local Register 13 */ |
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131 | void *r14; /* (r14) Local Register 14 */ |
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132 | void *r15; /* (r15) Local Register 15 */ |
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133 | /* XXX Looks like sometimes there is FP stuff here (MC manual)? */ |
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134 | } CPU_Call_frame; |
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135 | |
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136 | /* |
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137 | * The following table contains the information required to configure |
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138 | * the i960 specific parameters. |
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139 | */ |
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140 | |
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141 | typedef struct { |
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142 | void (*pretasking_hook)( void ); |
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143 | void (*predriver_hook)( void ); |
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144 | void (*postdriver_hook)( void ); |
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145 | void (*idle_task)( void ); |
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146 | boolean do_zero_of_workspace; |
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147 | unsigned32 interrupt_stack_size; |
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148 | unsigned32 extra_system_initialization_stack; |
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149 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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150 | i960ca_PRCB *Prcb; |
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151 | #endif |
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152 | } rtems_cpu_table; |
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153 | |
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154 | /* variables */ |
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155 | |
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156 | EXTERN void *_CPU_Interrupt_stack_low; |
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157 | EXTERN void *_CPU_Interrupt_stack_high; |
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158 | |
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159 | /* constants */ |
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160 | |
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161 | /* |
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162 | * This defines the number of levels and the mask used to pick those |
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163 | * bits out of a thread mode. |
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164 | */ |
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165 | |
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166 | #define CPU_MODES_INTERRUPT_LEVEL 0x0000001f /* interrupt level in mode */ |
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167 | #define CPU_MODES_INTERRUPT_MASK 0x0000001f /* interrupt level in mode */ |
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168 | |
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169 | /* |
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170 | * context size area for floating point |
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171 | */ |
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172 | |
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173 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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174 | |
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175 | /* |
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176 | * extra stack required by system initialization thread |
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177 | * |
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178 | * NOTE: Make sure this stays positive ... |
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179 | */ |
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180 | |
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181 | #define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK \ |
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182 | (4096 - CPU_STACK_MINIMUM_SIZE) |
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183 | |
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184 | /* |
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185 | * i960 family supports 256 distinct vectors. |
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186 | */ |
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187 | |
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188 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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189 | |
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190 | /* |
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191 | * Minimum size of a thread's stack. |
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192 | * |
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193 | * NOTE: See CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK |
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194 | */ |
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195 | |
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196 | #define CPU_STACK_MINIMUM_SIZE 1024 |
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197 | |
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198 | /* |
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199 | * i960 is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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200 | */ |
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201 | |
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202 | #define CPU_ALIGNMENT 4 |
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203 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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204 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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205 | |
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206 | /* |
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207 | * i960ca stack requires 16 byte alignment |
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208 | * |
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209 | * NOTE: This factor may need to be family member dependent. |
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210 | */ |
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211 | |
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212 | #define CPU_STACK_ALIGNMENT 16 |
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213 | |
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214 | /* macros */ |
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215 | |
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216 | /* |
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217 | * ISR handler macros |
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218 | * |
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219 | * These macros perform the following functions: |
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220 | * + disable all maskable CPU interrupts |
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221 | * + restore previous interrupt level (enable) |
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222 | * + temporarily restore interrupts (flash) |
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223 | * + set a particular level |
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224 | */ |
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225 | |
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226 | #define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level ) |
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227 | #define _CPU_ISR_Enable( _level ) i960_enable_interrupts( _level ) |
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228 | #define _CPU_ISR_Flash( _level ) i960_flash_interrupts( _level ) |
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229 | |
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230 | #define _CPU_ISR_Set_level( newlevel ) \ |
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231 | { \ |
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232 | unsigned32 _mask, _level=(newlevel); \ |
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233 | \ |
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234 | __asm__ volatile ( "ldconst 0x1f0000,%0; \ |
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235 | modpc 0,%0,%1" : "=d" (_mask), "=d" (_level) \ |
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236 | : "0" (_mask), "1" (_level) \ |
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237 | ); \ |
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238 | } |
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239 | |
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240 | /* ISR handler section macros */ |
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241 | |
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242 | /* |
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243 | * Context handler macros |
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244 | * |
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245 | * These macros perform the following functions: |
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246 | * + initialize a context area |
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247 | * + restart the current thread |
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248 | * + calculate the initial pointer into a FP context area |
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249 | * + initialize an FP context area |
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250 | */ |
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251 | |
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252 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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253 | _isr, _entry ) \ |
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254 | { CPU_Call_frame *_texit_frame; \ |
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255 | unsigned32 _mask; \ |
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256 | unsigned32 _base_pc; \ |
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257 | unsigned32 _stack_tmp; \ |
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258 | void *_stack; \ |
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259 | \ |
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260 | _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \ |
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261 | _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \ |
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262 | _stack = (void *) _stack_tmp; \ |
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263 | \ |
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264 | __asm__ volatile ( "flushreg" : : ); /* flush register cache */ \ |
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265 | \ |
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266 | (_the_context)->r0_pfp = _stack; \ |
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267 | (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \ |
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268 | (_the_context)->r1_sp = _stack + (2 * sizeof(CPU_Call_frame)); \ |
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269 | __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \ |
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270 | "modpc 0,0,%1 ; " \ |
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271 | "andnot %0,%1,%1 ; " \ |
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272 | : "=d" (_mask), "=d" (_base_pc) : ); \ |
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273 | (_the_context)->pc = _base_pc | ((_isr) << 16); \ |
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274 | (_the_context)->g14 = 0; \ |
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275 | \ |
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276 | _texit_frame = (CPU_Call_frame *)_stack; \ |
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277 | _texit_frame->r0_pfp = NULL; \ |
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278 | _texit_frame->r1_sp = (_the_context)->g15_fp; \ |
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279 | _texit_frame->r2_rip = (_entry); \ |
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280 | } |
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281 | |
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282 | #define _CPU_Context_Restart_self( _the_context ) \ |
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283 | _CPU_Context_restore( (_the_context) ); |
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284 | |
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285 | #define _CPU_Context_Fp_start( _base, _offset ) NULL |
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286 | |
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287 | #define _CPU_Context_Initialize_fp( _fp_area ) |
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288 | |
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289 | /* end of Context handler macros */ |
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290 | |
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291 | /* |
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292 | * Fatal Error manager macros |
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293 | * |
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294 | * These macros perform the following functions: |
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295 | * + disable interrupts and halt the CPU |
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296 | */ |
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297 | |
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298 | #define _CPU_Fatal_halt( _errorcode ) \ |
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299 | { unsigned32 _mask, _level; \ |
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300 | unsigned32 _error = (_errorcode); \ |
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301 | \ |
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302 | __asm__ volatile ( "ldconst 0x1f0000,%0 ; \ |
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303 | mov %0,%1 ; \ |
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304 | modpc 0,%0,%1 ; \ |
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305 | mov %2,g0 ; \ |
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306 | self: b self " \ |
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307 | : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \ |
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308 | } |
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309 | |
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310 | /* end of Fatal Error Manager macros */ |
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311 | |
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312 | /* |
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313 | * Bitfield handler macros |
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314 | * |
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315 | * These macros perform the following functions: |
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316 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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317 | */ |
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318 | |
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319 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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320 | { unsigned32 _search = (_value); \ |
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321 | \ |
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322 | __asm__ volatile ( "scanbit %0,%1 " \ |
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323 | : "=d" (_search), "=d" (_output) \ |
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324 | : "0" (_search), "1" (_output) ); \ |
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325 | } |
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326 | |
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327 | /* end of Bitfield handler macros */ |
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328 | |
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329 | /* |
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330 | * Priority handler macros |
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331 | * |
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332 | * These macros perform the following functions: |
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333 | * + return a mask with the bit for this major/minor portion of |
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334 | * of thread priority set. |
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335 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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336 | * into an index into the thread ready chain bit maps |
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337 | */ |
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338 | |
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339 | #define _CPU_Priority_Mask( _bit_number ) \ |
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340 | ( 0x8000 >> (_bit_number) ) |
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341 | |
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342 | #define _CPU_Priority_Bits_index( _priority ) \ |
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343 | ( 15 - (_priority) ) |
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344 | |
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345 | /* end of Priority handler macros */ |
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346 | |
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347 | /* functions */ |
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348 | |
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349 | /* |
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350 | * _CPU_Initialize |
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351 | * |
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352 | * This routine performs CPU dependent initialization. |
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353 | */ |
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354 | |
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355 | void _CPU_Initialize( |
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356 | rtems_cpu_table *cpu_table, |
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357 | void (*thread_dispatch) |
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358 | ); |
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359 | |
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360 | /* |
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361 | * _CPU_ISR_install_raw_handler |
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362 | * |
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363 | * This routine installs a "raw" interrupt handler directly into the |
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364 | * processor's vector table. |
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365 | */ |
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366 | |
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367 | void _CPU_ISR_install_raw_handler( |
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368 | unsigned32 vector, |
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369 | proc_ptr new_handler, |
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370 | proc_ptr *old_handler |
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371 | ); |
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372 | |
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373 | /* |
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374 | * _CPU_ISR_install_vector |
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375 | * |
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376 | * This routine installs an interrupt vector. |
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377 | */ |
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378 | |
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379 | void _CPU_ISR_install_vector( |
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380 | unsigned32 vector, |
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381 | proc_ptr new_handler, |
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382 | proc_ptr *old_handler |
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383 | ); |
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384 | |
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385 | /* |
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386 | * _CPU_Install_interrupt_stack |
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387 | * |
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388 | * This routine installs the hardware interrupt stack pointer. |
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389 | */ |
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390 | |
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391 | void _CPU_Install_interrupt_stack( void ); |
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392 | |
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393 | /* |
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394 | * _CPU_Context_switch |
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395 | * |
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396 | * This routine switches from the run context to the heir context. |
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397 | */ |
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398 | |
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399 | void _CPU_Context_switch( |
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400 | Context_Control *run, |
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401 | Context_Control *heir |
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402 | ); |
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403 | |
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404 | /* |
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405 | * _CPU_Context_restore |
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406 | * |
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407 | * This routine is generallu used only to restart self in an |
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408 | * efficient manner and avoid stack conflicts. |
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409 | */ |
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410 | |
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411 | void _CPU_Context_restore( |
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412 | Context_Control *new_context |
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413 | ); |
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414 | |
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415 | /* |
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416 | * _CPU_Context_save_fp |
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417 | * |
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418 | * This routine saves the floating point context passed to it. |
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419 | */ |
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420 | |
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421 | void _CPU_Context_save_fp( |
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422 | void **fp_context_ptr |
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423 | ); |
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424 | |
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425 | /* |
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426 | * _CPU_Context_restore_fp |
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427 | * |
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428 | * This routine restores the floating point context passed to it. |
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429 | */ |
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430 | |
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431 | void _CPU_Context_restore_fp( |
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432 | void **fp_context_ptr |
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433 | ); |
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434 | |
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435 | #ifdef __cplusplus |
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436 | } |
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437 | #endif |
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438 | |
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439 | #endif |
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440 | /* end of include file */ |
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