source: rtems/c/src/exec/score/cpu/i960/cpu.h @ 2e4bc8b4

4.104.114.84.95
Last change on this file since 2e4bc8b4 was 2e4bc8b4, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 7, 1997 at 9:17:42 PM

initialized variable to eliminate warning

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i960 processor family.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#pragma align 4            /* for GNU C structure alignment */
25
26#include <rtems/score/i960.h>              /* pick up machine definitions */
27#ifndef ASM
28#include <rtems/score/i960types.h>
29#endif
30
31#define CPU_INLINE_ENABLE_DISPATCH       FALSE
32#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
33
34/*
35 *  Use the i960's hardware interrupt stack support and have the
36 *  interrupt manager allocate the memory for it.
37 */
38
39#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
40#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
41#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
42
43/*
44 *  Some family members have no FP (SA/KA/CA/CF), others have it built in
45 *  (KB/MC/MX).  There does not appear to be an external coprocessor
46 *  for this family.
47 */
48
49#if ( I960_HAS_FPU == 1 )
50#define CPU_HARDWARE_FP     TRUE
51#error "Floating point support for i960 family has been implemented!!!"
52#else
53#define CPU_HARDWARE_FP     FALSE
54#endif
55
56#define CPU_ALL_TASKS_ARE_FP             FALSE
57#define CPU_IDLE_TASK_IS_FP              FALSE
58#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
59
60#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
61#define CPU_STACK_GROWS_UP               TRUE
62#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
63
64/* structures */
65
66/*
67 *  Basic integer context for the i960 family.
68 */
69
70typedef struct {
71  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
72  void       *r1_sp;                  /* (r1)  Stack Pointer */
73  unsigned32  pc;                     /* (pc)  Processor Control */
74  void       *g8;                     /* (g8)  Global Register 8 */
75  void       *g9;                     /* (g9)  Global Register 9 */
76  void       *g10;                    /* (g10) Global Register 10 */
77  void       *g11;                    /* (g11) Global Register 11 */
78  void       *g12;                    /* (g12) Global Register 12 */
79  void       *g13;                    /* (g13) Global Register 13 */
80  unsigned32  g14;                    /* (g14) Global Register 14 */
81  void       *g15_fp;                 /* (g15) Frame Pointer */
82}   Context_Control;
83
84/*
85 *  FP context save area for the i960 Numeric Extension
86 */
87
88typedef struct {
89   unsigned32  fp0_1;                 /* (fp0) first word  */
90   unsigned32  fp0_2;                 /* (fp0) second word */
91   unsigned32  fp0_3;                 /* (fp0) third word  */
92   unsigned32  fp1_1;                 /* (fp1) first word  */
93   unsigned32  fp1_2;                 /* (fp1) second word */
94   unsigned32  fp1_3;                 /* (fp1) third word  */
95   unsigned32  fp2_1;                 /* (fp2) first word  */
96   unsigned32  fp2_2;                 /* (fp2) second word */
97   unsigned32  fp2_3;                 /* (fp2) third word  */
98   unsigned32  fp3_1;                 /* (fp3) first word  */
99   unsigned32  fp3_2;                 /* (fp3) second word */
100   unsigned32  fp3_3;                 /* (fp3) third word  */
101} Context_Control_fp;
102
103/*
104 *  The following structure defines the set of information saved
105 *  on the current stack by RTEMS upon receipt of each interrupt.
106 */
107
108typedef struct {
109  unsigned32   TBD;   /* XXX Fix for this CPU */
110} CPU_Interrupt_frame;
111
112/*
113 *  Call frame for the i960 family.
114 */
115
116typedef struct {
117  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
118  void       *r1_sp;                  /* (r1)  Stack Pointer */
119  void       *r2_rip;                 /* (r2)  Return Instruction Pointer */
120  void       *r3;                     /* (r3)  Local Register 3 */
121  void       *r4;                     /* (r4)  Local Register 4 */
122  void       *r5;                     /* (r5)  Local Register 5 */
123  void       *r6;                     /* (r6)  Local Register 6 */
124  void       *r7;                     /* (r7)  Local Register 7 */
125  void       *r8;                     /* (r8)  Local Register 8 */
126  void       *r9;                     /* (r9)  Local Register 9 */
127  void       *r10;                    /* (r10) Local Register 10 */
128  void       *r11;                    /* (r11) Local Register 11 */
129  void       *r12;                    /* (r12) Local Register 12 */
130  void       *r13;                    /* (r13) Local Register 13 */
131  void       *r14;                    /* (r14) Local Register 14 */
132  void       *r15;                    /* (r15) Local Register 15 */
133  /* XXX Looks like sometimes there is FP stuff here (MC manual)? */
134}   CPU_Call_frame;
135
136/*
137 *  The following table contains the information required to configure
138 *  the i960 specific parameters.
139 */
140
141typedef struct {
142  void       (*pretasking_hook)( void );
143  void       (*predriver_hook)( void );
144  void       (*postdriver_hook)( void );
145  void       (*idle_task)( void );
146  boolean      do_zero_of_workspace;
147  unsigned32   interrupt_stack_size;
148  unsigned32   extra_mpci_receive_server_stack;
149  void *     (*stack_allocate_hook)( unsigned32 );
150  void       (*stack_free_hook)( void* );
151  /* end of fields required on all CPUs */
152
153#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
154  i960ca_PRCB *Prcb;
155#endif
156}   rtems_cpu_table;
157
158/* variables */
159
160SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
161SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
162
163/* constants */
164
165/*
166 *  This defines the number of levels and the mask used to pick those
167 *  bits out of a thread mode.
168 */
169
170#define CPU_MODES_INTERRUPT_LEVEL  0x0000001f  /* interrupt level in mode */
171#define CPU_MODES_INTERRUPT_MASK   0x0000001f  /* interrupt level in mode */
172
173/*
174 *  context size area for floating point
175 */
176
177#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
178
179/*
180 *  extra stack required by the MPCI receive server thread
181 */
182
183#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE)
184
185/*
186 *  i960 family supports 256 distinct vectors.
187 */
188
189#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
190#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
191
192/*
193 *  Minimum size of a thread's stack.
194 *
195 *  NOTE:  See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK
196 */
197
198#define CPU_STACK_MINIMUM_SIZE          2048
199
200/*
201 *  i960 is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
202 */
203
204#define CPU_ALIGNMENT                   4
205#define CPU_HEAP_ALIGNMENT              CPU_ALIGNMENT
206#define CPU_PARTITION_ALIGNMENT         CPU_ALIGNMENT
207
208/*
209 * i960ca stack requires 16 byte alignment
210 *
211 *  NOTE:  This factor may need to be family member dependent.
212 */
213
214#define CPU_STACK_ALIGNMENT        16
215
216/* macros */
217
218/*
219 *  ISR handler macros
220 *
221 *  These macros perform the following functions:
222 *     + disable all maskable CPU interrupts
223 *     + restore previous interrupt level (enable)
224 *     + temporarily restore interrupts (flash)
225 *     + set a particular level
226 */
227
228#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level )
229#define _CPU_ISR_Enable( _level )  i960_enable_interrupts( _level )
230#define _CPU_ISR_Flash( _level )   i960_flash_interrupts( _level )
231
232#define _CPU_ISR_Set_level( newlevel ) \
233  { \
234    unsigned32 _mask = 0; \
235    unsigned32 _level = (newlevel); \
236    \
237    __asm__ volatile ( "ldconst 0x1f0000,%0; \
238                    modpc   0,%0,%1"     : "=d" (_mask), "=d" (_level) \
239                                         : "0"  (_mask), "1" (_level) \
240    ); \
241  }
242
243unsigned32 _CPU_ISR_Get_level( void );
244
245/* ISR handler section macros */
246
247/*
248 *  Context handler macros
249 *
250 *  These macros perform the following functions:
251 *     + initialize a context area
252 *     + restart the current thread
253 *     + calculate the initial pointer into a FP context area
254 *     + initialize an FP context area
255 */
256
257#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
258                                  _isr, _entry, _is_fp ) \
259 { CPU_Call_frame *_texit_frame; \
260   unsigned32 _mask; \
261   unsigned32 _base_pc; \
262   unsigned32  _stack_tmp; \
263   void       *_stack; \
264   \
265  _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \
266  _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
267  _stack = (void *) _stack_tmp; \
268   \
269   __asm__ volatile ( "flushreg" : : );   /* flush register cache */ \
270   \
271   (_the_context)->r0_pfp = _stack; \
272   (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \
273   (_the_context)->r1_sp  = _stack + (2 * sizeof(CPU_Call_frame)); \
274   __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \
275                  "modpc   0,0,%1 ; " \
276                  "andnot  %0,%1,%1 ; " \
277                  : "=d" (_mask), "=d" (_base_pc) : ); \
278   (_the_context)->pc     = _base_pc | ((_isr) << 16); \
279   (_the_context)->g14    = 0; \
280   \
281   _texit_frame         = (CPU_Call_frame *)_stack; \
282   _texit_frame->r0_pfp = NULL; \
283   _texit_frame->r1_sp  = (_the_context)->g15_fp; \
284   _texit_frame->r2_rip = (_entry); \
285 }
286
287#define _CPU_Context_Restart_self( _the_context ) \
288   _CPU_Context_restore( (_the_context) );
289
290#define _CPU_Context_Fp_start( _base, _offset )         NULL
291
292#define _CPU_Context_Initialize_fp( _fp_area )
293
294/* end of Context handler macros */
295
296/*
297 *  Fatal Error manager macros
298 *
299 *  These macros perform the following functions:
300 *    + disable interrupts and halt the CPU
301 */
302
303#define _CPU_Fatal_halt( _errorcode ) \
304  { unsigned32 _mask, _level; \
305    unsigned32 _error = (_errorcode); \
306    \
307    __asm__ volatile ( "ldconst 0x1f0000,%0 ; \
308                    mov     %0,%1 ; \
309                    modpc   0,%0,%1 ; \
310                    mov     %2,g0 ; \
311            self:   b       self " \
312                    : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \
313  }
314
315/* end of Fatal Error Manager macros */
316
317/*
318 *  Bitfield handler macros
319 *
320 *  These macros perform the following functions:
321 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
322 */
323
324#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
325#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
326
327#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
328  { unsigned32 _search = (_value); \
329    \
330    (_output) = 0; /* to prevent warnings */ \
331    __asm__ volatile ( "scanbit   %0,%1  " \
332                    : "=d" (_search), "=d" (_output) \
333                    : "0"  (_search), "1"  (_output) ); \
334  }
335
336/* end of Bitfield handler macros */
337
338/*
339 *  Priority handler macros
340 *
341 *  These macros perform the following functions:
342 *    + return a mask with the bit for this major/minor portion of
343 *      of thread priority set.
344 *    + translate the bit number returned by "Bitfield_find_first_bit"
345 *      into an index into the thread ready chain bit maps
346 */
347
348#define _CPU_Priority_Mask( _bit_number ) \
349   ( 0x8000 >> (_bit_number) )
350
351#define _CPU_Priority_bits_index( _priority ) \
352   ( 15 - (_priority) )
353
354/* end of Priority handler macros */
355
356/* functions */
357
358/*
359 *  _CPU_Initialize
360 *
361 *  This routine performs CPU dependent initialization.
362 */
363
364void _CPU_Initialize(
365  rtems_cpu_table  *cpu_table,
366  void      (*thread_dispatch)
367);
368
369/*
370 *  _CPU_ISR_install_raw_handler
371 *
372 *  This routine installs a "raw" interrupt handler directly into the
373 *  processor's vector table.
374 */
375 
376void _CPU_ISR_install_raw_handler(
377  unsigned32  vector,
378  proc_ptr    new_handler,
379  proc_ptr   *old_handler
380);
381
382/*
383 *  _CPU_ISR_install_vector
384 *
385 *  This routine installs an interrupt vector.
386 */
387
388void _CPU_ISR_install_vector(
389  unsigned32  vector,
390  proc_ptr    new_handler,
391  proc_ptr   *old_handler
392);
393
394/*
395 *  _CPU_Install_interrupt_stack
396 *
397 *  This routine installs the hardware interrupt stack pointer.
398 */
399
400void _CPU_Install_interrupt_stack( void );
401
402/*
403 *  _CPU_Context_switch
404 *
405 *  This routine switches from the run context to the heir context.
406 */
407
408void _CPU_Context_switch(
409  Context_Control  *run,
410  Context_Control  *heir
411);
412
413/*
414 *  _CPU_Context_restore
415 *
416 *  This routine is generallu used only to restart self in an
417 *  efficient manner and avoid stack conflicts.
418 */
419
420void _CPU_Context_restore(
421  Context_Control *new_context
422);
423
424/*
425 *  _CPU_Context_save_fp
426 *
427 *  This routine saves the floating point context passed to it.
428 */
429
430void _CPU_Context_save_fp(
431  void        **fp_context_ptr
432);
433
434/*
435 *  _CPU_Context_restore_fp
436 *
437 *  This routine restores the floating point context passed to it.
438 */
439
440void _CPU_Context_restore_fp(
441  void        **fp_context_ptr
442);
443
444#ifdef __cplusplus
445}
446#endif
447
448#endif
449/* end of include file */
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