[ac7d5ef0] | 1 | /* cpu.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the Intel |
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| 4 | * i960 processor family. |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * All rights assigned to U.S. Government, 1994. |
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| 9 | * |
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| 10 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 11 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 12 | * notice must appear in all copies of this file and its derivatives. |
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| 13 | * |
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| 14 | * $Id$ |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef __CPU_h |
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| 18 | #define __CPU_h |
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| 19 | |
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| 20 | #ifdef __cplusplus |
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| 21 | extern "C" { |
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| 22 | #endif |
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| 23 | |
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| 24 | #pragma align 4 /* for GNU C structure alignment */ |
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| 25 | |
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[b9181082] | 26 | #include <rtems/score/i960.h> /* pick up machine definitions */ |
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[88d594a] | 27 | #ifndef ASM |
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[5e9b32b] | 28 | #include <rtems/score/i960types.h> |
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[88d594a] | 29 | #endif |
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[ac7d5ef0] | 30 | |
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| 31 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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| 32 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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| 33 | |
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| 34 | /* |
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| 35 | * Use the i960's hardware interrupt stack support and have the |
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| 36 | * interrupt manager allocate the memory for it. |
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| 37 | */ |
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| 38 | |
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| 39 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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| 40 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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| 41 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 42 | |
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| 43 | /* |
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| 44 | * Some family members have no FP (SA/KA/CA/CF), others have it built in |
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| 45 | * (KB/MC/MX). There does not appear to be an external coprocessor |
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| 46 | * for this family. |
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| 47 | */ |
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| 48 | |
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| 49 | #if ( I960_HAS_FPU == 1 ) |
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| 50 | #define CPU_HARDWARE_FP TRUE |
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| 51 | #error "Floating point support for i960 family has been implemented!!!" |
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| 52 | #else |
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| 53 | #define CPU_HARDWARE_FP FALSE |
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| 54 | #endif |
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| 55 | |
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| 56 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 57 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 58 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 59 | |
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| 60 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 61 | #define CPU_STACK_GROWS_UP TRUE |
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| 62 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) |
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| 63 | |
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| 64 | /* structures */ |
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| 65 | |
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| 66 | /* |
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| 67 | * Basic integer context for the i960 family. |
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| 68 | */ |
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| 69 | |
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| 70 | typedef struct { |
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| 71 | void *r0_pfp; /* (r0) Previous Frame Pointer */ |
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| 72 | void *r1_sp; /* (r1) Stack Pointer */ |
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| 73 | unsigned32 pc; /* (pc) Processor Control */ |
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| 74 | void *g8; /* (g8) Global Register 8 */ |
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| 75 | void *g9; /* (g9) Global Register 9 */ |
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| 76 | void *g10; /* (g10) Global Register 10 */ |
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| 77 | void *g11; /* (g11) Global Register 11 */ |
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| 78 | void *g12; /* (g12) Global Register 12 */ |
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| 79 | void *g13; /* (g13) Global Register 13 */ |
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| 80 | unsigned32 g14; /* (g14) Global Register 14 */ |
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| 81 | void *g15_fp; /* (g15) Frame Pointer */ |
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| 82 | } Context_Control; |
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| 83 | |
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| 84 | /* |
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| 85 | * FP context save area for the i960 Numeric Extension |
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| 86 | */ |
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| 87 | |
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| 88 | typedef struct { |
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| 89 | unsigned32 fp0_1; /* (fp0) first word */ |
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| 90 | unsigned32 fp0_2; /* (fp0) second word */ |
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| 91 | unsigned32 fp0_3; /* (fp0) third word */ |
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| 92 | unsigned32 fp1_1; /* (fp1) first word */ |
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| 93 | unsigned32 fp1_2; /* (fp1) second word */ |
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| 94 | unsigned32 fp1_3; /* (fp1) third word */ |
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| 95 | unsigned32 fp2_1; /* (fp2) first word */ |
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| 96 | unsigned32 fp2_2; /* (fp2) second word */ |
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| 97 | unsigned32 fp2_3; /* (fp2) third word */ |
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| 98 | unsigned32 fp3_1; /* (fp3) first word */ |
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| 99 | unsigned32 fp3_2; /* (fp3) second word */ |
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| 100 | unsigned32 fp3_3; /* (fp3) third word */ |
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| 101 | } Context_Control_fp; |
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| 102 | |
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| 103 | /* |
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| 104 | * The following structure defines the set of information saved |
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| 105 | * on the current stack by RTEMS upon receipt of each interrupt. |
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| 106 | */ |
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| 107 | |
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| 108 | typedef struct { |
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| 109 | unsigned32 TBD; /* XXX Fix for this CPU */ |
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| 110 | } CPU_Interrupt_frame; |
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| 111 | |
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| 112 | /* |
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| 113 | * Call frame for the i960 family. |
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| 114 | */ |
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| 115 | |
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| 116 | typedef struct { |
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| 117 | void *r0_pfp; /* (r0) Previous Frame Pointer */ |
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| 118 | void *r1_sp; /* (r1) Stack Pointer */ |
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| 119 | void *r2_rip; /* (r2) Return Instruction Pointer */ |
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| 120 | void *r3; /* (r3) Local Register 3 */ |
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| 121 | void *r4; /* (r4) Local Register 4 */ |
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| 122 | void *r5; /* (r5) Local Register 5 */ |
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| 123 | void *r6; /* (r6) Local Register 6 */ |
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| 124 | void *r7; /* (r7) Local Register 7 */ |
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| 125 | void *r8; /* (r8) Local Register 8 */ |
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| 126 | void *r9; /* (r9) Local Register 9 */ |
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| 127 | void *r10; /* (r10) Local Register 10 */ |
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| 128 | void *r11; /* (r11) Local Register 11 */ |
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| 129 | void *r12; /* (r12) Local Register 12 */ |
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| 130 | void *r13; /* (r13) Local Register 13 */ |
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| 131 | void *r14; /* (r14) Local Register 14 */ |
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| 132 | void *r15; /* (r15) Local Register 15 */ |
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| 133 | /* XXX Looks like sometimes there is FP stuff here (MC manual)? */ |
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| 134 | } CPU_Call_frame; |
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| 135 | |
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| 136 | /* |
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| 137 | * The following table contains the information required to configure |
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| 138 | * the i960 specific parameters. |
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| 139 | */ |
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| 140 | |
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| 141 | typedef struct { |
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| 142 | void (*pretasking_hook)( void ); |
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| 143 | void (*predriver_hook)( void ); |
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| 144 | void (*postdriver_hook)( void ); |
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| 145 | void (*idle_task)( void ); |
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| 146 | boolean do_zero_of_workspace; |
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| 147 | unsigned32 interrupt_stack_size; |
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[75f09e5] | 148 | unsigned32 extra_mpci_receive_server_stack; |
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[96981e3a] | 149 | void * (*stack_allocate_hook)( unsigned32 ); |
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| 150 | void (*stack_free_hook)( void* ); |
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| 151 | /* end of fields required on all CPUs */ |
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| 152 | |
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[ac7d5ef0] | 153 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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| 154 | i960ca_PRCB *Prcb; |
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| 155 | #endif |
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| 156 | } rtems_cpu_table; |
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| 157 | |
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| 158 | /* variables */ |
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| 159 | |
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[c627b2a3] | 160 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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| 161 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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[ac7d5ef0] | 162 | |
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| 163 | /* constants */ |
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| 164 | |
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| 165 | /* |
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| 166 | * This defines the number of levels and the mask used to pick those |
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| 167 | * bits out of a thread mode. |
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| 168 | */ |
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| 169 | |
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| 170 | #define CPU_MODES_INTERRUPT_LEVEL 0x0000001f /* interrupt level in mode */ |
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| 171 | #define CPU_MODES_INTERRUPT_MASK 0x0000001f /* interrupt level in mode */ |
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| 172 | |
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| 173 | /* |
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| 174 | * context size area for floating point |
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| 175 | */ |
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| 176 | |
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| 177 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 178 | |
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| 179 | /* |
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[75f09e5] | 180 | * extra stack required by the MPCI receive server thread |
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[ac7d5ef0] | 181 | */ |
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| 182 | |
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[75f09e5] | 183 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE) |
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[ac7d5ef0] | 184 | |
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| 185 | /* |
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| 186 | * i960 family supports 256 distinct vectors. |
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| 187 | */ |
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| 188 | |
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[9700578] | 189 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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| 190 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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[ac7d5ef0] | 191 | |
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| 192 | /* |
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| 193 | * Minimum size of a thread's stack. |
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| 194 | * |
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[75f09e5] | 195 | * NOTE: See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK |
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[ac7d5ef0] | 196 | */ |
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| 197 | |
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[3652ad35] | 198 | #define CPU_STACK_MINIMUM_SIZE 2048 |
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[ac7d5ef0] | 199 | |
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| 200 | /* |
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| 201 | * i960 is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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| 202 | */ |
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| 203 | |
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| 204 | #define CPU_ALIGNMENT 4 |
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| 205 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 206 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 207 | |
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| 208 | /* |
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| 209 | * i960ca stack requires 16 byte alignment |
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| 210 | * |
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| 211 | * NOTE: This factor may need to be family member dependent. |
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| 212 | */ |
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| 213 | |
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| 214 | #define CPU_STACK_ALIGNMENT 16 |
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| 215 | |
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| 216 | /* macros */ |
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| 217 | |
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| 218 | /* |
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| 219 | * ISR handler macros |
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| 220 | * |
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| 221 | * These macros perform the following functions: |
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| 222 | * + disable all maskable CPU interrupts |
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| 223 | * + restore previous interrupt level (enable) |
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| 224 | * + temporarily restore interrupts (flash) |
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| 225 | * + set a particular level |
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| 226 | */ |
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| 227 | |
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| 228 | #define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level ) |
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| 229 | #define _CPU_ISR_Enable( _level ) i960_enable_interrupts( _level ) |
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| 230 | #define _CPU_ISR_Flash( _level ) i960_flash_interrupts( _level ) |
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| 231 | |
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| 232 | #define _CPU_ISR_Set_level( newlevel ) \ |
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| 233 | { \ |
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| 234 | unsigned32 _mask, _level=(newlevel); \ |
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| 235 | \ |
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| 236 | __asm__ volatile ( "ldconst 0x1f0000,%0; \ |
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| 237 | modpc 0,%0,%1" : "=d" (_mask), "=d" (_level) \ |
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| 238 | : "0" (_mask), "1" (_level) \ |
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| 239 | ); \ |
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| 240 | } |
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| 241 | |
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[3a4ae6c] | 242 | unsigned32 _CPU_ISR_Get_level( void ); |
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| 243 | |
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[ac7d5ef0] | 244 | /* ISR handler section macros */ |
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| 245 | |
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| 246 | /* |
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| 247 | * Context handler macros |
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| 248 | * |
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| 249 | * These macros perform the following functions: |
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| 250 | * + initialize a context area |
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| 251 | * + restart the current thread |
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| 252 | * + calculate the initial pointer into a FP context area |
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| 253 | * + initialize an FP context area |
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| 254 | */ |
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| 255 | |
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| 256 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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[9700578] | 257 | _isr, _entry, _is_fp ) \ |
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[ac7d5ef0] | 258 | { CPU_Call_frame *_texit_frame; \ |
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| 259 | unsigned32 _mask; \ |
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| 260 | unsigned32 _base_pc; \ |
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| 261 | unsigned32 _stack_tmp; \ |
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| 262 | void *_stack; \ |
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| 263 | \ |
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| 264 | _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \ |
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| 265 | _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \ |
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| 266 | _stack = (void *) _stack_tmp; \ |
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| 267 | \ |
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| 268 | __asm__ volatile ( "flushreg" : : ); /* flush register cache */ \ |
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| 269 | \ |
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| 270 | (_the_context)->r0_pfp = _stack; \ |
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| 271 | (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \ |
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| 272 | (_the_context)->r1_sp = _stack + (2 * sizeof(CPU_Call_frame)); \ |
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| 273 | __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \ |
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| 274 | "modpc 0,0,%1 ; " \ |
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| 275 | "andnot %0,%1,%1 ; " \ |
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| 276 | : "=d" (_mask), "=d" (_base_pc) : ); \ |
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| 277 | (_the_context)->pc = _base_pc | ((_isr) << 16); \ |
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| 278 | (_the_context)->g14 = 0; \ |
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| 279 | \ |
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| 280 | _texit_frame = (CPU_Call_frame *)_stack; \ |
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| 281 | _texit_frame->r0_pfp = NULL; \ |
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| 282 | _texit_frame->r1_sp = (_the_context)->g15_fp; \ |
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| 283 | _texit_frame->r2_rip = (_entry); \ |
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| 284 | } |
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| 285 | |
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| 286 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 287 | _CPU_Context_restore( (_the_context) ); |
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| 288 | |
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| 289 | #define _CPU_Context_Fp_start( _base, _offset ) NULL |
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| 290 | |
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| 291 | #define _CPU_Context_Initialize_fp( _fp_area ) |
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| 292 | |
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| 293 | /* end of Context handler macros */ |
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| 294 | |
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| 295 | /* |
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| 296 | * Fatal Error manager macros |
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| 297 | * |
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| 298 | * These macros perform the following functions: |
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| 299 | * + disable interrupts and halt the CPU |
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| 300 | */ |
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| 301 | |
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| 302 | #define _CPU_Fatal_halt( _errorcode ) \ |
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| 303 | { unsigned32 _mask, _level; \ |
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| 304 | unsigned32 _error = (_errorcode); \ |
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| 305 | \ |
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| 306 | __asm__ volatile ( "ldconst 0x1f0000,%0 ; \ |
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| 307 | mov %0,%1 ; \ |
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| 308 | modpc 0,%0,%1 ; \ |
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| 309 | mov %2,g0 ; \ |
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| 310 | self: b self " \ |
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| 311 | : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \ |
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| 312 | } |
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| 313 | |
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| 314 | /* end of Fatal Error Manager macros */ |
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| 315 | |
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| 316 | /* |
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| 317 | * Bitfield handler macros |
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| 318 | * |
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| 319 | * These macros perform the following functions: |
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| 320 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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| 321 | */ |
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| 322 | |
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[9700578] | 323 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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| 324 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
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| 325 | |
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[ac7d5ef0] | 326 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 327 | { unsigned32 _search = (_value); \ |
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| 328 | \ |
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| 329 | __asm__ volatile ( "scanbit %0,%1 " \ |
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| 330 | : "=d" (_search), "=d" (_output) \ |
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| 331 | : "0" (_search), "1" (_output) ); \ |
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| 332 | } |
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| 333 | |
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| 334 | /* end of Bitfield handler macros */ |
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| 335 | |
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| 336 | /* |
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| 337 | * Priority handler macros |
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| 338 | * |
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| 339 | * These macros perform the following functions: |
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| 340 | * + return a mask with the bit for this major/minor portion of |
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| 341 | * of thread priority set. |
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| 342 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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| 343 | * into an index into the thread ready chain bit maps |
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| 344 | */ |
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| 345 | |
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| 346 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 347 | ( 0x8000 >> (_bit_number) ) |
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| 348 | |
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[9700578] | 349 | #define _CPU_Priority_bits_index( _priority ) \ |
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[ac7d5ef0] | 350 | ( 15 - (_priority) ) |
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| 351 | |
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| 352 | /* end of Priority handler macros */ |
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| 353 | |
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| 354 | /* functions */ |
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| 355 | |
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| 356 | /* |
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| 357 | * _CPU_Initialize |
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| 358 | * |
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| 359 | * This routine performs CPU dependent initialization. |
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| 360 | */ |
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| 361 | |
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| 362 | void _CPU_Initialize( |
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| 363 | rtems_cpu_table *cpu_table, |
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| 364 | void (*thread_dispatch) |
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| 365 | ); |
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| 366 | |
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[637df35] | 367 | /* |
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| 368 | * _CPU_ISR_install_raw_handler |
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| 369 | * |
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| 370 | * This routine installs a "raw" interrupt handler directly into the |
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| 371 | * processor's vector table. |
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| 372 | */ |
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| 373 | |
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| 374 | void _CPU_ISR_install_raw_handler( |
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| 375 | unsigned32 vector, |
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| 376 | proc_ptr new_handler, |
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| 377 | proc_ptr *old_handler |
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| 378 | ); |
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| 379 | |
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[ac7d5ef0] | 380 | /* |
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| 381 | * _CPU_ISR_install_vector |
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| 382 | * |
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| 383 | * This routine installs an interrupt vector. |
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| 384 | */ |
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| 385 | |
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| 386 | void _CPU_ISR_install_vector( |
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| 387 | unsigned32 vector, |
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| 388 | proc_ptr new_handler, |
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| 389 | proc_ptr *old_handler |
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| 390 | ); |
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| 391 | |
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| 392 | /* |
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| 393 | * _CPU_Install_interrupt_stack |
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| 394 | * |
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| 395 | * This routine installs the hardware interrupt stack pointer. |
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| 396 | */ |
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| 397 | |
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| 398 | void _CPU_Install_interrupt_stack( void ); |
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| 399 | |
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| 400 | /* |
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| 401 | * _CPU_Context_switch |
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| 402 | * |
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| 403 | * This routine switches from the run context to the heir context. |
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| 404 | */ |
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| 405 | |
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| 406 | void _CPU_Context_switch( |
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| 407 | Context_Control *run, |
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| 408 | Context_Control *heir |
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| 409 | ); |
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| 410 | |
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| 411 | /* |
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| 412 | * _CPU_Context_restore |
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| 413 | * |
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| 414 | * This routine is generallu used only to restart self in an |
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| 415 | * efficient manner and avoid stack conflicts. |
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| 416 | */ |
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| 417 | |
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| 418 | void _CPU_Context_restore( |
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| 419 | Context_Control *new_context |
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| 420 | ); |
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| 421 | |
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| 422 | /* |
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| 423 | * _CPU_Context_save_fp |
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| 424 | * |
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| 425 | * This routine saves the floating point context passed to it. |
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| 426 | */ |
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| 427 | |
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| 428 | void _CPU_Context_save_fp( |
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| 429 | void **fp_context_ptr |
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| 430 | ); |
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| 431 | |
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| 432 | /* |
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| 433 | * _CPU_Context_restore_fp |
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| 434 | * |
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| 435 | * This routine restores the floating point context passed to it. |
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| 436 | */ |
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| 437 | |
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| 438 | void _CPU_Context_restore_fp( |
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| 439 | void **fp_context_ptr |
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| 440 | ); |
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| 441 | |
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| 442 | #ifdef __cplusplus |
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| 443 | } |
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| 444 | #endif |
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| 445 | |
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| 446 | #endif |
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| 447 | /* end of include file */ |
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