source: rtems/c/src/exec/score/cpu/i960/cpu.c @ afd63b7

4.104.114.84.95
Last change on this file since afd63b7 was afd63b7, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 13, 2000 at 10:57:19 PM

Added crude i960ka support.

  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 *  Intel i960CA Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14/*
15 * 1999/04/26: added support for Intel i960RP
16 */
17
18#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
19#elif defined(__i960RP__)
20#elif defined(__i960KA__)
21
22#else
23#warning "***  ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY  ***"
24#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
25#endif
26
27#include <rtems/system.h>
28#include <rtems/score/isr.h>
29
30/*  _CPU_Initialize
31 *
32 *  This routine performs processor dependent initialization.
33 *
34 *  INPUT PARAMETERS:
35 *    cpu_table       - CPU table to initialize
36 *    thread_dispatch - address of disptaching routine
37 *
38 *  OUTPUT PARAMETERS: NONE
39 */
40
41void _CPU_Initialize(
42  rtems_cpu_table  *cpu_table,
43  void      (*thread_dispatch)      /* ignored on this CPU */
44)
45{
46
47  _CPU_Table = *cpu_table;
48
49}
50
51/*PAGE
52 *
53 *  _CPU_ISR_Get_level
54 */
55 
56unsigned32 _CPU_ISR_Get_level( void )
57{
58  unsigned32 level;
59 
60  i960_get_interrupt_level( level );
61 
62  return level;
63}
64
65/*PAGE
66 *
67 *  _CPU_ISR_install_raw_handler
68 */
69
70#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
71#define i960_vector_caching_enabled( _prcb ) \
72   ((_prcb)->control_tbl->icon & 0x2000)
73#elif defined(__i960RP__)
74#define i960_vector_caching_enabled( _prcb ) \
75   ((*((unsigned int *) ICON_ADDR)) & 0x2000)
76#elif defined(__i960KA__)
77#define i960_vector_caching_enabled( _prcb ) 0
78#endif
79
80void _CPU_ISR_install_raw_handler(
81  unsigned32  vector,
82  proc_ptr    new_handler,
83  proc_ptr   *old_handler
84)
85{
86  i960_PRCB   *prcb = _CPU_Table.Prcb;
87  proc_ptr    *cached_intr_tbl = NULL;
88
89  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
90   *  in the Interrupt Table are used to manage pending interrupts.
91   *  Thus vector 8, the first valid vector number, is actually in
92   *  slot 9 in the table.
93   */
94
95  *old_handler = prcb->intr_tbl[ vector + 1 ];
96
97  prcb->intr_tbl[ vector + 1 ] = new_handler;
98
99  if ( i960_vector_caching_enabled( prcb ) )
100    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
101      cached_intr_tbl[ vector >> 4 ] = new_handler;
102}
103
104/*PAGE
105 *
106 *  _CPU__ISR_install_vector
107 *
108 *  Install the RTEMS vector wrapper in the CPU's interrupt table.
109 *
110 *  Input parameters:
111 *    vector      - interrupt vector number
112 *    old_handler - former ISR for this vector number
113 *    new_handler - replacement ISR for this vector number
114 *
115 *  Output parameters:  NONE
116 *
117 */
118
119void _CPU_ISR_install_vector(
120  unsigned32  vector,
121  proc_ptr    new_handler,
122  proc_ptr   *old_handler
123)
124{
125  proc_ptr ignored;
126
127  *old_handler = _ISR_Vector_table[ vector ];
128
129  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
130
131  _ISR_Vector_table[ vector ] = new_handler;
132}
133
134/*PAGE
135 *
136 *  _CPU_Install_interrupt_stack
137 */
138
139#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
140#define soft_reset( prcb ) \
141 { register i960_PRCB *_prcb = (prcb); \
142   register unsigned32  *_next=0; \
143   register unsigned32   _cmd  = 0x30000; \
144   asm volatile( "lda    next,%1; \
145                  sysctl %0,%1,%2; \
146            next: mov    g0,g0" \
147                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
148                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
149 }
150#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
151#define soft_reset( prcb ) \
152 { register i960_PRCB *_prcb = (prcb); \
153   register unsigned32  *_next=0; \
154   register unsigned32   _cmd  = 0x300; \
155   asm volatile( "lda    next,%1; \
156                  sysctl %0,%1,%2; \
157            next: mov    g0,g0" \
158                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
159                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
160 }
161#elif defined(__i960KA__)
162#define soft_reset( prcb )
163#endif
164
165void _CPU_Install_interrupt_stack( void )
166{
167  i960_PRCB *prcb = _CPU_Table.Prcb;
168  unsigned32   level;
169#if defined(__i960RP__) || defined(__i960_RP__)
170  unsigned32 *isp = (int *) ISP_ADDR;
171#endif
172
173  /*
174   *  Set the Interrupt Stack in the PRCB and force a reload of it.
175   *  Interrupts are disabled for safety.
176   */
177
178  _CPU_ISR_Disable( level );
179
180  prcb->intr_stack = _CPU_Interrupt_stack_low;
181
182#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
183    soft_reset( prcb );
184#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
185    *isp = (unsigned32) prcb->intr_stack;
186#endif
187
188  _CPU_ISR_Enable( level );
189}
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