source: rtems/c/src/exec/score/cpu/i960/cpu.c @ 752badac

4.104.114.84.95
Last change on this file since 752badac was 752badac, checked in by Joel Sherrill <joel.sherrill@…>, on 01/14/00 at 14:55:37

Removed warning.

  • Property mode set to 100644
File size: 4.4 KB
Line 
1/*
2 *  Intel i960CA Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14/*
15 * 1999/04/26: added support for Intel i960RP
16 */
17
18#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
19#elif defined(__i960RP__)
20#else
21#warning "***  ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY  ***"
22#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
23#endif
24
25#include <rtems/system.h>
26#include <rtems/score/isr.h>
27
28/*  _CPU_Initialize
29 *
30 *  This routine performs processor dependent initialization.
31 *
32 *  INPUT PARAMETERS:
33 *    cpu_table       - CPU table to initialize
34 *    thread_dispatch - address of disptaching routine
35 *
36 *  OUTPUT PARAMETERS: NONE
37 */
38
39void _CPU_Initialize(
40  rtems_cpu_table  *cpu_table,
41  void      (*thread_dispatch)      /* ignored on this CPU */
42)
43{
44
45  _CPU_Table = *cpu_table;
46
47}
48
49/*PAGE
50 *
51 *  _CPU_ISR_Get_level
52 */
53 
54unsigned32 _CPU_ISR_Get_level( void )
55{
56  unsigned32 level;
57 
58  i960_get_interrupt_level( level );
59 
60  return level;
61}
62
63/*PAGE
64 *
65 *  _CPU_ISR_install_raw_handler
66 */
67
68#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
69#define i960_vector_caching_enabled( _prcb ) \
70   ((_prcb)->control_tbl->icon & 0x2000)
71#elif defined(__i960RP__)
72#define i960_vector_caching_enabled( _prcb ) \
73   ((*((unsigned int *) ICON_ADDR)) & 0x2000)
74#endif
75
76void _CPU_ISR_install_raw_handler(
77  unsigned32  vector,
78  proc_ptr    new_handler,
79  proc_ptr   *old_handler
80)
81{
82  i960_PRCB   *prcb = _CPU_Table.Prcb;
83  proc_ptr    *cached_intr_tbl = NULL;
84
85  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
86   *  in the Interrupt Table are used to manage pending interrupts.
87   *  Thus vector 8, the first valid vector number, is actually in
88   *  slot 9 in the table.
89   */
90
91  *old_handler = prcb->intr_tbl[ vector + 1 ];
92
93  prcb->intr_tbl[ vector + 1 ] = new_handler;
94
95  if ( i960_vector_caching_enabled( prcb ) )
96    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
97      cached_intr_tbl[ vector >> 4 ] = new_handler;
98}
99
100/*PAGE
101 *
102 *  _CPU__ISR_install_vector
103 *
104 *  Install the RTEMS vector wrapper in the CPU's interrupt table.
105 *
106 *  Input parameters:
107 *    vector      - interrupt vector number
108 *    old_handler - former ISR for this vector number
109 *    new_handler - replacement ISR for this vector number
110 *
111 *  Output parameters:  NONE
112 *
113 */
114
115void _CPU_ISR_install_vector(
116  unsigned32  vector,
117  proc_ptr    new_handler,
118  proc_ptr   *old_handler
119)
120{
121  proc_ptr ignored;
122
123  *old_handler = _ISR_Vector_table[ vector ];
124
125  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
126
127  _ISR_Vector_table[ vector ] = new_handler;
128}
129
130/*PAGE
131 *
132 *  _CPU_Install_interrupt_stack
133 */
134
135#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
136#define soft_reset( prcb ) \
137 { register i960_PRCB *_prcb = (prcb); \
138   register unsigned32  *_next=0; \
139   register unsigned32   _cmd  = 0x30000; \
140   asm volatile( "lda    next,%1; \
141                  sysctl %0,%1,%2; \
142            next: mov    g0,g0" \
143                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
144                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
145 }
146#else
147#if defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
148#define soft_reset( prcb ) \
149 { register i960_PRCB *_prcb = (prcb); \
150   register unsigned32  *_next=0; \
151   register unsigned32   _cmd  = 0x300; \
152   asm volatile( "lda    next,%1; \
153                  sysctl %0,%1,%2; \
154            next: mov    g0,g0" \
155                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
156                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
157 }
158#endif
159#endif
160
161void _CPU_Install_interrupt_stack( void )
162{
163  i960_PRCB *prcb = _CPU_Table.Prcb;
164  unsigned32   level;
165#if defined(__i960RP__) || defined(__i960_RP__)
166  unsigned32 *isp = (int *) ISP_ADDR;
167#endif
168
169  /*
170   *  Set the Interrupt Stack in the PRCB and force a reload of it.
171   *  Interrupts are disabled for safety.
172   */
173
174  _CPU_ISR_Disable( level );
175
176    prcb->intr_stack = _CPU_Interrupt_stack_low;
177
178#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
179    soft_reset( prcb );
180#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
181    *isp = (unsigned32) prcb->intr_stack;
182#endif
183
184  _CPU_ISR_Enable( level );
185}
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