source: rtems/c/src/exec/score/cpu/i960/cpu.c @ 702c5f5

4.104.114.84.95
Last change on this file since 702c5f5 was 702c5f5, checked in by Joel Sherrill <joel.sherrill@…>, on 10/27/99 at 15:29:18

The rxgen960 BSP and i960 RPM support was submitted by Mark Bronson
<mark@…> of RAMIX.

  • Property mode set to 100644
File size: 4.4 KB
Line 
1/*
2 *  Intel i960CA Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989-1998.
6 *  On-Line Applications Research Corporation (OAR).
7 *  Copyright assigned to U.S. Government, 1994.
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15/*
16 * 1999/04/26: added support for Intel i960RP
17 */
18
19#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
20#elif defined(__i960RP__)
21#else
22#warning "***  ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY  ***"
23#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
24#endif
25
26#include <rtems/system.h>
27#include <rtems/score/isr.h>
28
29/*  _CPU_Initialize
30 *
31 *  This routine performs processor dependent initialization.
32 *
33 *  INPUT PARAMETERS:
34 *    cpu_table       - CPU table to initialize
35 *    thread_dispatch - address of disptaching routine
36 *
37 *  OUTPUT PARAMETERS: NONE
38 */
39
40void _CPU_Initialize(
41  rtems_cpu_table  *cpu_table,
42  void      (*thread_dispatch)      /* ignored on this CPU */
43)
44{
45
46  _CPU_Table = *cpu_table;
47
48}
49
50/*PAGE
51 *
52 *  _CPU_ISR_Get_level
53 */
54 
55unsigned32 _CPU_ISR_Get_level( void )
56{
57  unsigned32 level;
58 
59  i960_get_interrupt_level( level );
60 
61  return level;
62}
63
64/*PAGE
65 *
66 *  _CPU_ISR_install_raw_handler
67 */
68
69#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
70#define _Is_vector_caching_enabled( _prcb ) \
71   ((_prcb)->control_tbl->icon & 0x2000)
72#elif defined(__i960RP__)
73#define _Is_vector_caching_enabled( _prcb ) \
74   ((*((unsigned int *) ICON_ADDR)) & 0x2000)
75#endif
76
77void _CPU_ISR_install_raw_handler(
78  unsigned32  vector,
79  proc_ptr    new_handler,
80  proc_ptr   *old_handler
81)
82{
83  i960_PRCB   *prcb = _CPU_Table.Prcb;
84  proc_ptr    *cached_intr_tbl = NULL;
85
86  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
87   *  in the Interrupt Table are used to manage pending interrupts.
88   *  Thus vector 8, the first valid vector number, is actually in
89   *  slot 9 in the table.
90   */
91
92  *old_handler = prcb->intr_tbl[ vector + 1 ];
93
94  prcb->intr_tbl[ vector + 1 ] = new_handler;
95
96  if ( _Is_vector_caching_enabled( prcb ) )
97    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
98      cached_intr_tbl[ vector >> 4 ] = new_handler;
99}
100
101/*PAGE
102 *
103 *  _CPU__ISR_install_vector
104 *
105 *  Install the RTEMS vector wrapper in the CPU's interrupt table.
106 *
107 *  Input parameters:
108 *    vector      - interrupt vector number
109 *    old_handler - former ISR for this vector number
110 *    new_handler - replacement ISR for this vector number
111 *
112 *  Output parameters:  NONE
113 *
114 */
115
116void _CPU_ISR_install_vector(
117  unsigned32  vector,
118  proc_ptr    new_handler,
119  proc_ptr   *old_handler
120)
121{
122  proc_ptr ignored;
123
124  *old_handler = _ISR_Vector_table[ vector ];
125
126  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
127
128  _ISR_Vector_table[ vector ] = new_handler;
129}
130
131/*PAGE
132 *
133 *  _CPU_Install_interrupt_stack
134 */
135
136#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
137#define soft_reset( prcb ) \
138 { register i960_PRCB *_prcb = (prcb); \
139   register unsigned32  *_next=0; \
140   register unsigned32   _cmd  = 0x30000; \
141   asm volatile( "lda    next,%1; \
142                  sysctl %0,%1,%2; \
143            next: mov    g0,g0" \
144                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
145                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
146 }
147#else
148#if defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
149#define soft_reset( prcb ) \
150 { register i960_PRCB *_prcb = (prcb); \
151   register unsigned32  *_next=0; \
152   register unsigned32   _cmd  = 0x300; \
153   asm volatile( "lda    next,%1; \
154                  sysctl %0,%1,%2; \
155            next: mov    g0,g0" \
156                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
157                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
158 }
159#endif
160#endif
161
162void _CPU_Install_interrupt_stack( void )
163{
164  i960_PRCB *prcb = _CPU_Table.Prcb;
165  unsigned32   level;
166#if defined(__i960RP__) || defined(__i960_RP__)
167  int *isp = (int *) ISP_ADDR;
168#endif
169
170  /*
171   *  Set the Interrupt Stack in the PRCB and force a reload of it.
172   *  Interrupts are disabled for safety.
173   */
174
175  _CPU_ISR_Disable( level );
176
177    prcb->intr_stack = _CPU_Interrupt_stack_low;
178
179#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
180    soft_reset( prcb );
181#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
182    *isp = prcb->intr_stack;
183#endif
184
185  _CPU_ISR_Enable( level );
186}
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