source: rtems/c/src/exec/score/cpu/i960/cpu.c @ 60b791ad

4.104.114.84.9
Last change on this file since 60b791ad was 60b791ad, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 17, 1998 at 11:46:28 PM

updated copyright to 1998

  • Property mode set to 100644
File size: 3.4 KB
Line 
1/*
2 *  Intel i960CA Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989-1998.
6 *  On-Line Applications Research Corporation (OAR).
7 *  Copyright assigned to U.S. Government, 1994.
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
17#else
18#warning "***    ENTIRE FILE IMPLEMENTED & TESTED FOR CA ONLY     ***"
19#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
20#endif
21
22#include <rtems/system.h>
23#include <rtems/score/isr.h>
24
25/*  _CPU_Initialize
26 *
27 *  This routine performs processor dependent initialization.
28 *
29 *  INPUT PARAMETERS:
30 *    cpu_table       - CPU table to initialize
31 *    thread_dispatch - address of disptaching routine
32 *
33 *  OUTPUT PARAMETERS: NONE
34 */
35
36void _CPU_Initialize(
37  rtems_cpu_table  *cpu_table,
38  void      (*thread_dispatch)      /* ignored on this CPU */
39)
40{
41
42  _CPU_Table = *cpu_table;
43
44}
45
46/*PAGE
47 *
48 *  _CPU_ISR_Get_level
49 */
50 
51unsigned32 _CPU_ISR_Get_level( void )
52{
53  unsigned32 level;
54 
55  i960_get_interrupt_level( level );
56 
57  return level;
58}
59
60/*PAGE
61 *
62 *  _CPU_ISR_install_raw_handler
63 */
64 
65#define _Is_vector_caching_enabled( _prcb ) \
66   ((_prcb)->control_tbl->icon & 0x2000)
67
68void _CPU_ISR_install_raw_handler(
69  unsigned32  vector,
70  proc_ptr    new_handler,
71  proc_ptr   *old_handler
72)
73{
74  i960ca_PRCB *prcb = _CPU_Table.Prcb;
75  proc_ptr    *cached_intr_tbl = NULL;
76
77  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
78   *  in the Interrupt Table are used to manage pending interrupts.
79   *  Thus vector 8, the first valid vector number, is actually in
80   *  slot 9 in the table.
81   */
82
83  *old_handler = prcb->intr_tbl[ vector + 1 ];
84
85  prcb->intr_tbl[ vector + 1 ] = new_handler;
86
87  if ( _Is_vector_caching_enabled( prcb ) )
88    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
89      cached_intr_tbl[ vector >> 4 ] = new_handler;
90}
91
92/*PAGE
93 *
94 *  _CPU__ISR_install_vector
95 *
96 *  Install the RTEMS vector wrapper in the CPU's interrupt table.
97 *
98 *  Input parameters:
99 *    vector      - interrupt vector number
100 *    old_handler - former ISR for this vector number
101 *    new_handler - replacement ISR for this vector number
102 *
103 *  Output parameters:  NONE
104 *
105 */
106
107void _CPU_ISR_install_vector(
108  unsigned32  vector,
109  proc_ptr    new_handler,
110  proc_ptr   *old_handler
111)
112{
113  proc_ptr ignored;
114
115  *old_handler = _ISR_Vector_table[ vector ];
116
117  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
118
119  _ISR_Vector_table[ vector ] = new_handler;
120}
121
122/*PAGE
123 *
124 *  _CPU_Install_interrupt_stack
125 */
126
127#define soft_reset( prcb ) \
128 { register i960ca_PRCB *_prcb = (prcb); \
129   register unsigned32  *_next=0; \
130   register unsigned32   _cmd  = 0x30000; \
131   asm volatile( "lda    next,%1; \
132                  sysctl %0,%1,%2; \
133            next: mov    g0,g0" \
134                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
135                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
136 }
137
138void _CPU_Install_interrupt_stack( void )
139{
140  i960ca_PRCB *prcb = _CPU_Table.Prcb;
141  unsigned32   level;
142
143  /*
144   *  Set the Interrupt Stack in the PRCB and force a reload of it.
145   *  Interrupts are disabled for safety.
146   */
147
148  _CPU_ISR_Disable( level );
149
150    prcb->intr_stack = _CPU_Interrupt_stack_low;
151
152    soft_reset( prcb );
153
154  _CPU_ISR_Enable( level );
155}
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