1 | /* |
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2 | * Intel i960CA Dependent Source |
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3 | * |
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4 | * |
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5 | * COPYRIGHT (c) 1989-1999. |
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6 | * On-Line Applications Research Corporation (OAR). |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.OARcorp.com/rtems/license.html. |
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11 | * |
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12 | * $Id$ |
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13 | */ |
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14 | /* |
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15 | * 1999/04/26: added support for Intel i960RP |
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16 | */ |
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17 | |
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18 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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19 | #elif defined(__i960RP__) |
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20 | #else |
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21 | #warning "*** ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY ***" |
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22 | #warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***" |
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23 | #endif |
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24 | |
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25 | #include <rtems/system.h> |
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26 | #include <rtems/score/isr.h> |
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27 | |
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28 | /* _CPU_Initialize |
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29 | * |
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30 | * This routine performs processor dependent initialization. |
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31 | * |
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32 | * INPUT PARAMETERS: |
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33 | * cpu_table - CPU table to initialize |
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34 | * thread_dispatch - address of disptaching routine |
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35 | * |
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36 | * OUTPUT PARAMETERS: NONE |
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37 | */ |
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38 | |
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39 | void _CPU_Initialize( |
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40 | rtems_cpu_table *cpu_table, |
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41 | void (*thread_dispatch) /* ignored on this CPU */ |
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42 | ) |
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43 | { |
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44 | |
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45 | _CPU_Table = *cpu_table; |
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46 | |
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47 | } |
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48 | |
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49 | /*PAGE |
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50 | * |
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51 | * _CPU_ISR_Get_level |
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52 | */ |
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53 | |
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54 | unsigned32 _CPU_ISR_Get_level( void ) |
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55 | { |
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56 | unsigned32 level; |
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57 | |
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58 | i960_get_interrupt_level( level ); |
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59 | |
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60 | return level; |
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61 | } |
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62 | |
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63 | /*PAGE |
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64 | * |
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65 | * _CPU_ISR_install_raw_handler |
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66 | */ |
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67 | |
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68 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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69 | #define i960_vector_caching_enabled( _prcb ) \ |
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70 | ((_prcb)->control_tbl->icon & 0x2000) |
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71 | #elif defined(__i960RP__) |
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72 | #define i960_vector_caching_enabled( _prcb ) \ |
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73 | ((*((unsigned int *) ICON_ADDR)) & 0x2000) |
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74 | #endif |
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75 | |
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76 | void _CPU_ISR_install_raw_handler( |
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77 | unsigned32 vector, |
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78 | proc_ptr new_handler, |
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79 | proc_ptr *old_handler |
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80 | ) |
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81 | { |
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82 | i960_PRCB *prcb = _CPU_Table.Prcb; |
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83 | proc_ptr *cached_intr_tbl = NULL; |
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84 | |
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85 | /* The i80960CA does not support vectors 0-7. The first 9 entries |
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86 | * in the Interrupt Table are used to manage pending interrupts. |
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87 | * Thus vector 8, the first valid vector number, is actually in |
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88 | * slot 9 in the table. |
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89 | */ |
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90 | |
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91 | *old_handler = prcb->intr_tbl[ vector + 1 ]; |
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92 | |
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93 | prcb->intr_tbl[ vector + 1 ] = new_handler; |
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94 | |
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95 | if ( i960_vector_caching_enabled( prcb ) ) |
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96 | if ( (vector & 0xf) == 0x2 ) /* cacheable? */ |
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97 | cached_intr_tbl[ vector >> 4 ] = new_handler; |
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98 | } |
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99 | |
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100 | /*PAGE |
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101 | * |
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102 | * _CPU__ISR_install_vector |
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103 | * |
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104 | * Install the RTEMS vector wrapper in the CPU's interrupt table. |
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105 | * |
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106 | * Input parameters: |
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107 | * vector - interrupt vector number |
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108 | * old_handler - former ISR for this vector number |
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109 | * new_handler - replacement ISR for this vector number |
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110 | * |
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111 | * Output parameters: NONE |
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112 | * |
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113 | */ |
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114 | |
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115 | void _CPU_ISR_install_vector( |
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116 | unsigned32 vector, |
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117 | proc_ptr new_handler, |
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118 | proc_ptr *old_handler |
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119 | ) |
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120 | { |
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121 | proc_ptr ignored; |
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122 | |
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123 | *old_handler = _ISR_Vector_table[ vector ]; |
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124 | |
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125 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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126 | |
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127 | _ISR_Vector_table[ vector ] = new_handler; |
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128 | } |
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129 | |
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130 | /*PAGE |
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131 | * |
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132 | * _CPU_Install_interrupt_stack |
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133 | */ |
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134 | |
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135 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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136 | #define soft_reset( prcb ) \ |
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137 | { register i960_PRCB *_prcb = (prcb); \ |
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138 | register unsigned32 *_next=0; \ |
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139 | register unsigned32 _cmd = 0x30000; \ |
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140 | asm volatile( "lda next,%1; \ |
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141 | sysctl %0,%1,%2; \ |
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142 | next: mov g0,g0" \ |
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143 | : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ |
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144 | : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ |
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145 | } |
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146 | #else |
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147 | #if defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP) |
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148 | #define soft_reset( prcb ) \ |
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149 | { register i960_PRCB *_prcb = (prcb); \ |
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150 | register unsigned32 *_next=0; \ |
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151 | register unsigned32 _cmd = 0x300; \ |
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152 | asm volatile( "lda next,%1; \ |
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153 | sysctl %0,%1,%2; \ |
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154 | next: mov g0,g0" \ |
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155 | : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ |
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156 | : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ |
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157 | } |
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158 | #endif |
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159 | #endif |
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160 | |
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161 | void _CPU_Install_interrupt_stack( void ) |
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162 | { |
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163 | i960_PRCB *prcb = _CPU_Table.Prcb; |
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164 | unsigned32 level; |
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165 | #if defined(__i960RP__) || defined(__i960_RP__) |
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166 | unsigned32 *isp = (int *) ISP_ADDR; |
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167 | #endif |
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168 | |
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169 | /* |
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170 | * Set the Interrupt Stack in the PRCB and force a reload of it. |
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171 | * Interrupts are disabled for safety. |
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172 | */ |
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173 | |
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174 | _CPU_ISR_Disable( level ); |
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175 | |
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176 | prcb->intr_stack = _CPU_Interrupt_stack_low; |
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177 | |
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178 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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179 | soft_reset( prcb ); |
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180 | #elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP) |
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181 | *isp = (unsigned32) prcb->intr_stack; |
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182 | #endif |
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183 | |
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184 | _CPU_ISR_Enable( level ); |
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185 | } |
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