[ac7d5ef0] | 1 | /* |
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| 2 | * Intel i960CA Dependent Source |
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| 3 | * |
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| 4 | * |
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[60b791ad] | 5 | * COPYRIGHT (c) 1989-1998. |
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[ac7d5ef0] | 6 | * On-Line Applications Research Corporation (OAR). |
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[03f2154e] | 7 | * Copyright assigned to U.S. Government, 1994. |
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[ac7d5ef0] | 8 | * |
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[98e4ebf5] | 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 11 | * http://www.OARcorp.com/rtems/license.html. |
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[ac7d5ef0] | 12 | * |
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| 13 | * $Id$ |
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| 14 | */ |
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[702c5f5] | 15 | /* |
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| 16 | * 1999/04/26: added support for Intel i960RP |
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| 17 | */ |
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[ac7d5ef0] | 18 | |
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| 19 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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[702c5f5] | 20 | #elif defined(__i960RP__) |
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[ac7d5ef0] | 21 | #else |
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[702c5f5] | 22 | #warning "*** ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY ***" |
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[ac7d5ef0] | 23 | #warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***" |
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| 24 | #endif |
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| 25 | |
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| 26 | #include <rtems/system.h> |
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[5e9b32b] | 27 | #include <rtems/score/isr.h> |
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[ac7d5ef0] | 28 | |
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| 29 | /* _CPU_Initialize |
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| 30 | * |
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| 31 | * This routine performs processor dependent initialization. |
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| 32 | * |
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| 33 | * INPUT PARAMETERS: |
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| 34 | * cpu_table - CPU table to initialize |
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| 35 | * thread_dispatch - address of disptaching routine |
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| 36 | * |
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| 37 | * OUTPUT PARAMETERS: NONE |
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| 38 | */ |
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| 39 | |
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| 40 | void _CPU_Initialize( |
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| 41 | rtems_cpu_table *cpu_table, |
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| 42 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 43 | ) |
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| 44 | { |
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| 45 | |
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| 46 | _CPU_Table = *cpu_table; |
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| 47 | |
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| 48 | } |
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| 49 | |
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[3a4ae6c] | 50 | /*PAGE |
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| 51 | * |
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| 52 | * _CPU_ISR_Get_level |
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| 53 | */ |
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| 54 | |
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| 55 | unsigned32 _CPU_ISR_Get_level( void ) |
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| 56 | { |
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| 57 | unsigned32 level; |
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| 58 | |
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| 59 | i960_get_interrupt_level( level ); |
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| 60 | |
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| 61 | return level; |
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| 62 | } |
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| 63 | |
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[637df35] | 64 | /*PAGE |
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| 65 | * |
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| 66 | * _CPU_ISR_install_raw_handler |
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| 67 | */ |
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[702c5f5] | 68 | |
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| 69 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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[ae7325bd] | 70 | #define i960_vector_caching_enabled( _prcb ) \ |
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[637df35] | 71 | ((_prcb)->control_tbl->icon & 0x2000) |
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[702c5f5] | 72 | #elif defined(__i960RP__) |
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[ae7325bd] | 73 | #define i960_vector_caching_enabled( _prcb ) \ |
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[702c5f5] | 74 | ((*((unsigned int *) ICON_ADDR)) & 0x2000) |
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| 75 | #endif |
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[637df35] | 76 | |
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| 77 | void _CPU_ISR_install_raw_handler( |
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| 78 | unsigned32 vector, |
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| 79 | proc_ptr new_handler, |
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| 80 | proc_ptr *old_handler |
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| 81 | ) |
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| 82 | { |
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[702c5f5] | 83 | i960_PRCB *prcb = _CPU_Table.Prcb; |
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[637df35] | 84 | proc_ptr *cached_intr_tbl = NULL; |
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| 85 | |
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| 86 | /* The i80960CA does not support vectors 0-7. The first 9 entries |
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| 87 | * in the Interrupt Table are used to manage pending interrupts. |
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| 88 | * Thus vector 8, the first valid vector number, is actually in |
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| 89 | * slot 9 in the table. |
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| 90 | */ |
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| 91 | |
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| 92 | *old_handler = prcb->intr_tbl[ vector + 1 ]; |
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| 93 | |
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| 94 | prcb->intr_tbl[ vector + 1 ] = new_handler; |
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| 95 | |
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[ae7325bd] | 96 | if ( i960_vector_caching_enabled( prcb ) ) |
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[637df35] | 97 | if ( (vector & 0xf) == 0x2 ) /* cacheable? */ |
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| 98 | cached_intr_tbl[ vector >> 4 ] = new_handler; |
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| 99 | } |
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| 100 | |
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| 101 | /*PAGE |
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| 102 | * |
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| 103 | * _CPU__ISR_install_vector |
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[ac7d5ef0] | 104 | * |
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| 105 | * Install the RTEMS vector wrapper in the CPU's interrupt table. |
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| 106 | * |
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| 107 | * Input parameters: |
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| 108 | * vector - interrupt vector number |
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| 109 | * old_handler - former ISR for this vector number |
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| 110 | * new_handler - replacement ISR for this vector number |
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| 111 | * |
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| 112 | * Output parameters: NONE |
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| 113 | * |
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| 114 | */ |
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| 115 | |
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| 116 | void _CPU_ISR_install_vector( |
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| 117 | unsigned32 vector, |
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| 118 | proc_ptr new_handler, |
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| 119 | proc_ptr *old_handler |
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| 120 | ) |
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| 121 | { |
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[637df35] | 122 | proc_ptr ignored; |
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[ac7d5ef0] | 123 | |
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| 124 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 125 | |
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[637df35] | 126 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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[ac7d5ef0] | 127 | |
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[637df35] | 128 | _ISR_Vector_table[ vector ] = new_handler; |
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[ac7d5ef0] | 129 | } |
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| 130 | |
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| 131 | /*PAGE |
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| 132 | * |
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| 133 | * _CPU_Install_interrupt_stack |
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| 134 | */ |
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| 135 | |
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[702c5f5] | 136 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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[ac7d5ef0] | 137 | #define soft_reset( prcb ) \ |
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[702c5f5] | 138 | { register i960_PRCB *_prcb = (prcb); \ |
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[ac7d5ef0] | 139 | register unsigned32 *_next=0; \ |
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| 140 | register unsigned32 _cmd = 0x30000; \ |
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| 141 | asm volatile( "lda next,%1; \ |
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| 142 | sysctl %0,%1,%2; \ |
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| 143 | next: mov g0,g0" \ |
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| 144 | : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ |
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| 145 | : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ |
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| 146 | } |
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[702c5f5] | 147 | #else |
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| 148 | #if defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP) |
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| 149 | #define soft_reset( prcb ) \ |
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| 150 | { register i960_PRCB *_prcb = (prcb); \ |
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| 151 | register unsigned32 *_next=0; \ |
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| 152 | register unsigned32 _cmd = 0x300; \ |
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| 153 | asm volatile( "lda next,%1; \ |
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| 154 | sysctl %0,%1,%2; \ |
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| 155 | next: mov g0,g0" \ |
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| 156 | : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ |
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| 157 | : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ |
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| 158 | } |
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| 159 | #endif |
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| 160 | #endif |
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[ac7d5ef0] | 161 | |
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| 162 | void _CPU_Install_interrupt_stack( void ) |
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| 163 | { |
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[702c5f5] | 164 | i960_PRCB *prcb = _CPU_Table.Prcb; |
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[ac7d5ef0] | 165 | unsigned32 level; |
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[702c5f5] | 166 | #if defined(__i960RP__) || defined(__i960_RP__) |
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| 167 | int *isp = (int *) ISP_ADDR; |
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| 168 | #endif |
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[ac7d5ef0] | 169 | |
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| 170 | /* |
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| 171 | * Set the Interrupt Stack in the PRCB and force a reload of it. |
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| 172 | * Interrupts are disabled for safety. |
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| 173 | */ |
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| 174 | |
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| 175 | _CPU_ISR_Disable( level ); |
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| 176 | |
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| 177 | prcb->intr_stack = _CPU_Interrupt_stack_low; |
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| 178 | |
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[702c5f5] | 179 | #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) |
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[ac7d5ef0] | 180 | soft_reset( prcb ); |
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[702c5f5] | 181 | #elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP) |
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| 182 | *isp = prcb->intr_stack; |
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| 183 | #endif |
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[ac7d5ef0] | 184 | |
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| 185 | _CPU_ISR_Enable( level ); |
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| 186 | } |
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