source: rtems/c/src/exec/score/cpu/i386/cpu.h @ ecc3fe3

4.104.114.84.95
Last change on this file since ecc3fe3 was ecc3fe3, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 23, 1998 at 4:41:00 PM

IDLE task stack size now specified as a field in the CPU Table for all
ports.

  • Property mode set to 100644
File size: 11.7 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i386 processor.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/i386.h>              /* pick up machine definitions */
25#include <libcpu/cpu.h>
26
27#ifndef ASM
28#include <rtems/score/i386types.h>
29#endif
30
31/* conditional compilation parameters */
32
33#define CPU_INLINE_ENABLE_DISPATCH       TRUE
34#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
35
36/*
37 *  i386 has an RTEMS allocated and managed interrupt stack.
38 */
39
40#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
41#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
42#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
43
44/*
45 *  Does the RTEMS invoke the user's ISR with the vector number and
46 *  a pointer to the saved interrupt frame (1) or just the vector
47 *  number (0)?
48 */
49
50#define CPU_ISR_PASSES_FRAME_POINTER 0
51
52/*
53 *  Some family members have no FP, some have an FPU such as the i387
54 *  for the i386, others have it built in (i486DX, Pentium).
55 */
56
57#if ( I386_HAS_FPU == 1 )
58#define CPU_HARDWARE_FP     TRUE    /* i387 for i386 */
59#else
60#define CPU_HARDWARE_FP     FALSE
61#endif
62
63#define CPU_ALL_TASKS_ARE_FP             FALSE
64#define CPU_IDLE_TASK_IS_FP              FALSE
65#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
66
67#define CPU_STACK_GROWS_UP               FALSE
68#define CPU_STRUCTURE_ALIGNMENT
69
70/*
71 *  Does this port provide a CPU dependent IDLE task implementation?
72 * 
73 *  If TRUE, then the routine _CPU_Thread_Idle_body
74 *  must be provided and is the default IDLE thread body instead of
75 *  _CPU_Thread_Idle_body.
76 *
77 *  If FALSE, then use the generic IDLE thread body if the BSP does
78 *  not provide one.
79 */
80 
81#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
82
83/*
84 *  Define what is required to specify how the network to host conversion
85 *  routines are handled.
86 */
87
88#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
89#define CPU_BIG_ENDIAN                           FALSE
90#define CPU_LITTLE_ENDIAN                        TRUE
91
92/* structures */
93
94/*
95 *  Basic integer context for the i386 family.
96 */
97
98typedef struct {
99  unsigned32  eflags;   /* extended flags register                   */
100  void       *esp;      /* extended stack pointer register           */
101  void       *ebp;      /* extended base pointer register            */
102  unsigned32  ebx;      /* extended bx register                      */
103  unsigned32  esi;      /* extended source index register            */
104  unsigned32  edi;      /* extended destination index flags register */
105}   Context_Control;
106
107/*
108 *  FP context save area for the i387 numeric coprocessors.
109 */
110
111typedef struct {
112  unsigned8   fp_save_area[108];    /* context size area for I80387 */
113                                    /*  28 bytes for environment    */
114} Context_Control_fp;
115
116
117/*
118 *  The following structure defines the set of information saved
119 *  on the current stack by RTEMS upon receipt of execptions.
120 *
121 * idtIndex is either the interrupt number or the trap/exception number.
122 * faultCode is the code pushed by the processor on some exceptions.
123 */
124
125typedef struct {
126  unsigned32  edi;
127  unsigned32  esi;
128  unsigned32  ebp;
129  unsigned32  esp0;
130  unsigned32  ebx;
131  unsigned32  edx;
132  unsigned32  ecx;
133  unsigned32  eax;
134  unsigned32  idtIndex;
135  unsigned32  faultCode;
136  unsigned32  eip;
137  unsigned32  cs;
138  unsigned32  eflags;
139} CPU_Exception_frame;
140
141typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
142extern cpuExcHandlerType _currentExcHandler;
143extern void rtems_exception_init_mngt();
144
145/*
146 *  The following structure defines the set of information saved
147 *  on the current stack by RTEMS upon receipt of each interrupt
148 *  that will lead to re-enter the kernel to signal the thread.
149 */
150
151typedef CPU_Exception_frame CPU_Interrupt_frame;
152
153typedef enum {
154  DIVIDE_BY_ZERO        =       0,
155  DEBUG                 =       1,
156  NMI                   =       2,
157  BREAKPOINT            =       3,
158  OVERFLOW              =       4,
159  BOUND                 =       5,
160  ILLEGAL_INSTR         =       6,
161  MATH_COPROC_UNAVAIL   =       7,
162  DOUBLE_FAULT          =       8,
163  I386_COPROC_SEG_ERR   =       9,
164  INVALID_TSS           =       10,
165  SEGMENT_NOT_PRESENT   =       11,
166  STACK_SEGMENT_FAULT   =       12,
167  GENERAL_PROT_ERR      =       13,
168  PAGE_FAULT            =       14,
169  INTEL_RES15           =       15,
170  FLOAT_ERROR           =       16,
171  ALIGN_CHECK           =       17,
172  MACHINE_CHECK         =       18
173} Intel_symbolic_exception_name;
174 
175
176/*
177 *  The following table contains the information required to configure
178 *  the i386 specific parameters.
179 */
180
181typedef struct {
182  void       (*pretasking_hook)( void );
183  void       (*predriver_hook)( void );
184  void       (*postdriver_hook)( void );
185  void       (*idle_task)( void );
186  boolean      do_zero_of_workspace;
187  unsigned32   idle_task_stack_size;
188  unsigned32   interrupt_stack_size;
189  unsigned32   extra_mpci_receive_server_stack;
190  void *     (*stack_allocate_hook)( unsigned32 );
191  void       (*stack_free_hook)( void* );
192  /* end of fields required on all CPUs */
193
194  unsigned32   interrupt_table_segment;
195  void        *interrupt_table_offset;
196}   rtems_cpu_table;
197
198/*
199 *  context size area for floating point
200 *
201 *  NOTE:  This is out of place on the i386 to avoid a forward reference.
202 */
203
204#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
205
206/* variables */
207
208SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
209SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
210SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
211
212/* constants */
213
214/*
215 *  This defines the number of levels and the mask used to pick those
216 *  bits out of a thread mode.
217 */
218
219#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
220#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
221
222/*
223 *  extra stack required by the MPCI receive server thread
224 */
225
226#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
227
228/*
229 *  i386 family supports 256 distinct vectors.
230 */
231
232#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
233#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
234
235/*
236 *  Minimum size of a thread's stack.
237 */
238
239#define CPU_STACK_MINIMUM_SIZE          1024
240
241/*
242 *  i386 is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
243 */
244
245#define CPU_ALIGNMENT                    4
246#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
247#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
248
249/*
250 *  On i386 thread stacks require no further alignment after allocation
251 *  from the Workspace.
252 */
253
254#define CPU_STACK_ALIGNMENT             0
255
256/* macros */
257
258/*
259 *  ISR handler macros
260 *
261 *  These macros perform the following functions:
262 *     + disable all maskable CPU interrupts
263 *     + restore previous interrupt level (enable)
264 *     + temporarily restore interrupts (flash)
265 *     + set a particular level
266 */
267
268#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
269
270#define _CPU_ISR_Enable( _level )  i386_enable_interrupts( _level )
271
272#define _CPU_ISR_Flash( _level )   i386_flash_interrupts( _level )
273
274#define _CPU_ISR_Set_level( _new_level ) \
275  { \
276    if ( _new_level ) asm volatile ( "cli" ); \
277    else              asm volatile ( "sti" ); \
278  }
279
280unsigned32 _CPU_ISR_Get_level( void );
281
282/* end of ISR handler macros */
283
284/*
285 *  Context handler macros
286 *
287 *  These macros perform the following functions:
288 *     + initialize a context area
289 *     + restart the current thread
290 *     + calculate the initial pointer into a FP context area
291 *     + initialize an FP context area
292 */
293
294#define CPU_EFLAGS_INTERRUPTS_ON  0x00003202
295#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
296
297#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
298                                   _isr, _entry_point, _is_fp ) \
299  do { \
300    unsigned32 _stack; \
301    \
302    if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \
303    else          (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \
304    \
305    _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \
306    \
307    *((proc_ptr *)(_stack)) = (_entry_point); \
308    (_the_context)->ebp     = (void *) _stack; \
309    (_the_context)->esp     = (void *) _stack; \
310  } while (0)
311
312#define _CPU_Context_Restart_self( _the_context ) \
313   _CPU_Context_restore( (_the_context) );
314
315#define _CPU_Context_Fp_start( _base, _offset ) \
316   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
317
318#define _CPU_Context_Initialize_fp( _fp_area ) \
319  { \
320    unsigned32 *_source      = (unsigned32 *) &_CPU_Null_fp_context; \
321    unsigned32 *_destination = *(_fp_area); \
322    unsigned32  _index; \
323    \
324    for ( _index=0 ; _index < CPU_CONTEXT_FP_SIZE/4 ; _index++ ) \
325      *_destination++ = *_source++; \
326  }
327
328/* end of Context handler macros */
329
330/*
331 *  Fatal Error manager macros
332 *
333 *  These macros perform the following functions:
334 *    + disable interrupts and halt the CPU
335 */
336
337#define _CPU_Fatal_halt( _error ) \
338  { \
339    asm volatile ( "cli ; \
340                    movl %0,%%eax ; \
341                    hlt" \
342                    : "=r" ((_error)) : "0" ((_error)) \
343    ); \
344  }
345
346/* end of Fatal Error manager macros */
347
348/*
349 *  Bitfield handler macros
350 *
351 *  These macros perform the following functions:
352 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
353 */
354
355#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
356#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
357
358#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
359  { \
360    register unsigned16 __value_in_register = (_value); \
361    \
362    _output = 0; \
363    \
364    asm volatile ( "bsfw    %0,%1 " \
365                    : "=r" (__value_in_register), "=r" (_output) \
366                    : "0"  (__value_in_register), "1"  (_output) \
367    ); \
368  }
369
370/* end of Bitfield handler macros */
371
372/*
373 *  Priority handler macros
374 *
375 *  These macros perform the following functions:
376 *    + return a mask with the bit for this major/minor portion of
377 *      of thread priority set.
378 *    + translate the bit number returned by "Bitfield_find_first_bit"
379 *      into an index into the thread ready chain bit maps
380 */
381
382#define _CPU_Priority_Mask( _bit_number ) \
383  ( 1 << (_bit_number) )
384
385#define _CPU_Priority_bits_index( _priority ) \
386  (_priority)
387
388/* functions */
389
390/*
391 *  _CPU_Initialize
392 *
393 *  This routine performs CPU dependent initialization.
394 */
395
396void _CPU_Initialize(
397  rtems_cpu_table  *cpu_table,
398  void      (*thread_dispatch)
399);
400
401/*
402 *  _CPU_ISR_install_raw_handler
403 *
404 *  This routine installs a "raw" interrupt handler directly into the
405 *  processor's vector table.
406 */
407 
408void _CPU_ISR_install_raw_handler(
409  unsigned32  vector,
410  proc_ptr    new_handler,
411  proc_ptr   *old_handler
412);
413
414/*
415 *  _CPU_ISR_install_vector
416 *
417 *  This routine installs an interrupt vector.
418 */
419
420void _CPU_ISR_install_vector(
421  unsigned32  vector,
422  proc_ptr    new_handler,
423  proc_ptr   *old_handler
424);
425
426/*
427 *  _CPU_Thread_Idle_body
428 *
429 *  Use the halt instruction of low power mode of a particular i386 model.
430 */
431
432#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
433
434void _CPU_Thread_Idle_body( void );
435
436#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
437
438/*
439 *  _CPU_Context_switch
440 *
441 *  This routine switches from the run context to the heir context.
442 */
443
444void _CPU_Context_switch(
445  Context_Control  *run,
446  Context_Control  *heir
447);
448
449/*
450 *  _CPU_Context_restore
451 *
452 *  This routine is generally used only to restart self in an
453 *  efficient manner and avoid stack conflicts.
454 */
455
456void _CPU_Context_restore(
457  Context_Control *new_context
458);
459
460/*
461 *  _CPU_Context_save_fp
462 *
463 *  This routine saves the floating point context passed to it.
464 */
465
466void _CPU_Context_save_fp(
467  void **fp_context_ptr
468);
469
470/*
471 *  _CPU_Context_restore_fp
472 *
473 *  This routine restores the floating point context passed to it.
474 */
475
476void _CPU_Context_restore_fp(
477  void **fp_context_ptr
478);
479
480#ifdef __cplusplus
481}
482#endif
483
484#endif
485/* end of include file */
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