1 | /* cpu.h |
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2 | * |
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3 | * This include file contains information pertaining to the Intel |
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4 | * i386 processor. |
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5 | * |
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6 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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7 | * On-Line Applications Research Corporation (OAR). |
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8 | * All rights assigned to U.S. Government, 1994. |
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9 | * |
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10 | * This material may be reproduced by or for the U.S. Government pursuant |
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11 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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12 | * notice must appear in all copies of this file and its derivatives. |
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13 | * |
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14 | * $Id$ |
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15 | */ |
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16 | |
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17 | #ifndef __CPU_h |
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18 | #define __CPU_h |
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19 | |
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20 | #ifdef __cplusplus |
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21 | extern "C" { |
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22 | #endif |
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23 | |
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24 | #ifndef ASM |
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25 | #include <rtems/score/i386types.h> |
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26 | #endif |
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27 | #include <rtems/score/i386.h> |
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28 | |
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29 | /* conditional compilation parameters */ |
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30 | |
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31 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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32 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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33 | |
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34 | /* |
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35 | * i386 has an RTEMS allocated and managed interrupt stack. |
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36 | */ |
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37 | |
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38 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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39 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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40 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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41 | |
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42 | /* |
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43 | * Some family members have no FP, some have an FPU such as the i387 |
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44 | * for the i386, others have it built in (i486DX, Pentium). |
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45 | */ |
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46 | |
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47 | #if ( I386_HAS_FPU == 1 ) |
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48 | #define CPU_HARDWARE_FP TRUE /* i387 for i386 */ |
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49 | #else |
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50 | #define CPU_HARDWARE_FP FALSE |
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51 | #endif |
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52 | |
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53 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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54 | #define CPU_IDLE_TASK_IS_FP FALSE |
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55 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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56 | |
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57 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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58 | #define CPU_STACK_GROWS_UP FALSE |
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59 | #define CPU_STRUCTURE_ALIGNMENT |
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60 | |
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61 | /* structures */ |
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62 | |
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63 | /* |
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64 | * Basic integer context for the i386 family. |
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65 | */ |
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66 | |
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67 | typedef struct { |
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68 | unsigned32 eflags; /* extended flags register */ |
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69 | void *esp; /* extended stack pointer register */ |
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70 | void *ebp; /* extended base pointer register */ |
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71 | unsigned32 ebx; /* extended bx register */ |
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72 | unsigned32 esi; /* extended source index register */ |
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73 | unsigned32 edi; /* extended destination index flags register */ |
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74 | } Context_Control; |
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75 | |
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76 | /* |
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77 | * FP context save area for the i387 numeric coprocessors. |
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78 | */ |
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79 | |
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80 | typedef struct { |
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81 | unsigned8 fp_save_area[108]; /* context size area for I80387 */ |
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82 | /* 28 bytes for environment */ |
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83 | } Context_Control_fp; |
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84 | |
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85 | /* |
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86 | * The following structure defines the set of information saved |
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87 | * on the current stack by RTEMS upon receipt of each interrupt. |
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88 | */ |
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89 | |
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90 | typedef struct { |
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91 | unsigned32 TBD; /* XXX Fix for this CPU */ |
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92 | } CPU_Interrupt_frame; |
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93 | |
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94 | /* |
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95 | * The following table contains the information required to configure |
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96 | * the i386 specific parameters. |
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97 | */ |
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98 | |
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99 | typedef struct { |
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100 | void (*pretasking_hook)( void ); |
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101 | void (*predriver_hook)( void ); |
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102 | void (*postdriver_hook)( void ); |
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103 | void (*idle_task)( void ); |
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104 | boolean do_zero_of_workspace; |
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105 | unsigned32 interrupt_stack_size; |
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106 | unsigned32 extra_mpci_receive_server_stack; |
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107 | void * (*stack_allocate_hook)( unsigned32 ); |
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108 | void (*stack_free_hook)( void* ); |
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109 | /* end of fields required on all CPUs */ |
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110 | |
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111 | unsigned32 interrupt_table_segment; |
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112 | void *interrupt_table_offset; |
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113 | } rtems_cpu_table; |
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114 | |
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115 | /* |
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116 | * context size area for floating point |
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117 | * |
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118 | * NOTE: This is out of place on the i386 to avoid a forward reference. |
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119 | */ |
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120 | |
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121 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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122 | |
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123 | /* variables */ |
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124 | |
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125 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
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126 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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127 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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128 | |
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129 | /* constants */ |
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130 | |
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131 | /* |
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132 | * This defines the number of levels and the mask used to pick those |
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133 | * bits out of a thread mode. |
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134 | */ |
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135 | |
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136 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
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137 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
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138 | |
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139 | /* |
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140 | * extra stack required by the MPCI receive server thread |
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141 | */ |
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142 | |
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143 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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144 | |
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145 | /* |
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146 | * i386 family supports 256 distinct vectors. |
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147 | */ |
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148 | |
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149 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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150 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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151 | |
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152 | /* |
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153 | * Minimum size of a thread's stack. |
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154 | */ |
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155 | |
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156 | #define CPU_STACK_MINIMUM_SIZE 1024 |
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157 | |
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158 | /* |
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159 | * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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160 | */ |
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161 | |
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162 | #define CPU_ALIGNMENT 4 |
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163 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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164 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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165 | |
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166 | /* |
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167 | * On i386 thread stacks require no further alignment after allocation |
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168 | * from the Workspace. |
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169 | */ |
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170 | |
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171 | #define CPU_STACK_ALIGNMENT 0 |
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172 | |
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173 | /* macros */ |
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174 | |
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175 | /* |
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176 | * ISR handler macros |
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177 | * |
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178 | * These macros perform the following functions: |
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179 | * + disable all maskable CPU interrupts |
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180 | * + restore previous interrupt level (enable) |
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181 | * + temporarily restore interrupts (flash) |
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182 | * + set a particular level |
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183 | */ |
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184 | |
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185 | #define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) |
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186 | |
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187 | #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) |
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188 | |
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189 | #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) |
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190 | |
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191 | #define _CPU_ISR_Set_level( _new_level ) \ |
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192 | { \ |
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193 | if ( _new_level ) asm volatile ( "cli" ); \ |
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194 | else asm volatile ( "sti" ); \ |
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195 | } |
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196 | |
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197 | unsigned32 _CPU_ISR_Get_level( void ); |
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198 | |
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199 | /* end of ISR handler macros */ |
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200 | |
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201 | /* |
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202 | * Context handler macros |
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203 | * |
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204 | * These macros perform the following functions: |
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205 | * + initialize a context area |
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206 | * + restart the current thread |
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207 | * + calculate the initial pointer into a FP context area |
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208 | * + initialize an FP context area |
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209 | */ |
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210 | |
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211 | #define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 |
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212 | #define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 |
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213 | |
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214 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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215 | _isr, _entry_point, _is_fp ) \ |
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216 | do { \ |
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217 | unsigned32 _stack; \ |
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218 | \ |
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219 | if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \ |
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220 | else (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \ |
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221 | \ |
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222 | _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \ |
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223 | \ |
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224 | *((proc_ptr *)(_stack)) = (_entry_point); \ |
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225 | (_the_context)->ebp = (void *) _stack; \ |
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226 | (_the_context)->esp = (void *) _stack; \ |
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227 | } while (0) |
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228 | |
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229 | #define _CPU_Context_Restart_self( _the_context ) \ |
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230 | _CPU_Context_restore( (_the_context) ); |
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231 | |
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232 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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233 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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234 | |
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235 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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236 | { \ |
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237 | unsigned32 *_source = (unsigned32 *) &_CPU_Null_fp_context; \ |
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238 | unsigned32 *_destination = *(_fp_area); \ |
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239 | unsigned32 _index; \ |
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240 | \ |
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241 | for ( _index=0 ; _index < CPU_CONTEXT_FP_SIZE/4 ; _index++ ) \ |
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242 | *_destination++ = *_source++; \ |
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243 | } |
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244 | |
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245 | /* end of Context handler macros */ |
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246 | |
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247 | /* |
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248 | * Fatal Error manager macros |
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249 | * |
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250 | * These macros perform the following functions: |
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251 | * + disable interrupts and halt the CPU |
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252 | */ |
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253 | |
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254 | #define _CPU_Fatal_halt( _error ) \ |
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255 | { \ |
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256 | asm volatile ( "cli ; \ |
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257 | movl %0,%%eax ; \ |
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258 | hlt" \ |
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259 | : "=r" ((_error)) : "0" ((_error)) \ |
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260 | ); \ |
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261 | } |
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262 | |
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263 | /* end of Fatal Error manager macros */ |
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264 | |
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265 | /* |
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266 | * Bitfield handler macros |
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267 | * |
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268 | * These macros perform the following functions: |
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269 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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270 | */ |
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271 | |
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272 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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273 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
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274 | |
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275 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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276 | { \ |
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277 | register unsigned16 __value_in_register = (_value); \ |
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278 | \ |
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279 | _output = 0; \ |
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280 | \ |
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281 | asm volatile ( "bsfw %0,%1 " \ |
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282 | : "=r" (__value_in_register), "=r" (_output) \ |
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283 | : "0" (__value_in_register), "1" (_output) \ |
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284 | ); \ |
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285 | } |
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286 | |
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287 | /* end of Bitfield handler macros */ |
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288 | |
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289 | /* |
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290 | * Priority handler macros |
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291 | * |
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292 | * These macros perform the following functions: |
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293 | * + return a mask with the bit for this major/minor portion of |
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294 | * of thread priority set. |
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295 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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296 | * into an index into the thread ready chain bit maps |
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297 | */ |
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298 | |
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299 | #define _CPU_Priority_Mask( _bit_number ) \ |
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300 | ( 1 << (_bit_number) ) |
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301 | |
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302 | #define _CPU_Priority_bits_index( _priority ) \ |
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303 | (_priority) |
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304 | |
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305 | /* functions */ |
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306 | |
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307 | /* |
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308 | * _CPU_Initialize |
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309 | * |
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310 | * This routine performs CPU dependent initialization. |
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311 | */ |
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312 | |
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313 | void _CPU_Initialize( |
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314 | rtems_cpu_table *cpu_table, |
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315 | void (*thread_dispatch) |
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316 | ); |
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317 | |
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318 | /* |
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319 | * _CPU_ISR_install_raw_handler |
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320 | * |
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321 | * This routine installs a "raw" interrupt handler directly into the |
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322 | * processor's vector table. |
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323 | */ |
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324 | |
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325 | void _CPU_ISR_install_raw_handler( |
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326 | unsigned32 vector, |
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327 | proc_ptr new_handler, |
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328 | proc_ptr *old_handler |
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329 | ); |
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330 | |
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331 | /* |
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332 | * _CPU_ISR_install_vector |
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333 | * |
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334 | * This routine installs an interrupt vector. |
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335 | */ |
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336 | |
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337 | void _CPU_ISR_install_vector( |
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338 | unsigned32 vector, |
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339 | proc_ptr new_handler, |
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340 | proc_ptr *old_handler |
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341 | ); |
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342 | |
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343 | /* |
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344 | * _CPU_Context_switch |
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345 | * |
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346 | * This routine switches from the run context to the heir context. |
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347 | */ |
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348 | |
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349 | void _CPU_Context_switch( |
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350 | Context_Control *run, |
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351 | Context_Control *heir |
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352 | ); |
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353 | |
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354 | /* |
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355 | * _CPU_Context_restore |
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356 | * |
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357 | * This routine is generallu used only to restart self in an |
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358 | * efficient manner and avoid stack conflicts. |
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359 | */ |
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360 | |
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361 | void _CPU_Context_restore( |
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362 | Context_Control *new_context |
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363 | ); |
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364 | |
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365 | /* |
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366 | * _CPU_Context_save_fp |
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367 | * |
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368 | * This routine saves the floating point context passed to it. |
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369 | */ |
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370 | |
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371 | void _CPU_Context_save_fp( |
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372 | void **fp_context_ptr |
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373 | ); |
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374 | |
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375 | /* |
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376 | * _CPU_Context_restore_fp |
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377 | * |
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378 | * This routine restores the floating point context passed to it. |
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379 | */ |
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380 | |
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381 | void _CPU_Context_restore_fp( |
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382 | void **fp_context_ptr |
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383 | ); |
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384 | |
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385 | #ifdef __cplusplus |
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386 | } |
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387 | #endif |
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388 | |
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389 | #endif |
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390 | /* end of include file */ |
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