source: rtems/c/src/exec/score/cpu/i386/cpu.h @ 95a1d50

4.104.114.84.95
Last change on this file since 95a1d50 was 95a1d50, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 29, 1997 at 12:08:14 AM

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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i386 processor.
5 *
6 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
7 *  On-Line Applications Research Corporation (OAR).
8 *  All rights assigned to U.S. Government, 1994.
9 *
10 *  This material may be reproduced by or for the U.S. Government pursuant
11 *  to the copyright license under the clause at DFARS 252.227-7013.  This
12 *  notice must appear in all copies of this file and its derivatives.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/i386.h>              /* pick up machine definitions */
25#ifndef ASM
26#include <rtems/score/i386types.h>
27#endif
28
29/* conditional compilation parameters */
30
31#define CPU_INLINE_ENABLE_DISPATCH       TRUE
32#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
33
34/*
35 *  i386 has an RTEMS allocated and managed interrupt stack.
36 */
37
38#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
39#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
40#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
41
42/*
43 *  Some family members have no FP, some have an FPU such as the i387
44 *  for the i386, others have it built in (i486DX, Pentium).
45 */
46
47#if ( I386_HAS_FPU == 1 )
48#define CPU_HARDWARE_FP     TRUE    /* i387 for i386 */
49#else
50#define CPU_HARDWARE_FP     FALSE
51#endif
52
53#define CPU_ALL_TASKS_ARE_FP             FALSE
54#define CPU_IDLE_TASK_IS_FP              FALSE
55#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
56
57#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
58#define CPU_STACK_GROWS_UP               FALSE
59#define CPU_STRUCTURE_ALIGNMENT
60
61/* structures */
62
63/*
64 *  Basic integer context for the i386 family.
65 */
66
67typedef struct {
68  unsigned32  eflags;   /* extended flags register                   */
69  void       *esp;      /* extended stack pointer register           */
70  void       *ebp;      /* extended base pointer register            */
71  unsigned32  ebx;      /* extended bx register                      */
72  unsigned32  esi;      /* extended source index register            */
73  unsigned32  edi;      /* extended destination index flags register */
74}   Context_Control;
75
76/*
77 *  FP context save area for the i387 numeric coprocessors.
78 */
79
80typedef struct {
81  unsigned8   fp_save_area[108];    /* context size area for I80387 */
82                                    /*  28 bytes for environment    */
83} Context_Control_fp;
84
85/*
86 *  The following structure defines the set of information saved
87 *  on the current stack by RTEMS upon receipt of each interrupt.
88 */
89
90typedef struct {
91  unsigned32   TBD;   /* XXX Fix for this CPU */
92} CPU_Interrupt_frame;
93
94/*
95 *  The following table contains the information required to configure
96 *  the i386 specific parameters.
97 */
98
99typedef struct {
100  void       (*pretasking_hook)( void );
101  void       (*predriver_hook)( void );
102  void       (*postdriver_hook)( void );
103  void       (*idle_task)( void );
104  boolean      do_zero_of_workspace;
105  unsigned32   interrupt_stack_size;
106  unsigned32   extra_mpci_receive_server_stack;
107  void *     (*stack_allocate_hook)( unsigned32 );
108  void       (*stack_free_hook)( void* );
109  /* end of fields required on all CPUs */
110
111  unsigned32   interrupt_table_segment;
112  void        *interrupt_table_offset;
113}   rtems_cpu_table;
114
115/*
116 *  context size area for floating point
117 *
118 *  NOTE:  This is out of place on the i386 to avoid a forward reference.
119 */
120
121#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
122
123/* variables */
124
125SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
126SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
127SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
128
129/* constants */
130
131/*
132 *  This defines the number of levels and the mask used to pick those
133 *  bits out of a thread mode.
134 */
135
136#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
137#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
138
139/*
140 *  extra stack required by the MPCI receive server thread
141 */
142
143#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
144
145/*
146 *  i386 family supports 256 distinct vectors.
147 */
148
149#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
150#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
151
152/*
153 *  Minimum size of a thread's stack.
154 */
155
156#define CPU_STACK_MINIMUM_SIZE          1024
157
158/*
159 *  i386 is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
160 */
161
162#define CPU_ALIGNMENT                    4
163#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
164#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
165
166/*
167 *  On i386 thread stacks require no further alignment after allocation
168 *  from the Workspace.
169 */
170
171#define CPU_STACK_ALIGNMENT             0
172
173/* macros */
174
175/*
176 *  ISR handler macros
177 *
178 *  These macros perform the following functions:
179 *     + disable all maskable CPU interrupts
180 *     + restore previous interrupt level (enable)
181 *     + temporarily restore interrupts (flash)
182 *     + set a particular level
183 */
184
185#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
186
187#define _CPU_ISR_Enable( _level )  i386_enable_interrupts( _level )
188
189#define _CPU_ISR_Flash( _level )   i386_flash_interrupts( _level )
190
191#define _CPU_ISR_Set_level( _new_level ) \
192  { \
193    if ( _new_level ) asm volatile ( "cli" ); \
194    else              asm volatile ( "sti" ); \
195  }
196
197unsigned32 _CPU_ISR_Get_level( void );
198
199/* end of ISR handler macros */
200
201/*
202 *  Context handler macros
203 *
204 *  These macros perform the following functions:
205 *     + initialize a context area
206 *     + restart the current thread
207 *     + calculate the initial pointer into a FP context area
208 *     + initialize an FP context area
209 */
210
211#define CPU_EFLAGS_INTERRUPTS_ON  0x00003202
212#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
213
214#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
215                                   _isr, _entry_point, _is_fp ) \
216  do { \
217    unsigned32 _stack; \
218    \
219    if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \
220    else          (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \
221    \
222    _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \
223    \
224    *((proc_ptr *)(_stack)) = (_entry_point); \
225    (_the_context)->ebp     = (void *) _stack; \
226    (_the_context)->esp     = (void *) _stack; \
227  } while (0)
228
229#define _CPU_Context_Restart_self( _the_context ) \
230   _CPU_Context_restore( (_the_context) );
231
232#define _CPU_Context_Fp_start( _base, _offset ) \
233   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
234
235#define _CPU_Context_Initialize_fp( _fp_area ) \
236  { \
237    unsigned32 *_source      = (unsigned32 *) &_CPU_Null_fp_context; \
238    unsigned32 *_destination = *(_fp_area); \
239    unsigned32  _index; \
240    \
241    for ( _index=0 ; _index < CPU_CONTEXT_FP_SIZE/4 ; _index++ ) \
242      *_destination++ = *_source++; \
243  }
244
245/* end of Context handler macros */
246
247/*
248 *  Fatal Error manager macros
249 *
250 *  These macros perform the following functions:
251 *    + disable interrupts and halt the CPU
252 */
253
254#define _CPU_Fatal_halt( _error ) \
255  { \
256    asm volatile ( "cli ; \
257                    movl %0,%%eax ; \
258                    hlt" \
259                    : "=r" ((_error)) : "0" ((_error)) \
260    ); \
261  }
262
263/* end of Fatal Error manager macros */
264
265/*
266 *  Bitfield handler macros
267 *
268 *  These macros perform the following functions:
269 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
270 */
271
272#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
273#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
274
275#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
276  { \
277    register unsigned16 __value_in_register = (_value); \
278    \
279    _output = 0; \
280    \
281    asm volatile ( "bsfw    %0,%1 " \
282                    : "=r" (__value_in_register), "=r" (_output) \
283                    : "0"  (__value_in_register), "1"  (_output) \
284    ); \
285  }
286
287/* end of Bitfield handler macros */
288
289/*
290 *  Priority handler macros
291 *
292 *  These macros perform the following functions:
293 *    + return a mask with the bit for this major/minor portion of
294 *      of thread priority set.
295 *    + translate the bit number returned by "Bitfield_find_first_bit"
296 *      into an index into the thread ready chain bit maps
297 */
298
299#define _CPU_Priority_Mask( _bit_number ) \
300  ( 1 << (_bit_number) )
301
302#define _CPU_Priority_bits_index( _priority ) \
303  (_priority)
304
305/* functions */
306
307/*
308 *  _CPU_Initialize
309 *
310 *  This routine performs CPU dependent initialization.
311 */
312
313void _CPU_Initialize(
314  rtems_cpu_table  *cpu_table,
315  void      (*thread_dispatch)
316);
317
318/*
319 *  _CPU_ISR_install_raw_handler
320 *
321 *  This routine installs a "raw" interrupt handler directly into the
322 *  processor's vector table.
323 */
324 
325void _CPU_ISR_install_raw_handler(
326  unsigned32  vector,
327  proc_ptr    new_handler,
328  proc_ptr   *old_handler
329);
330
331/*
332 *  _CPU_ISR_install_vector
333 *
334 *  This routine installs an interrupt vector.
335 */
336
337void _CPU_ISR_install_vector(
338  unsigned32  vector,
339  proc_ptr    new_handler,
340  proc_ptr   *old_handler
341);
342
343/*
344 *  _CPU_Context_switch
345 *
346 *  This routine switches from the run context to the heir context.
347 */
348
349void _CPU_Context_switch(
350  Context_Control  *run,
351  Context_Control  *heir
352);
353
354/*
355 *  _CPU_Context_restore
356 *
357 *  This routine is generallu used only to restart self in an
358 *  efficient manner and avoid stack conflicts.
359 */
360
361void _CPU_Context_restore(
362  Context_Control *new_context
363);
364
365/*
366 *  _CPU_Context_save_fp
367 *
368 *  This routine saves the floating point context passed to it.
369 */
370
371void _CPU_Context_save_fp(
372  void **fp_context_ptr
373);
374
375/*
376 *  _CPU_Context_restore_fp
377 *
378 *  This routine restores the floating point context passed to it.
379 */
380
381void _CPU_Context_restore_fp(
382  void **fp_context_ptr
383);
384
385#ifdef __cplusplus
386}
387#endif
388
389#endif
390/* end of include file */
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