source: rtems/c/src/exec/score/cpu/i386/cpu.h @ 4721cf1

4.104.114.84.95
Last change on this file since 4721cf1 was 4721cf1, checked in by Joel Sherrill <joel.sherrill@…>, on 12/03/98 at 23:54:14

Patch from Emmanuel Raguet <raguet@…> to add remote debug server
and RPC support to RTEMS. Thanks. :) Email follows:

Hello,

For Xmas, here is the Remote Debugger on RTEMS !

Here are 2 patches for the Remote Debugger on RTEMS for pc386 from Linux
host :

  • one for RTEMS it self,
  • one for GDB-4.17.

1/ RTEMS patch
--------------

This patch adds 2 libraries :

  • a simplified SUN RPC library
  • the Remote Debugger library

The configuration command is the following :
../rtems4/configure --target=i386-rtemself --enable-rtemsbsp=pc386
--enable-rdbg

The SUN RPC library is built only if networking is set.
The RDBG library is built if networking and enable-rdbg are set.

The function used to initialize the debugger is :

rtems_rdbg_initialize ();

A special function has been created to force a task to be
in a "debug" state : enterRdbg().
The use of this function is not mandatory.

2/ GDB-4.17 patch
-----------------

This patch create a new RTEMS target for GDB-4.17.

The configuration command is the following :
./configure --enable-shared --target=i386RTEMS

To connect to a target, use :

target rtems [your_site_address]

Then, attach the target using : attach 1

And... Debug ;)

You can obtain the original GDB-4.17 on
ftp://ftp.debian.org/debian/dists/stable/main/source/devel/gdb_4.17.orig.tar.gz

This has been tested from a Debian 2.0.1 linux host.

  • Property mode set to 100644
File size: 12.1 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Intel
4 *  i386 processor.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 */
16
17#ifndef __CPU_h
18#define __CPU_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/i386.h>              /* pick up machine definitions */
25#include <libcpu/cpu.h>
26
27#ifndef ASM
28#include <rtems/score/i386types.h>
29#endif
30
31/* conditional compilation parameters */
32
33#define CPU_INLINE_ENABLE_DISPATCH       TRUE
34#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
35
36/*
37 *  i386 has an RTEMS allocated and managed interrupt stack.
38 */
39
40#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
41#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
42#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
43
44/*
45 *  Does the RTEMS invoke the user's ISR with the vector number and
46 *  a pointer to the saved interrupt frame (1) or just the vector
47 *  number (0)?
48 */
49
50#define CPU_ISR_PASSES_FRAME_POINTER 0
51
52/*
53 *  Some family members have no FP, some have an FPU such as the i387
54 *  for the i386, others have it built in (i486DX, Pentium).
55 */
56
57#if ( I386_HAS_FPU == 1 )
58#define CPU_HARDWARE_FP     TRUE    /* i387 for i386 */
59#else
60#define CPU_HARDWARE_FP     FALSE
61#endif
62
63#define CPU_ALL_TASKS_ARE_FP             FALSE
64#define CPU_IDLE_TASK_IS_FP              FALSE
65#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
66
67#define CPU_STACK_GROWS_UP               FALSE
68#define CPU_STRUCTURE_ALIGNMENT
69
70/*
71 *  Does this port provide a CPU dependent IDLE task implementation?
72 * 
73 *  If TRUE, then the routine _CPU_Thread_Idle_body
74 *  must be provided and is the default IDLE thread body instead of
75 *  _CPU_Thread_Idle_body.
76 *
77 *  If FALSE, then use the generic IDLE thread body if the BSP does
78 *  not provide one.
79 */
80 
81#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
82
83/*
84 *  Define what is required to specify how the network to host conversion
85 *  routines are handled.
86 */
87
88#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
89#define CPU_BIG_ENDIAN                           FALSE
90#define CPU_LITTLE_ENDIAN                        TRUE
91
92/* structures */
93
94/*
95 *  Basic integer context for the i386 family.
96 */
97
98typedef struct {
99  unsigned32  eflags;   /* extended flags register                   */
100  void       *esp;      /* extended stack pointer register           */
101  void       *ebp;      /* extended base pointer register            */
102  unsigned32  ebx;      /* extended bx register                      */
103  unsigned32  esi;      /* extended source index register            */
104  unsigned32  edi;      /* extended destination index flags register */
105}   Context_Control;
106
107/*
108 *  FP context save area for the i387 numeric coprocessors.
109 */
110
111typedef struct {
112  unsigned8   fp_save_area[108];    /* context size area for I80387 */
113                                    /*  28 bytes for environment    */
114} Context_Control_fp;
115
116
117/*
118 *  The following structure defines the set of information saved
119 *  on the current stack by RTEMS upon receipt of execptions.
120 *
121 * idtIndex is either the interrupt number or the trap/exception number.
122 * faultCode is the code pushed by the processor on some exceptions.
123 */
124
125typedef struct {
126  unsigned32  edi;
127  unsigned32  esi;
128  unsigned32  ebp;
129  unsigned32  esp0;
130  unsigned32  ebx;
131  unsigned32  edx;
132  unsigned32  ecx;
133  unsigned32  eax;
134  unsigned32  idtIndex;
135  unsigned32  faultCode;
136  unsigned32  eip;
137  unsigned32  cs;
138  unsigned32  eflags;
139} CPU_Exception_frame;
140
141typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
142extern cpuExcHandlerType _currentExcHandler;
143extern void rtems_exception_init_mngt();
144
145/*
146 *  The following structure defines the set of information saved
147 *  on the current stack by RTEMS upon receipt of each interrupt
148 *  that will lead to re-enter the kernel to signal the thread.
149 */
150
151typedef CPU_Exception_frame CPU_Interrupt_frame;
152
153typedef enum {
154  I386_EXCEPTION_DIVIDE_BY_ZERO      = 0,
155  I386_EXCEPTION_DEBUG               = 1,
156  I386_EXCEPTION_NMI                 = 2,
157  I386_EXCEPTION_BREAKPOINT          = 3,
158  I386_EXCEPTION_OVERFLOW            = 4,
159  I386_EXCEPTION_BOUND               = 5,
160  I386_EXCEPTION_ILLEGAL_INSTR       = 6,
161  I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7,
162  I386_EXCEPTION_DOUBLE_FAULT        = 8,
163  I386_EXCEPTION_I386_COPROC_SEG_ERR = 9,
164  I386_EXCEPTION_INVALID_TSS         = 10,
165  I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11,
166  I386_EXCEPTION_STACK_SEGMENT_FAULT = 12,
167  I386_EXCEPTION_GENERAL_PROT_ERR    = 13,
168  I386_EXCEPTION_PAGE_FAULT          = 14,
169  I386_EXCEPTION_INTEL_RES15         = 15,
170  I386_EXCEPTION_FLOAT_ERROR         = 16,
171  I386_EXCEPTION_ALIGN_CHECK         = 17,
172  I386_EXCEPTION_MACHINE_CHECK       = 18,
173  I386_EXCEPTION_ENTER_RDBG          = 50     /* to enter manually RDBG */
174
175} Intel_symbolic_exception_name;
176 
177
178/*
179 *  The following table contains the information required to configure
180 *  the i386 specific parameters.
181 */
182
183typedef struct {
184  void       (*pretasking_hook)( void );
185  void       (*predriver_hook)( void );
186  void       (*postdriver_hook)( void );
187  void       (*idle_task)( void );
188  boolean      do_zero_of_workspace;
189  unsigned32   idle_task_stack_size;
190  unsigned32   interrupt_stack_size;
191  unsigned32   extra_mpci_receive_server_stack;
192  void *     (*stack_allocate_hook)( unsigned32 );
193  void       (*stack_free_hook)( void* );
194  /* end of fields required on all CPUs */
195
196  unsigned32   interrupt_table_segment;
197  void        *interrupt_table_offset;
198}   rtems_cpu_table;
199
200/*
201 *  context size area for floating point
202 *
203 *  NOTE:  This is out of place on the i386 to avoid a forward reference.
204 */
205
206#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
207
208/* variables */
209
210SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
211SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
212SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
213
214/* constants */
215
216/*
217 *  This defines the number of levels and the mask used to pick those
218 *  bits out of a thread mode.
219 */
220
221#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
222#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
223
224/*
225 *  extra stack required by the MPCI receive server thread
226 */
227
228#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
229
230/*
231 *  i386 family supports 256 distinct vectors.
232 */
233
234#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
235#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
236
237/*
238 *  Minimum size of a thread's stack.
239 */
240
241#define CPU_STACK_MINIMUM_SIZE          1024
242
243/*
244 *  i386 is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
245 */
246
247#define CPU_ALIGNMENT                    4
248#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
249#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
250
251/*
252 *  On i386 thread stacks require no further alignment after allocation
253 *  from the Workspace.
254 */
255
256#define CPU_STACK_ALIGNMENT             0
257
258/* macros */
259
260/*
261 *  ISR handler macros
262 *
263 *  These macros perform the following functions:
264 *     + disable all maskable CPU interrupts
265 *     + restore previous interrupt level (enable)
266 *     + temporarily restore interrupts (flash)
267 *     + set a particular level
268 */
269
270#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
271
272#define _CPU_ISR_Enable( _level )  i386_enable_interrupts( _level )
273
274#define _CPU_ISR_Flash( _level )   i386_flash_interrupts( _level )
275
276#define _CPU_ISR_Set_level( _new_level ) \
277  { \
278    if ( _new_level ) asm volatile ( "cli" ); \
279    else              asm volatile ( "sti" ); \
280  }
281
282unsigned32 _CPU_ISR_Get_level( void );
283
284/* end of ISR handler macros */
285
286/*
287 *  Context handler macros
288 *
289 *  These macros perform the following functions:
290 *     + initialize a context area
291 *     + restart the current thread
292 *     + calculate the initial pointer into a FP context area
293 *     + initialize an FP context area
294 */
295
296#define CPU_EFLAGS_INTERRUPTS_ON  0x00003202
297#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
298
299#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
300                                   _isr, _entry_point, _is_fp ) \
301  do { \
302    unsigned32 _stack; \
303    \
304    if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \
305    else          (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \
306    \
307    _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \
308    \
309    *((proc_ptr *)(_stack)) = (_entry_point); \
310    (_the_context)->ebp     = (void *) _stack; \
311    (_the_context)->esp     = (void *) _stack; \
312  } while (0)
313
314#define _CPU_Context_Restart_self( _the_context ) \
315   _CPU_Context_restore( (_the_context) );
316
317#define _CPU_Context_Fp_start( _base, _offset ) \
318   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
319
320#define _CPU_Context_Initialize_fp( _fp_area ) \
321  { \
322    unsigned32 *_source      = (unsigned32 *) &_CPU_Null_fp_context; \
323    unsigned32 *_destination = *(_fp_area); \
324    unsigned32  _index; \
325    \
326    for ( _index=0 ; _index < CPU_CONTEXT_FP_SIZE/4 ; _index++ ) \
327      *_destination++ = *_source++; \
328  }
329
330/* end of Context handler macros */
331
332/*
333 *  Fatal Error manager macros
334 *
335 *  These macros perform the following functions:
336 *    + disable interrupts and halt the CPU
337 */
338
339#define _CPU_Fatal_halt( _error ) \
340  { \
341    asm volatile ( "cli ; \
342                    movl %0,%%eax ; \
343                    hlt" \
344                    : "=r" ((_error)) : "0" ((_error)) \
345    ); \
346  }
347
348/* end of Fatal Error manager macros */
349
350/*
351 *  Bitfield handler macros
352 *
353 *  These macros perform the following functions:
354 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
355 */
356
357#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
358#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
359
360#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
361  { \
362    register unsigned16 __value_in_register = (_value); \
363    \
364    _output = 0; \
365    \
366    asm volatile ( "bsfw    %0,%1 " \
367                    : "=r" (__value_in_register), "=r" (_output) \
368                    : "0"  (__value_in_register), "1"  (_output) \
369    ); \
370  }
371
372/* end of Bitfield handler macros */
373
374/*
375 *  Priority handler macros
376 *
377 *  These macros perform the following functions:
378 *    + return a mask with the bit for this major/minor portion of
379 *      of thread priority set.
380 *    + translate the bit number returned by "Bitfield_find_first_bit"
381 *      into an index into the thread ready chain bit maps
382 */
383
384#define _CPU_Priority_Mask( _bit_number ) \
385  ( 1 << (_bit_number) )
386
387#define _CPU_Priority_bits_index( _priority ) \
388  (_priority)
389
390/* functions */
391
392/*
393 *  _CPU_Initialize
394 *
395 *  This routine performs CPU dependent initialization.
396 */
397
398void _CPU_Initialize(
399  rtems_cpu_table  *cpu_table,
400  void      (*thread_dispatch)
401);
402
403/*
404 *  _CPU_ISR_install_raw_handler
405 *
406 *  This routine installs a "raw" interrupt handler directly into the
407 *  processor's vector table.
408 */
409 
410void _CPU_ISR_install_raw_handler(
411  unsigned32  vector,
412  proc_ptr    new_handler,
413  proc_ptr   *old_handler
414);
415
416/*
417 *  _CPU_ISR_install_vector
418 *
419 *  This routine installs an interrupt vector.
420 */
421
422void _CPU_ISR_install_vector(
423  unsigned32  vector,
424  proc_ptr    new_handler,
425  proc_ptr   *old_handler
426);
427
428/*
429 *  _CPU_Thread_Idle_body
430 *
431 *  Use the halt instruction of low power mode of a particular i386 model.
432 */
433
434#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
435
436void _CPU_Thread_Idle_body( void );
437
438#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
439
440/*
441 *  _CPU_Context_switch
442 *
443 *  This routine switches from the run context to the heir context.
444 */
445
446void _CPU_Context_switch(
447  Context_Control  *run,
448  Context_Control  *heir
449);
450
451/*
452 *  _CPU_Context_restore
453 *
454 *  This routine is generally used only to restart self in an
455 *  efficient manner and avoid stack conflicts.
456 */
457
458void _CPU_Context_restore(
459  Context_Control *new_context
460);
461
462/*
463 *  _CPU_Context_save_fp
464 *
465 *  This routine saves the floating point context passed to it.
466 */
467
468void _CPU_Context_save_fp(
469  void **fp_context_ptr
470);
471
472/*
473 *  _CPU_Context_restore_fp
474 *
475 *  This routine restores the floating point context passed to it.
476 */
477
478void _CPU_Context_restore_fp(
479  void **fp_context_ptr
480);
481
482#ifdef __cplusplus
483}
484#endif
485
486#endif
487/* end of include file */
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