[ac7d5ef0] | 1 | /* cpu.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the Intel |
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| 4 | * i386 processor. |
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| 5 | * |
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[60b791ad] | 6 | * COPYRIGHT (c) 1989-1998. |
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[ac7d5ef0] | 7 | * On-Line Applications Research Corporation (OAR). |
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[03f2154e] | 8 | * Copyright assigned to U.S. Government, 1994. |
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[ac7d5ef0] | 9 | * |
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[98e4ebf5] | 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 12 | * http://www.OARcorp.com/rtems/license.html. |
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[ac7d5ef0] | 13 | * |
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| 14 | * $Id$ |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef __CPU_h |
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| 18 | #define __CPU_h |
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| 19 | |
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| 20 | #ifdef __cplusplus |
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| 21 | extern "C" { |
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| 22 | #endif |
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| 23 | |
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[95a1d50] | 24 | #include <rtems/score/i386.h> /* pick up machine definitions */ |
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[67a2288] | 25 | #include <libcpu/cpu.h> |
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| 26 | |
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[88d594a] | 27 | #ifndef ASM |
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[5e9b32b] | 28 | #include <rtems/score/i386types.h> |
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[88d594a] | 29 | #endif |
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[ac7d5ef0] | 30 | |
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| 31 | /* conditional compilation parameters */ |
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| 32 | |
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| 33 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 34 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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| 35 | |
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| 36 | /* |
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| 37 | * i386 has an RTEMS allocated and managed interrupt stack. |
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| 38 | */ |
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| 39 | |
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| 40 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 41 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 42 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 43 | |
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[937a6f3c] | 44 | /* |
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| 45 | * Does the RTEMS invoke the user's ISR with the vector number and |
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| 46 | * a pointer to the saved interrupt frame (1) or just the vector |
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| 47 | * number (0)? |
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| 48 | */ |
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| 49 | |
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| 50 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 51 | |
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[ac7d5ef0] | 52 | /* |
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| 53 | * Some family members have no FP, some have an FPU such as the i387 |
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| 54 | * for the i386, others have it built in (i486DX, Pentium). |
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| 55 | */ |
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| 56 | |
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| 57 | #if ( I386_HAS_FPU == 1 ) |
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| 58 | #define CPU_HARDWARE_FP TRUE /* i387 for i386 */ |
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| 59 | #else |
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| 60 | #define CPU_HARDWARE_FP FALSE |
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| 61 | #endif |
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| 62 | |
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| 63 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 64 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 65 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 66 | |
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[8b2ee37c] | 67 | #define CPU_PROVIDES_IDLE_THREAD_BODY YES |
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[ac7d5ef0] | 68 | #define CPU_STACK_GROWS_UP FALSE |
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| 69 | #define CPU_STRUCTURE_ALIGNMENT |
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| 70 | |
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[e2d79559] | 71 | /* |
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| 72 | * Define what is required to specify how the network to host conversion |
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| 73 | * routines are handled. |
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| 74 | */ |
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| 75 | |
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| 76 | #define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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| 77 | #define CPU_BIG_ENDIAN FALSE |
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| 78 | #define CPU_LITTLE_ENDIAN TRUE |
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| 79 | |
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[ac7d5ef0] | 80 | /* structures */ |
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| 81 | |
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| 82 | /* |
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| 83 | * Basic integer context for the i386 family. |
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| 84 | */ |
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| 85 | |
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| 86 | typedef struct { |
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| 87 | unsigned32 eflags; /* extended flags register */ |
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| 88 | void *esp; /* extended stack pointer register */ |
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| 89 | void *ebp; /* extended base pointer register */ |
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| 90 | unsigned32 ebx; /* extended bx register */ |
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| 91 | unsigned32 esi; /* extended source index register */ |
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| 92 | unsigned32 edi; /* extended destination index flags register */ |
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| 93 | } Context_Control; |
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| 94 | |
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| 95 | /* |
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| 96 | * FP context save area for the i387 numeric coprocessors. |
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| 97 | */ |
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| 98 | |
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| 99 | typedef struct { |
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| 100 | unsigned8 fp_save_area[108]; /* context size area for I80387 */ |
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| 101 | /* 28 bytes for environment */ |
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| 102 | } Context_Control_fp; |
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| 103 | |
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[8b2ee37c] | 104 | |
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[ac7d5ef0] | 105 | /* |
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| 106 | * The following structure defines the set of information saved |
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[8b2ee37c] | 107 | * on the current stack by RTEMS upon receipt of execptions. |
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| 108 | * |
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| 109 | * idtIndex is either the interrupt number or the trap/exception number. |
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| 110 | * faultCode is the code pushed by the processor on some exceptions. |
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[ac7d5ef0] | 111 | */ |
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| 112 | |
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| 113 | typedef struct { |
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[8b2ee37c] | 114 | |
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| 115 | unsigned32 edi, |
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| 116 | esi, |
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| 117 | ebp, |
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| 118 | esp0, |
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| 119 | ebx, |
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| 120 | edx, |
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| 121 | ecx, |
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| 122 | eax, |
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| 123 | idtIndex, |
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| 124 | faultCode, |
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| 125 | eip, |
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| 126 | cs, |
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| 127 | eflags; |
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| 128 | }CPU_Exception_frame; |
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| 129 | |
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| 130 | /* |
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| 131 | * The following structure defines the set of information saved |
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| 132 | * on the current stack by RTEMS upon receipt of each interrupt |
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| 133 | * that will lead to re-enter the kernel to signal the thread. |
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| 134 | */ |
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| 135 | |
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| 136 | typedef CPU_Exception_frame CPU_Interrupt_frame; |
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[ac7d5ef0] | 137 | |
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| 138 | /* |
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| 139 | * The following table contains the information required to configure |
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| 140 | * the i386 specific parameters. |
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| 141 | */ |
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| 142 | |
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| 143 | typedef struct { |
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| 144 | void (*pretasking_hook)( void ); |
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| 145 | void (*predriver_hook)( void ); |
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| 146 | void (*postdriver_hook)( void ); |
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| 147 | void (*idle_task)( void ); |
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| 148 | boolean do_zero_of_workspace; |
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| 149 | unsigned32 interrupt_stack_size; |
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[75f09e5] | 150 | unsigned32 extra_mpci_receive_server_stack; |
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[f581163a] | 151 | void * (*stack_allocate_hook)( unsigned32 ); |
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| 152 | void (*stack_free_hook)( void* ); |
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| 153 | /* end of fields required on all CPUs */ |
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[ac7d5ef0] | 154 | |
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| 155 | unsigned32 interrupt_table_segment; |
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| 156 | void *interrupt_table_offset; |
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| 157 | } rtems_cpu_table; |
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| 158 | |
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| 159 | /* |
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| 160 | * context size area for floating point |
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| 161 | * |
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| 162 | * NOTE: This is out of place on the i386 to avoid a forward reference. |
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| 163 | */ |
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| 164 | |
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| 165 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 166 | |
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| 167 | /* variables */ |
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| 168 | |
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[c627b2a3] | 169 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
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| 170 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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| 171 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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[ac7d5ef0] | 172 | |
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| 173 | /* constants */ |
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| 174 | |
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| 175 | /* |
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| 176 | * This defines the number of levels and the mask used to pick those |
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| 177 | * bits out of a thread mode. |
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| 178 | */ |
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| 179 | |
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| 180 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
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| 181 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
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| 182 | |
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| 183 | /* |
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[75f09e5] | 184 | * extra stack required by the MPCI receive server thread |
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[ac7d5ef0] | 185 | */ |
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| 186 | |
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[75f09e5] | 187 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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[ac7d5ef0] | 188 | |
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| 189 | /* |
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| 190 | * i386 family supports 256 distinct vectors. |
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| 191 | */ |
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| 192 | |
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[9700578] | 193 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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| 194 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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[ac7d5ef0] | 195 | |
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| 196 | /* |
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| 197 | * Minimum size of a thread's stack. |
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| 198 | */ |
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| 199 | |
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[3652ad35] | 200 | #define CPU_STACK_MINIMUM_SIZE 1024 |
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[ac7d5ef0] | 201 | |
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| 202 | /* |
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| 203 | * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. |
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| 204 | */ |
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| 205 | |
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| 206 | #define CPU_ALIGNMENT 4 |
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| 207 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 208 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 209 | |
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| 210 | /* |
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| 211 | * On i386 thread stacks require no further alignment after allocation |
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| 212 | * from the Workspace. |
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| 213 | */ |
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| 214 | |
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| 215 | #define CPU_STACK_ALIGNMENT 0 |
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| 216 | |
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| 217 | /* macros */ |
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| 218 | |
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| 219 | /* |
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| 220 | * ISR handler macros |
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| 221 | * |
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| 222 | * These macros perform the following functions: |
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| 223 | * + disable all maskable CPU interrupts |
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| 224 | * + restore previous interrupt level (enable) |
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| 225 | * + temporarily restore interrupts (flash) |
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| 226 | * + set a particular level |
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| 227 | */ |
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| 228 | |
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| 229 | #define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) |
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| 230 | |
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| 231 | #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) |
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| 232 | |
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| 233 | #define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) |
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| 234 | |
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| 235 | #define _CPU_ISR_Set_level( _new_level ) \ |
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| 236 | { \ |
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| 237 | if ( _new_level ) asm volatile ( "cli" ); \ |
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| 238 | else asm volatile ( "sti" ); \ |
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| 239 | } |
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| 240 | |
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[3a4ae6c] | 241 | unsigned32 _CPU_ISR_Get_level( void ); |
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| 242 | |
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[ac7d5ef0] | 243 | /* end of ISR handler macros */ |
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| 244 | |
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| 245 | /* |
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| 246 | * Context handler macros |
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| 247 | * |
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| 248 | * These macros perform the following functions: |
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| 249 | * + initialize a context area |
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| 250 | * + restart the current thread |
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| 251 | * + calculate the initial pointer into a FP context area |
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| 252 | * + initialize an FP context area |
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| 253 | */ |
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| 254 | |
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| 255 | #define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 |
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| 256 | #define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 |
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| 257 | |
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| 258 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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[9700578] | 259 | _isr, _entry_point, _is_fp ) \ |
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[ac7d5ef0] | 260 | do { \ |
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| 261 | unsigned32 _stack; \ |
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| 262 | \ |
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| 263 | if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \ |
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| 264 | else (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \ |
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| 265 | \ |
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| 266 | _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \ |
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| 267 | \ |
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| 268 | *((proc_ptr *)(_stack)) = (_entry_point); \ |
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| 269 | (_the_context)->ebp = (void *) _stack; \ |
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| 270 | (_the_context)->esp = (void *) _stack; \ |
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| 271 | } while (0) |
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| 272 | |
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| 273 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 274 | _CPU_Context_restore( (_the_context) ); |
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| 275 | |
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| 276 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 277 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
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| 278 | |
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| 279 | #define _CPU_Context_Initialize_fp( _fp_area ) \ |
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| 280 | { \ |
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[3652ad35] | 281 | unsigned32 *_source = (unsigned32 *) &_CPU_Null_fp_context; \ |
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| 282 | unsigned32 *_destination = *(_fp_area); \ |
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[ac7d5ef0] | 283 | unsigned32 _index; \ |
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| 284 | \ |
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| 285 | for ( _index=0 ; _index < CPU_CONTEXT_FP_SIZE/4 ; _index++ ) \ |
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| 286 | *_destination++ = *_source++; \ |
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| 287 | } |
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| 288 | |
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| 289 | /* end of Context handler macros */ |
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| 290 | |
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| 291 | /* |
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| 292 | * Fatal Error manager macros |
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| 293 | * |
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| 294 | * These macros perform the following functions: |
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| 295 | * + disable interrupts and halt the CPU |
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| 296 | */ |
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| 297 | |
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| 298 | #define _CPU_Fatal_halt( _error ) \ |
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| 299 | { \ |
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| 300 | asm volatile ( "cli ; \ |
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| 301 | movl %0,%%eax ; \ |
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| 302 | hlt" \ |
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| 303 | : "=r" ((_error)) : "0" ((_error)) \ |
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| 304 | ); \ |
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| 305 | } |
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| 306 | |
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| 307 | /* end of Fatal Error manager macros */ |
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| 308 | |
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| 309 | /* |
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| 310 | * Bitfield handler macros |
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| 311 | * |
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| 312 | * These macros perform the following functions: |
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| 313 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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| 314 | */ |
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| 315 | |
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[9700578] | 316 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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| 317 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
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| 318 | |
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[ac7d5ef0] | 319 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 320 | { \ |
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| 321 | register unsigned16 __value_in_register = (_value); \ |
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| 322 | \ |
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| 323 | _output = 0; \ |
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| 324 | \ |
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| 325 | asm volatile ( "bsfw %0,%1 " \ |
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| 326 | : "=r" (__value_in_register), "=r" (_output) \ |
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| 327 | : "0" (__value_in_register), "1" (_output) \ |
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| 328 | ); \ |
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| 329 | } |
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| 330 | |
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| 331 | /* end of Bitfield handler macros */ |
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| 332 | |
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| 333 | /* |
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| 334 | * Priority handler macros |
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| 335 | * |
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| 336 | * These macros perform the following functions: |
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| 337 | * + return a mask with the bit for this major/minor portion of |
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| 338 | * of thread priority set. |
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| 339 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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| 340 | * into an index into the thread ready chain bit maps |
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| 341 | */ |
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| 342 | |
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| 343 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 344 | ( 1 << (_bit_number) ) |
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| 345 | |
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[9700578] | 346 | #define _CPU_Priority_bits_index( _priority ) \ |
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[ac7d5ef0] | 347 | (_priority) |
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| 348 | |
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| 349 | /* functions */ |
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| 350 | |
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| 351 | /* |
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| 352 | * _CPU_Initialize |
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| 353 | * |
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| 354 | * This routine performs CPU dependent initialization. |
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| 355 | */ |
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| 356 | |
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| 357 | void _CPU_Initialize( |
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| 358 | rtems_cpu_table *cpu_table, |
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| 359 | void (*thread_dispatch) |
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| 360 | ); |
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| 361 | |
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[637df35] | 362 | /* |
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| 363 | * _CPU_ISR_install_raw_handler |
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| 364 | * |
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| 365 | * This routine installs a "raw" interrupt handler directly into the |
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| 366 | * processor's vector table. |
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| 367 | */ |
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| 368 | |
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| 369 | void _CPU_ISR_install_raw_handler( |
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| 370 | unsigned32 vector, |
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| 371 | proc_ptr new_handler, |
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| 372 | proc_ptr *old_handler |
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| 373 | ); |
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| 374 | |
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[ac7d5ef0] | 375 | /* |
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| 376 | * _CPU_ISR_install_vector |
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| 377 | * |
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| 378 | * This routine installs an interrupt vector. |
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| 379 | */ |
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| 380 | |
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| 381 | void _CPU_ISR_install_vector( |
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| 382 | unsigned32 vector, |
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| 383 | proc_ptr new_handler, |
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| 384 | proc_ptr *old_handler |
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| 385 | ); |
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| 386 | |
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| 387 | /* |
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| 388 | * _CPU_Context_switch |
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| 389 | * |
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| 390 | * This routine switches from the run context to the heir context. |
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| 391 | */ |
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| 392 | |
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| 393 | void _CPU_Context_switch( |
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| 394 | Context_Control *run, |
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| 395 | Context_Control *heir |
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| 396 | ); |
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| 397 | |
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| 398 | /* |
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| 399 | * _CPU_Context_restore |
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| 400 | * |
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[77ea27fc] | 401 | * This routine is generally used only to restart self in an |
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[ac7d5ef0] | 402 | * efficient manner and avoid stack conflicts. |
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| 403 | */ |
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| 404 | |
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| 405 | void _CPU_Context_restore( |
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| 406 | Context_Control *new_context |
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| 407 | ); |
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| 408 | |
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| 409 | /* |
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| 410 | * _CPU_Context_save_fp |
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| 411 | * |
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| 412 | * This routine saves the floating point context passed to it. |
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| 413 | */ |
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| 414 | |
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| 415 | void _CPU_Context_save_fp( |
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| 416 | void **fp_context_ptr |
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| 417 | ); |
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| 418 | |
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| 419 | /* |
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| 420 | * _CPU_Context_restore_fp |
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| 421 | * |
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| 422 | * This routine restores the floating point context passed to it. |
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| 423 | */ |
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| 424 | |
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| 425 | void _CPU_Context_restore_fp( |
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| 426 | void **fp_context_ptr |
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| 427 | ); |
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| 428 | |
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| 429 | #ifdef __cplusplus |
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| 430 | } |
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| 431 | #endif |
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| 432 | |
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| 433 | #endif |
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| 434 | /* end of include file */ |
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