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hppa.h @ 7908ba5b

4.104.114.84.95

Last change on this file since 7908ba5b was 7908ba5b, checked in by Joel Sherrill <joel.sherrill@…>, on 02/18/99 at 18:28:24

Part of the automake VI patch from Ralf Corsepius <corsepiu@…>:

4) rtems-rc-19990202-0.diff /reorg-score-cpu.sh

reorg-score-cpu.sh reorganizes the cpu/<cpu>/* subdirectories in a
similar manner than previous reorg scripts did. rtems-rc-19990202-0.diff
contains the diffs after reorg-score-cpu.sh has been run on a
rtems-19981215 snapshot + my patches up to rtems-rc-19990131-2.diff.

This patch is rather nasty and may break something. However, I've tested
it for about 10 different target/bsp pairs and believe to have shaken
out most bugs.

I wonder about the following .h files that were not moved:

a29k/asm.h
a29k/cpu_asm.h
i386/asm.h
i960/asm.h
m68k/asm.h
m68k/m68302.h
m68k/m68360.h
m68k/qsm.h
m68k/sim.h
mips64orion/asm.h
mips64orion/cpu_asm.h
mips64orion/mips64orion.h
no_cpu/asm.h
no_cpu/cpu_asm.h
powerpc/asm.h
powerpc/mpc860.h
sh/asm.h
sparc/asm.h
sparc/erc32.h

Property mode set to 100644

File size: 29.4 KB

Line
1	/*
2	* Description:
3	*
4	* Definitions for HP PA Risc
5	* ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
6	*
7	* COPYRIGHT (c) 1994 by Division Incorporated
8	*
9	* The license and distribution terms for this file may be
10	* found in the file LICENSE in this distribution or at
11	* http://www.OARcorp.com/rtems/license.html.
12	*
13	* Note:
14	* This file is included by both C and assembler code ( -DASM )
15	*
16	* $Id$
17	*/
18
19	#ifndef _INCLUDE_HPPA_H
20	#define _INCLUDE_HPPA_H
21
22	#ifdef ASM
23	#include <rtems/score/targopts.h>
24	#endif
25
26	#if defined(__cplusplus)
27	extern "C" {
28	#endif
29
30	/*
31	* This section contains the information required to build
32	* RTEMS for a particular member of the Hewlett Packard
33	* PA-RISC family. It does this by setting variables to
34	* indicate which implementation dependent features are
35	* present in a particular member of the family.
36	*/
37
38	#if defined(hppa7100)
39
40	#define CPU_MODEL_NAME "hppa 7100"
41
42	#elif defined(hppa7200)
43
44	#define CPU_MODEL_NAME "hppa 7200"
45
46	#else
47
48	#error "Unsupported CPU Model"
49
50	#endif
51
52	/*
53	* Define the name of the CPU family.
54	*/
55
56	#if !defined(CPU_NAME)
57	#define CPU_NAME "HP PA-RISC 1.1"
58	#endif
59
60	/*
61	* Processor Status Word (PSW) Masks
62	*/
63
64
65	#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
66	#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
67	#define HPPA_PSW_r2 0x20000000 /* reserved */
68	#define HPPA_PSW_r3 0x10000000 /* reserved */
69	#define HPPA_PSW_r4 0x08000000 /* reserved */
70	#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
71	#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
72	#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
73	#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
74	#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
75	#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
76	#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
77	#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
78	#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
79	#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
80	#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
81	#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
82	#define HPPA_PSW_r24 0x00000080 /* reserved */
83	#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
84	#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
85	#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
86	#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
87	#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
88	#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
89	#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
90	/* Low-Priority Machine Check */
91	/* Interruption Enable */
92
93	/*
94	* HPPA traps and interrupts
95	* basic layout. Note numbers do not denote priority
96	*
97	* 0-31 basic traps and interrupts defined by HPPA architecture
98	* 0-31 32 external interrupts
99	* 32-... bsp defined
100	*/
101
102	#define HPPA_TRAP_NON_EXISTENT 0
103	/* group 1 */
104	#define HPPA_TRAP_HIGH_PRIORITY_MACHINE_CHECK 1
105	/* group 2 */
106	#define HPPA_TRAP_POWER_FAIL 2
107	#define HPPA_TRAP_RECOVERY_COUNTER 3
108	#define HPPA_TRAP_EXTERNAL_INTERRUPT 4
109	#define HPPA_TRAP_LOW_PRIORITY_MACHINE_CHECK 5
110	#define HPPA_TRAP_PERFORMANCE_MONITOR 29
111	/* group 3 */
112	#define HPPA_TRAP_INSTRUCTION_TLB_MISS 6
113	#define HPPA_TRAP_INSTRUCTION_MEMORY_PROTECTION 7
114	#define HPPA_TRAP_INSTRUCTION_DEBUG 30
115	#define HPPA_TRAP_ILLEGAL_INSTRUCTION 8
116	#define HPPA_TRAP_BREAK_INSTRUCTION 9
117	#define HPPA_TRAP_PRIVILEGED_OPERATION 10
118	#define HPPA_TRAP_PRIVILEGED_REGISTER 11
119	#define HPPA_TRAP_OVERFLOW 12
120	#define HPPA_TRAP_CONDITIONAL 13
121	#define HPPA_TRAP_ASSIST_EXCEPTION 14
122	#define HPPA_TRAP_DATA_TLB_MISS 15
123	#define HPPA_TRAP_NON_ACCESS_INSTRUCTION_TLB_MISS 16
124	#define HPPA_TRAP_NON_ACCESS_DATA_TLB_MISS 17
125	#define HPPA_TRAP_DATA_MEMORY_ACCESS_RIGHTS 26
126	#define HPPA_TRAP_DATA_MEMORY_PROTECTION_ID 27
127	#define HPPA_TRAP_UNALIGNED_DATA_REFERENCE 28
128	#define HPPA_TRAP_DATA_MEMORY_PROTECTION 18
129	#define HPPA_TRAP_DATA_MEMORY_BREAK 19
130	#define HPPA_TRAP_TLB_DIRTY_BIT 20
131	#define HPPA_TRAP_PAGE_REFERENCE 21
132	#define HPPA_TRAP_DATA_DEBUG 31
133	#define HPPA_TRAP_ASSIST_EMULATION 22
134	/* group 4 */
135	#define HPPA_TRAP_HIGHER_PRIVILEGE_TRANSFER 23
136	#define HPPA_TRAP_LOWER_PRIVILEGE_TRANSFER 24
137	#define HPPA_TRAP_TAKEN_BRANCH 25
138
139	#define HPPA_INTERNAL_TRAPS 32
140
141	/* External Interrupts via interrupt 4 */
142
143	#define HPPA_INTERRUPT_EXTERNAL_0 0
144	#define HPPA_INTERRUPT_EXTERNAL_1 1
145	#define HPPA_INTERRUPT_EXTERNAL_2 2
146	#define HPPA_INTERRUPT_EXTERNAL_3 3
147	#define HPPA_INTERRUPT_EXTERNAL_4 4
148	#define HPPA_INTERRUPT_EXTERNAL_5 5
149	#define HPPA_INTERRUPT_EXTERNAL_6 6
150	#define HPPA_INTERRUPT_EXTERNAL_7 7
151	#define HPPA_INTERRUPT_EXTERNAL_8 8
152	#define HPPA_INTERRUPT_EXTERNAL_9 9
153	#define HPPA_INTERRUPT_EXTERNAL_10 10
154	#define HPPA_INTERRUPT_EXTERNAL_11 11
155	#define HPPA_INTERRUPT_EXTERNAL_12 12
156	#define HPPA_INTERRUPT_EXTERNAL_13 13
157	#define HPPA_INTERRUPT_EXTERNAL_14 14
158	#define HPPA_INTERRUPT_EXTERNAL_15 15
159	#define HPPA_INTERRUPT_EXTERNAL_16 16
160	#define HPPA_INTERRUPT_EXTERNAL_17 17
161	#define HPPA_INTERRUPT_EXTERNAL_18 18
162	#define HPPA_INTERRUPT_EXTERNAL_19 19
163	#define HPPA_INTERRUPT_EXTERNAL_20 20
164	#define HPPA_INTERRUPT_EXTERNAL_21 21
165	#define HPPA_INTERRUPT_EXTERNAL_22 22
166	#define HPPA_INTERRUPT_EXTERNAL_23 23
167	#define HPPA_INTERRUPT_EXTERNAL_24 24
168	#define HPPA_INTERRUPT_EXTERNAL_25 25
169	#define HPPA_INTERRUPT_EXTERNAL_26 26
170	#define HPPA_INTERRUPT_EXTERNAL_27 27
171	#define HPPA_INTERRUPT_EXTERNAL_28 28
172	#define HPPA_INTERRUPT_EXTERNAL_29 29
173	#define HPPA_INTERRUPT_EXTERNAL_30 30
174	#define HPPA_INTERRUPT_EXTERNAL_31 31
175
176	#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
177	#define HPPA_EXTERNAL_INTERRUPTS 32
178
179	/* BSP defined interrupts begin here */
180
181	#define HPPA_INTERRUPT_MAX 32
182
183	/*
184	* Cache characteristics
185	*/
186
187	#define HPPA_CACHELINE_SIZE 32
188	#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
189
190	/*
191	* page size characteristics
192	*/
193
194	#define HPPA_PAGE_SIZE 4096
195	#define HPPA_PAGE_MASK (0xfffff000)
196
197
198	/*
199	* TLB characteristics
200	*
201	* Flags and Access Control layout for using TLB protection insertion
202	*
203	* 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
204	* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
205	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
206	* \|?\|?\|T\|D\|B\|type \|PL1\|Pl2\|U\| access id \|?\|
207	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
208	*
209	*/
210
211	/*
212	* Access rights (type + PL1 + PL2)
213	*/
214	#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */
215	#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */
216	#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */
217	#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */
218	#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */
219	#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */
220	#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */
221	#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */
222
223	/*
224	* Floating point status register definitions
225	*/
226
227	#define HPPA_FPSTATUS_ENABLE_I 0x00000001 /* inexact operation */
228	#define HPPA_FPSTATUS_ENABLE_U 0x00000002 /* underflow */
229	#define HPPA_FPSTATUS_ENABLE_O 0x00000004 /* overflow */
230	#define HPPA_FPSTATUS_ENABLE_Z 0x00000008 /* division by zero */
231	#define HPPA_FPSTATUS_ENABLE_V 0x00000010 /* invalid operation */
232	#define HPPA_FPSTATUS_D 0x00000020 /* denormalize as zero */
233	#define HPPA_FPSTATUS_T 0x00000040 /* delayed trap */
234	#define HPPA_FPSTATUS_RM_MASK 0x00000600 /* rounding mode */
235	#define HPPA_FPSTATUS_RM_SHIFT 9
236	#define HPPA_FPSTATUS_CQ_MASK 0x001FFC00 /* compare queue */
237	#define HPPA_FPSTATUS_CQ_SHIFT 13
238	#define HPPA_FPSTATUS_C 0x04000000 /* most recent ompare bit */
239	#define HPPA_FPSTATUS_FLAG_I 0x08000000 /* inexact */
240	#define HPPA_FPSTATUS_FLAG_U 0x10000000 /* underflow */
241	#define HPPA_FPSTATUS_FLAG_O 0x20000000 /* overflow */
242	#define HPPA_FPSTATUS_FLAG_Z 0x40000000 /* division by zero */
243	#define HPPA_FPSTATUS_FLAG_V 0x80000000 /* invalid operation */
244
245
246	/*
247	* Inline macros for misc. interesting opcodes
248	*/
249
250	/* generate a global label */
251	#define HPPA_ASM_LABEL(label) \
252	asm(".export " label ", ! .label " label);
253
254	/* Return From Interrupt RFI */
255	#define HPPA_ASM_RFI() asm volatile ("rfi")
256
257	/* Set System Mask SSM i,t */
258	#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
259	: "=r" (gr) \
260	: "i" (i))
261	/* Reset System Mask RSM i,t */
262	#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
263	: "=r" (gr) \
264	: "i" (i))
265	/* Move To System Mask MTSM r */
266	#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
267	: : "r" (gr))
268
269	/* Load Space Identifier LDSID (s,b),t */
270	#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
271	: "=r" (grt) \
272	: "i" (sr), \
273	"r" (grb))
274
275	/*
276	* Gcc extended asm doesn't really allow for treatment of space registers
277	* as "registers", so we have to use "i" format.
278	* Unfortunately this means that the "=" constraint is not available.
279	*/
280
281	/* Move To Space Register MTSP r,sr */
282	#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
283	: : "i" (sr), \
284	"r" (gr))
285
286	/* Move From Space Register MFSP sr,t */
287	#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
288	: "=r" (gr) \
289	: "i" (sr))
290
291	/* Move To Control register MTCTL r,t */
292	#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
293	: : "i" (cr), \
294	"r" (gr))
295
296	/* Move From Control register MFCTL r,t */
297	#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
298	: "=r" (gr) \
299	: "i" (cr))
300
301	/* Synchronize caches SYNC */
302	#define HPPA_ASM_SYNC() asm volatile ("sync")
303
304	/* Probe Read Access PROBER (s,b),r,t */
305	#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
306	asm volatile ("prober (%1,%2),%3,%0" \
307	: "=r" (grt) \
308	: "i" (sr), \
309	"r" (groff), \
310	"r" (gracc))
311
312	/* Probe Read Access Immediate PROBERI (s,b),i,t*/
313	#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
314	asm volatile ("proberi (%1,%2),%3,%0" \
315	: "=r" (grt) \
316	: "i" (sr), \
317	"r" (groff), \
318	"i" (iacc))
319
320	/* Probe Write Access PROBEW (s,b),r,t */
321	#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
322	asm volatile ("probew (%1,%2),%3,%0" \
323	: "=r" (grt) \
324	: "i" (sr), \
325	"r" (groff), \
326	"r" (gracc))
327
328	/* Probe Write Access Immediate PROBEWI (s,b),i,t */
329	#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
330	asm volatile ("probewi (%1,%2),%3,%0" \
331	: "=r" (grt) \
332	: "i" (sr), \
333	"r" (groff), \
334	"i" (iacc))
335
336	/* Load Physical Address LPA x(s,b),t */
337	#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
338	: "=r" (grt) \
339	: "i" (sr), \
340	"r" (grb))
341
342	/* Load Coherence Index LCI x(s,b),t */
343	/* AKA: Load Hash Address LHA x(s,b),t */
344	#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
345	: "=r" (grt) \
346	: "r" (grx),\
347	"i" (sr), \
348	"r" (grb))
349	#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
350
351	/* Purge Data Tlb PDTLB x(s,b) */
352	#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
353	: : "r" (grx), \
354	"i" (sr), \
355	"r" (grb))
356
357	/* Purge Instruction Tlb PITLB x(s,b) */
358	#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
359	: : "r" (grx), \
360	"i" (sr), \
361	"r" (grb))
362
363	/* Purge Data Tlb Entry PDTLBE x(s,b) */
364	#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
365	: : "r" (grx), \
366	"i" (sr), \
367	"r" (grb))
368
369	/* Purge Instruction Tlb Entry PITLBE x(s,b) */
370	#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
371	: : "r" (grx), \
372	"i" (sr), \
373	"r" (grb))
374
375
376	/* Insert Data TLB Address IDTLBA r,(s,b) */
377	#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
378	: : "r" (gr), \
379	"i" (sr), \
380	"r" (grb))
381
382	/* Insert Instruction TLB Address IITLBA r,(s,b) */
383	#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
384	: : "r" (gr), \
385	"i" (sr), \
386	"r" (grb))
387
388	/* Insert Data TLB Protection IDTLBP r,(s,b) */
389	#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
390	: : "r" (gr), \
391	"i" (sr), \
392	"r" (grb))
393
394	/* Insert Instruction TLB Protection IITLBP r,(s,b) */
395	#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
396	: : "r" (gr), \
397	"i" (sr), \
398	"r" (grb))
399
400	/* Purge Data Cache PDC x(s,b) */
401	#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
402	: : "r" (grx), \
403	"i" (sr), \
404	"r" (grb))
405
406	/* Flush Data Cache FDC x(s,b) */
407	#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
408	: : "r" (grx), \
409	"i" (sr), \
410	"r" (grb))
411
412	/* Flush Instruction Cache FDC x(s,b) */
413	#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
414	: : "r" (grx), \
415	"i" (sr), \
416	"r" (grb))
417
418	/* Flush Data Cache Entry FDCE x(s,b) */
419	#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
420	: : "r" (grx), \
421	"i" (sr), \
422	"r" (grb))
423
424	/* Flush Instruction Cache Entry FICE x(s,b) */
425	#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
426	: : "r" (grx), \
427	"i" (sr), \
428	"r" (grb))
429
430	/* Break BREAK i5,i13 */
431	#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
432	: : "i" (i5), \
433	"i" (i13))
434
435	/* Load and Clear Word Short LDCWS d(s,b),t */
436	#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
437	: "=r" (grt) \
438	: "i" (i), \
439	"i" (sr), \
440	"r" (grb))
441
442	/* Load and Clear Word Indexed LDCWX x(s,b),t */
443	#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
444	: "=r" (grt) \
445	: "r" (grx), \
446	"i" (sr), \
447	"r" (grb))
448
449	/* Load Word Absolute Short LDWAS d(b),t */
450	/* NOTE: "short" here means "short displacement" */
451	#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
452	: "=r" (gr) \
453	: "i" (disp), \
454	"r" (grbase))
455
456	/* Store Word Absolute Short STWAS r,d(b) */
457	/* NOTE: "short" here means "short displacement" */
458	#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
459	: : "r" (gr), \
460	"i" (disp), \
461	"r" (grbase))
462
463	/*
464	* Swap bytes
465	* REFERENCE: PA72000 TRM -- Appendix C
466	*/
467	#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
468	" shd %1,%1,16,%0 \n\
469	dep %0,15,8,%0 \n\
470	shd %1,%0,8,%0" \
471	: "=r" (swapped) \
472	: "r" (value) \
473	)
474
475
476	/* 72000 Diagnose instructions follow
477	* These macros assume gas knows about these instructions.
478	* gas2.2.u1 did not.
479	* I added them to my copy and installed it locally.
480	*
481	* There are very special requirements for these guys
482	* ref: TRM 6.1.3 Programming Constraints
483	*
484	* The macros below handle the following rules
485	*
486	* Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
487	* Must never be nullified (hence the leading nop)
488	* NOP must preced every RDD,RDT,WDD,WDT,RDTLB
489	* Instruction preceeding GR_SHDW must not set any of the GR's saved
490	*
491	* The macros do NOT deal with the following problems
492	* doubled DIAGNOSE instructions must not straddle a page boundary
493	* if code translation enabled. (since 2nd could trap on ITLB)
494	* If you care about DHIT and DPE bits of DR0, then
495	* No store instruction in the 2 insn window before RDD
496	*/
497
498
499	/* Move To CPU/DIAG register MTCPU r,t */
500	#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
501	" mtcpu %1,%0 \n" \
502	" mtcpu %1,%0" \
503	: : "i" (dr), \
504	"r" (gr))
505
506	/* Move From CPU/DIAG register MFCPU r,t */
507	#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
508	" mfcpu %1,%0\n" \
509	" mfcpu %1,%0" \
510	: "=r" (gr) \
511	: "i" (dr))
512
513	/* Transfer of Control Enable TOC_EN */
514	#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
515	" tocen")
516
517	/* Transfer of Control Disable TOC_DIS */
518	#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
519	" tocdis")
520
521	/* Shadow Registers to General Register SHDW_GR */
522	#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
523	" shdwgr" \
524	::: "r1" "r8" "r9" "r16" \
525	"r17" "r24" "r25")
526
527	/* General Registers to Shadow Register GR_SHDW */
528	#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
529	" grshdw \n" \
530	" grshdw")
531
532	/*
533	* Definitions of special registers for use by the above macros.
534	*/
535
536	/* Hardware Space Registers */
537	#define HPPA_SR0 0
538	#define HPPA_SR1 1
539	#define HPPA_SR2 2
540	#define HPPA_SR3 3
541	#define HPPA_SR4 4
542	#define HPPA_SR5 5
543	#define HPPA_SR6 6
544	#define HPPA_SR7 7
545
546	/* Hardware Control Registers */
547	#define HPPA_CR0 0
548	#define HPPA_RCTR 0 /* Recovery Counter Register */
549
550	#define HPPA_CR8 8 /* Protection ID 1 */
551	#define HPPA_PIDR1 8
552
553	#define HPPA_CR9 9 /* Protection ID 2 */
554	#define HPPA_PIDR2 9
555
556	#define HPPA_CR10 10
557	#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
558
559	#define HPPA_CR11 11
560	#define HPPA_SAR 11 /* Shift Amount Register */
561
562	#define HPPA_CR12 12
563	#define HPPA_PIDR3 12 /* Protection ID 3 */
564
565	#define HPPA_CR13 13
566	#define HPPA_PIDR4 13 /* Protection ID 4 */
567
568	#define HPPA_CR14 14
569	#define HPPA_IVA 14 /* Interrupt Vector Address */
570
571	#define HPPA_CR15 15
572	#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
573
574	#define HPPA_CR16 16
575	#define HPPA_ITMR 16 /* Interval Timer */
576
577	#define HPPA_CR17 17
578	#define HPPA_PCSQ 17 /* Program Counter Space queue */
579
580	#define HPPA_CR18 18
581	#define HPPA_PCOQ 18 /* Program Counter Offset queue */
582
583	#define HPPA_CR19 19
584	#define HPPA_IIR 19 /* Interruption Instruction Register */
585
586	#define HPPA_CR20 20
587	#define HPPA_ISR 20 /* Interruption Space Register */
588
589	#define HPPA_CR21 21
590	#define HPPA_IOR 21 /* Interruption Offset Register */
591
592	#define HPPA_CR22 22
593	#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
594
595	#define HPPA_CR23 23
596	#define HPPA_EIRR 23 /* External Interrupt Request */
597
598	#define HPPA_CR24 24
599	#define HPPA_PPDA 24 /* Physcial Page Directory Address */
600	#define HPPA_TR0 24 /* Temporary register 0 */
601
602	#define HPPA_CR25 25
603	#define HPPA_HTA 25 /* Hash Table Address */
604	#define HPPA_TR1 25 /* Temporary register 1 */
605
606	#define HPPA_CR26 26
607	#define HPPA_TR2 26 /* Temporary register 2 */
608
609	#define HPPA_CR27 27
610	#define HPPA_TR3 27 /* Temporary register 3 */
611
612	#define HPPA_CR28 28
613	#define HPPA_TR4 28 /* Temporary register 4 */
614
615	#define HPPA_CR29 29
616	#define HPPA_TR5 29 /* Temporary register 5 */
617
618	#define HPPA_CR30 30
619	#define HPPA_TR6 30 /* Temporary register 6 */
620
621	#define HPPA_CR31 31
622	#define HPPA_CPUID 31 /* MP identifier */
623
624	/*
625	* Diagnose registers
626	*/
627
628	#define HPPA_DR0 0
629	#define HPPA_DR1 1
630	#define HPPA_DR8 8
631	#define HPPA_DR24 24
632	#define HPPA_DR25 25
633
634	/*
635	* Tear apart a break instruction to find its type.
636	*/
637	#define HPPA_BREAK5(x) ((x) & 0x1F)
638	#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
639
640	/* assemble a break instruction */
641	#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) \| (((i13) & 0x1FFF) << 13))
642
643
644	/*
645	* this won't work in ASM or non-GNU compilers
646	*/
647
648	#if !defined(ASM) && defined(__GNUC__)
649
650	/*
651	* static inline utility functions to get at control registers
652	*/
653
654	#define EMIT_GET_CONTROL(name, reg) \
655	static __inline__ unsigned int \
656	get_ ## name (void) \
657	{ \
658	unsigned int value; \
659	HPPA_ASM_MFCTL(reg, value); \
660	return value; \
661	}
662
663	#define EMIT_SET_CONTROL(name, reg) \
664	static __inline__ void \
665	set_ ## name (unsigned int new_value) \
666	{ \
667	HPPA_ASM_MTCTL(new_value, reg); \
668	}
669
670	#define EMIT_CONTROLS(name, reg) \
671	EMIT_GET_CONTROL(name, reg) \
672	EMIT_SET_CONTROL(name, reg)
673
674	EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
675	EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
676	EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
677	EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
678	EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
679	EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
680	EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
681	EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
682	EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
683	EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
684	EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
685	EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
686	EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
687	EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
688	EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
689	EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
690	EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
691	EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
692	EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
693	EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
694	EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
695	EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
696	EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
697	EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
698	EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
699	EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
700
701	#endif /* ASM and GNU */
702
703	/*
704	* If and How to invoke the debugger (a ROM debugger generally)
705	*/
706	#define CPU_INVOKE_DEBUGGER \
707	do { \
708	HPPA_ASM_BREAK(1,1); \
709	} while (0)
710
711	#ifdef __cplusplus
712	}
713	#endif
714
715	#endif /* ! _INCLUDE_HPPA_H */
716

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source: rtems/c/src/exec/score/cpu/hppa1.1/rtems/score/hppa.h @ 7908ba5b

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