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source: rtems/c/src/exec/score/cpu/hppa1.1/rtems/score/hppa.h @ 56ec190

4.104.114.84.95

Last change on this file since 56ec190 was 56ec190, checked in by Joel Sherrill <joel.sherrill@…>, on 04/19/02 at 13:25:06

2002-04-18 Ralf Corsepius <corsepiu@…>

rtems/score/hppa.h: Remove rtems/score/targopts.h.

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File size: 29.6 KB

Line
1	/*
2	* Description:
3	*
4	* Definitions for HP PA Risc
5	* ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
6	*
7	* COPYRIGHT (c) 1994 by Division Incorporated
8	*
9	* The license and distribution terms for this file may be
10	* found in the file LICENSE in this distribution or at
11	* http://www.OARcorp.com/rtems/license.html.
12	*
13	* Note:
14	* This file is included by both C and assembler code ( -DASM )
15	*
16	* $Id$
17	*/
18
19	#ifndef _INCLUDE_HPPA_H
20	#define _INCLUDE_HPPA_H
21
22	#if defined(__cplusplus)
23	extern "C" {
24	#endif
25
26	/*
27	* This section contains the information required to build
28	* RTEMS for a particular member of the Hewlett Packard
29	* PA-RISC family. It does this by setting variables to
30	* indicate which implementation dependent features are
31	* present in a particular member of the family.
32	*/
33
34	/*
35	* Hack to allow multlib effort to continue -- known to build.
36	*/
37
38	#define CPU_MODEL_NAME "hppa 7xxx"
39	#if 0
40	#if defined(rtems_multilib)
41	/*
42	* Figure out all CPU Model Feature Flags based upon compiler
43	* predefines.
44	*/
45
46	#define CPU_MODEL_NAME "rtems_multilib"
47
48	#elif defined(hppa7100)
49
50	#define CPU_MODEL_NAME "hppa 7100"
51
52	#elif defined(hppa7200)
53
54	#define CPU_MODEL_NAME "hppa 7200"
55
56	#else
57
58	#error "Unsupported CPU Model"
59
60	#endif
61	#endif
62
63	/*
64	* Define the name of the CPU family.
65	*/
66
67	#if !defined(CPU_NAME)
68	#define CPU_NAME "HP PA-RISC 1.1"
69	#endif
70
71	/*
72	* Processor Status Word (PSW) Masks
73	*/
74
75
76	#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
77	#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
78	#define HPPA_PSW_r2 0x20000000 /* reserved */
79	#define HPPA_PSW_r3 0x10000000 /* reserved */
80	#define HPPA_PSW_r4 0x08000000 /* reserved */
81	#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
82	#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
83	#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
84	#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
85	#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
86	#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
87	#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
88	#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
89	#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
90	#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
91	#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
92	#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
93	#define HPPA_PSW_r24 0x00000080 /* reserved */
94	#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
95	#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
96	#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
97	#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
98	#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
99	#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
100	#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
101	/* Low-Priority Machine Check */
102	/* Interruption Enable */
103
104	/*
105	* HPPA traps and interrupts
106	* basic layout. Note numbers do not denote priority
107	*
108	* 0-31 basic traps and interrupts defined by HPPA architecture
109	* 0-31 32 external interrupts
110	* 32-... bsp defined
111	*/
112
113	#define HPPA_TRAP_NON_EXISTENT 0
114	/* group 1 */
115	#define HPPA_TRAP_HIGH_PRIORITY_MACHINE_CHECK 1
116	/* group 2 */
117	#define HPPA_TRAP_POWER_FAIL 2
118	#define HPPA_TRAP_RECOVERY_COUNTER 3
119	#define HPPA_TRAP_EXTERNAL_INTERRUPT 4
120	#define HPPA_TRAP_LOW_PRIORITY_MACHINE_CHECK 5
121	#define HPPA_TRAP_PERFORMANCE_MONITOR 29
122	/* group 3 */
123	#define HPPA_TRAP_INSTRUCTION_TLB_MISS 6
124	#define HPPA_TRAP_INSTRUCTION_MEMORY_PROTECTION 7
125	#define HPPA_TRAP_INSTRUCTION_DEBUG 30
126	#define HPPA_TRAP_ILLEGAL_INSTRUCTION 8
127	#define HPPA_TRAP_BREAK_INSTRUCTION 9
128	#define HPPA_TRAP_PRIVILEGED_OPERATION 10
129	#define HPPA_TRAP_PRIVILEGED_REGISTER 11
130	#define HPPA_TRAP_OVERFLOW 12
131	#define HPPA_TRAP_CONDITIONAL 13
132	#define HPPA_TRAP_ASSIST_EXCEPTION 14
133	#define HPPA_TRAP_DATA_TLB_MISS 15
134	#define HPPA_TRAP_NON_ACCESS_INSTRUCTION_TLB_MISS 16
135	#define HPPA_TRAP_NON_ACCESS_DATA_TLB_MISS 17
136	#define HPPA_TRAP_DATA_MEMORY_ACCESS_RIGHTS 26
137	#define HPPA_TRAP_DATA_MEMORY_PROTECTION_ID 27
138	#define HPPA_TRAP_UNALIGNED_DATA_REFERENCE 28
139	#define HPPA_TRAP_DATA_MEMORY_PROTECTION 18
140	#define HPPA_TRAP_DATA_MEMORY_BREAK 19
141	#define HPPA_TRAP_TLB_DIRTY_BIT 20
142	#define HPPA_TRAP_PAGE_REFERENCE 21
143	#define HPPA_TRAP_DATA_DEBUG 31
144	#define HPPA_TRAP_ASSIST_EMULATION 22
145	/* group 4 */
146	#define HPPA_TRAP_HIGHER_PRIVILEGE_TRANSFER 23
147	#define HPPA_TRAP_LOWER_PRIVILEGE_TRANSFER 24
148	#define HPPA_TRAP_TAKEN_BRANCH 25
149
150	#define HPPA_INTERNAL_TRAPS 32
151
152	/* External Interrupts via interrupt 4 */
153
154	#define HPPA_INTERRUPT_EXTERNAL_0 0
155	#define HPPA_INTERRUPT_EXTERNAL_1 1
156	#define HPPA_INTERRUPT_EXTERNAL_2 2
157	#define HPPA_INTERRUPT_EXTERNAL_3 3
158	#define HPPA_INTERRUPT_EXTERNAL_4 4
159	#define HPPA_INTERRUPT_EXTERNAL_5 5
160	#define HPPA_INTERRUPT_EXTERNAL_6 6
161	#define HPPA_INTERRUPT_EXTERNAL_7 7
162	#define HPPA_INTERRUPT_EXTERNAL_8 8
163	#define HPPA_INTERRUPT_EXTERNAL_9 9
164	#define HPPA_INTERRUPT_EXTERNAL_10 10
165	#define HPPA_INTERRUPT_EXTERNAL_11 11
166	#define HPPA_INTERRUPT_EXTERNAL_12 12
167	#define HPPA_INTERRUPT_EXTERNAL_13 13
168	#define HPPA_INTERRUPT_EXTERNAL_14 14
169	#define HPPA_INTERRUPT_EXTERNAL_15 15
170	#define HPPA_INTERRUPT_EXTERNAL_16 16
171	#define HPPA_INTERRUPT_EXTERNAL_17 17
172	#define HPPA_INTERRUPT_EXTERNAL_18 18
173	#define HPPA_INTERRUPT_EXTERNAL_19 19
174	#define HPPA_INTERRUPT_EXTERNAL_20 20
175	#define HPPA_INTERRUPT_EXTERNAL_21 21
176	#define HPPA_INTERRUPT_EXTERNAL_22 22
177	#define HPPA_INTERRUPT_EXTERNAL_23 23
178	#define HPPA_INTERRUPT_EXTERNAL_24 24
179	#define HPPA_INTERRUPT_EXTERNAL_25 25
180	#define HPPA_INTERRUPT_EXTERNAL_26 26
181	#define HPPA_INTERRUPT_EXTERNAL_27 27
182	#define HPPA_INTERRUPT_EXTERNAL_28 28
183	#define HPPA_INTERRUPT_EXTERNAL_29 29
184	#define HPPA_INTERRUPT_EXTERNAL_30 30
185	#define HPPA_INTERRUPT_EXTERNAL_31 31
186
187	#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
188	#define HPPA_EXTERNAL_INTERRUPTS 32
189
190	/* BSP defined interrupts begin here */
191
192	#define HPPA_INTERRUPT_MAX 32
193
194	/*
195	* Cache characteristics
196	*/
197
198	#define HPPA_CACHELINE_SIZE 32
199	#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
200
201	/*
202	* page size characteristics
203	*/
204
205	#define HPPA_PAGE_SIZE 4096
206	#define HPPA_PAGE_MASK (0xfffff000)
207
208
209	/*
210	* TLB characteristics
211	*
212	* Flags and Access Control layout for using TLB protection insertion
213	*
214	* 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
215	* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
216	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
217	* \|?\|?\|T\|D\|B\|type \|PL1\|Pl2\|U\| access id \|?\|
218	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
219	*
220	*/
221
222	/*
223	* Access rights (type + PL1 + PL2)
224	*/
225	#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */
226	#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */
227	#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */
228	#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */
229	#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */
230	#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */
231	#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */
232	#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */
233
234	/*
235	* Floating point status register definitions
236	*/
237
238	#define HPPA_FPSTATUS_ENABLE_I 0x00000001 /* inexact operation */
239	#define HPPA_FPSTATUS_ENABLE_U 0x00000002 /* underflow */
240	#define HPPA_FPSTATUS_ENABLE_O 0x00000004 /* overflow */
241	#define HPPA_FPSTATUS_ENABLE_Z 0x00000008 /* division by zero */
242	#define HPPA_FPSTATUS_ENABLE_V 0x00000010 /* invalid operation */
243	#define HPPA_FPSTATUS_D 0x00000020 /* denormalize as zero */
244	#define HPPA_FPSTATUS_T 0x00000040 /* delayed trap */
245	#define HPPA_FPSTATUS_RM_MASK 0x00000600 /* rounding mode */
246	#define HPPA_FPSTATUS_RM_SHIFT 9
247	#define HPPA_FPSTATUS_CQ_MASK 0x001FFC00 /* compare queue */
248	#define HPPA_FPSTATUS_CQ_SHIFT 13
249	#define HPPA_FPSTATUS_C 0x04000000 /* most recent ompare bit */
250	#define HPPA_FPSTATUS_FLAG_I 0x08000000 /* inexact */
251	#define HPPA_FPSTATUS_FLAG_U 0x10000000 /* underflow */
252	#define HPPA_FPSTATUS_FLAG_O 0x20000000 /* overflow */
253	#define HPPA_FPSTATUS_FLAG_Z 0x40000000 /* division by zero */
254	#define HPPA_FPSTATUS_FLAG_V 0x80000000 /* invalid operation */
255
256
257	/*
258	* Inline macros for misc. interesting opcodes
259	*/
260
261	/* generate a global label */
262	#define HPPA_ASM_LABEL(label) \
263	asm(".export " label ", ! .label " label);
264
265	/* Return From Interrupt RFI */
266	#define HPPA_ASM_RFI() asm volatile ("rfi")
267
268	/* Set System Mask SSM i,t */
269	#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
270	: "=r" (gr) \
271	: "i" (i))
272	/* Reset System Mask RSM i,t */
273	#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
274	: "=r" (gr) \
275	: "i" (i))
276	/* Move To System Mask MTSM r */
277	#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
278	: : "r" (gr))
279
280	/* Load Space Identifier LDSID (s,b),t */
281	#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
282	: "=r" (grt) \
283	: "i" (sr), \
284	"r" (grb))
285
286	/*
287	* Gcc extended asm doesn't really allow for treatment of space registers
288	* as "registers", so we have to use "i" format.
289	* Unfortunately this means that the "=" constraint is not available.
290	*/
291
292	/* Move To Space Register MTSP r,sr */
293	#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
294	: : "i" (sr), \
295	"r" (gr))
296
297	/* Move From Space Register MFSP sr,t */
298	#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
299	: "=r" (gr) \
300	: "i" (sr))
301
302	/* Move To Control register MTCTL r,t */
303	#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
304	: : "i" (cr), \
305	"r" (gr))
306
307	/* Move From Control register MFCTL r,t */
308	#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
309	: "=r" (gr) \
310	: "i" (cr))
311
312	/* Synchronize caches SYNC */
313	#define HPPA_ASM_SYNC() asm volatile ("sync")
314
315	/* Probe Read Access PROBER (s,b),r,t */
316	#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
317	asm volatile ("prober (%1,%2),%3,%0" \
318	: "=r" (grt) \
319	: "i" (sr), \
320	"r" (groff), \
321	"r" (gracc))
322
323	/* Probe Read Access Immediate PROBERI (s,b),i,t*/
324	#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
325	asm volatile ("proberi (%1,%2),%3,%0" \
326	: "=r" (grt) \
327	: "i" (sr), \
328	"r" (groff), \
329	"i" (iacc))
330
331	/* Probe Write Access PROBEW (s,b),r,t */
332	#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
333	asm volatile ("probew (%1,%2),%3,%0" \
334	: "=r" (grt) \
335	: "i" (sr), \
336	"r" (groff), \
337	"r" (gracc))
338
339	/* Probe Write Access Immediate PROBEWI (s,b),i,t */
340	#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
341	asm volatile ("probewi (%1,%2),%3,%0" \
342	: "=r" (grt) \
343	: "i" (sr), \
344	"r" (groff), \
345	"i" (iacc))
346
347	/* Load Physical Address LPA x(s,b),t */
348	#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
349	: "=r" (grt) \
350	: "i" (sr), \
351	"r" (grb))
352
353	/* Load Coherence Index LCI x(s,b),t */
354	/* AKA: Load Hash Address LHA x(s,b),t */
355	#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
356	: "=r" (grt) \
357	: "r" (grx),\
358	"i" (sr), \
359	"r" (grb))
360	#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
361
362	/* Purge Data Tlb PDTLB x(s,b) */
363	#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
364	: : "r" (grx), \
365	"i" (sr), \
366	"r" (grb))
367
368	/* Purge Instruction Tlb PITLB x(s,b) */
369	#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
370	: : "r" (grx), \
371	"i" (sr), \
372	"r" (grb))
373
374	/* Purge Data Tlb Entry PDTLBE x(s,b) */
375	#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
376	: : "r" (grx), \
377	"i" (sr), \
378	"r" (grb))
379
380	/* Purge Instruction Tlb Entry PITLBE x(s,b) */
381	#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
382	: : "r" (grx), \
383	"i" (sr), \
384	"r" (grb))
385
386
387	/* Insert Data TLB Address IDTLBA r,(s,b) */
388	#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
389	: : "r" (gr), \
390	"i" (sr), \
391	"r" (grb))
392
393	/* Insert Instruction TLB Address IITLBA r,(s,b) */
394	#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
395	: : "r" (gr), \
396	"i" (sr), \
397	"r" (grb))
398
399	/* Insert Data TLB Protection IDTLBP r,(s,b) */
400	#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
401	: : "r" (gr), \
402	"i" (sr), \
403	"r" (grb))
404
405	/* Insert Instruction TLB Protection IITLBP r,(s,b) */
406	#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
407	: : "r" (gr), \
408	"i" (sr), \
409	"r" (grb))
410
411	/* Purge Data Cache PDC x(s,b) */
412	#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
413	: : "r" (grx), \
414	"i" (sr), \
415	"r" (grb))
416
417	/* Flush Data Cache FDC x(s,b) */
418	#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
419	: : "r" (grx), \
420	"i" (sr), \
421	"r" (grb))
422
423	/* Flush Instruction Cache FDC x(s,b) */
424	#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
425	: : "r" (grx), \
426	"i" (sr), \
427	"r" (grb))
428
429	/* Flush Data Cache Entry FDCE x(s,b) */
430	#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
431	: : "r" (grx), \
432	"i" (sr), \
433	"r" (grb))
434
435	/* Flush Instruction Cache Entry FICE x(s,b) */
436	#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
437	: : "r" (grx), \
438	"i" (sr), \
439	"r" (grb))
440
441	/* Break BREAK i5,i13 */
442	#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
443	: : "i" (i5), \
444	"i" (i13))
445
446	/* Load and Clear Word Short LDCWS d(s,b),t */
447	#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
448	: "=r" (grt) \
449	: "i" (i), \
450	"i" (sr), \
451	"r" (grb))
452
453	/* Load and Clear Word Indexed LDCWX x(s,b),t */
454	#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
455	: "=r" (grt) \
456	: "r" (grx), \
457	"i" (sr), \
458	"r" (grb))
459
460	/* Load Word Absolute Short LDWAS d(b),t */
461	/* NOTE: "short" here means "short displacement" */
462	#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
463	: "=r" (gr) \
464	: "i" (disp), \
465	"r" (grbase))
466
467	/* Store Word Absolute Short STWAS r,d(b) */
468	/* NOTE: "short" here means "short displacement" */
469	#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
470	: : "r" (gr), \
471	"i" (disp), \
472	"r" (grbase))
473
474	/*
475	* Swap bytes
476	* REFERENCE: PA72000 TRM -- Appendix C
477	*/
478	#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
479	" shd %1,%1,16,%0 \n\
480	dep %0,15,8,%0 \n\
481	shd %1,%0,8,%0" \
482	: "=r" (swapped) \
483	: "r" (value) \
484	)
485
486
487	/* 72000 Diagnose instructions follow
488	* These macros assume gas knows about these instructions.
489	* gas2.2.u1 did not.
490	* I added them to my copy and installed it locally.
491	*
492	* There are very special requirements for these guys
493	* ref: TRM 6.1.3 Programming Constraints
494	*
495	* The macros below handle the following rules
496	*
497	* Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
498	* Must never be nullified (hence the leading nop)
499	* NOP must preced every RDD,RDT,WDD,WDT,RDTLB
500	* Instruction preceeding GR_SHDW must not set any of the GR's saved
501	*
502	* The macros do NOT deal with the following problems
503	* doubled DIAGNOSE instructions must not straddle a page boundary
504	* if code translation enabled. (since 2nd could trap on ITLB)
505	* If you care about DHIT and DPE bits of DR0, then
506	* No store instruction in the 2 insn window before RDD
507	*/
508
509
510	/* Move To CPU/DIAG register MTCPU r,t */
511	#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
512	" mtcpu %1,%0 \n" \
513	" mtcpu %1,%0" \
514	: : "i" (dr), \
515	"r" (gr))
516
517	/* Move From CPU/DIAG register MFCPU r,t */
518	#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
519	" mfcpu %1,%0\n" \
520	" mfcpu %1,%0" \
521	: "=r" (gr) \
522	: "i" (dr))
523
524	/* Transfer of Control Enable TOC_EN */
525	#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
526	" tocen")
527
528	/* Transfer of Control Disable TOC_DIS */
529	#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
530	" tocdis")
531
532	/* Shadow Registers to General Register SHDW_GR */
533	#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
534	" shdwgr" \
535	::: "r1" "r8" "r9" "r16" \
536	"r17" "r24" "r25")
537
538	/* General Registers to Shadow Register GR_SHDW */
539	#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
540	" grshdw \n" \
541	" grshdw")
542
543	/*
544	* Definitions of special registers for use by the above macros.
545	*/
546
547	/* Hardware Space Registers */
548	#define HPPA_SR0 0
549	#define HPPA_SR1 1
550	#define HPPA_SR2 2
551	#define HPPA_SR3 3
552	#define HPPA_SR4 4
553	#define HPPA_SR5 5
554	#define HPPA_SR6 6
555	#define HPPA_SR7 7
556
557	/* Hardware Control Registers */
558	#define HPPA_CR0 0
559	#define HPPA_RCTR 0 /* Recovery Counter Register */
560
561	#define HPPA_CR8 8 /* Protection ID 1 */
562	#define HPPA_PIDR1 8
563
564	#define HPPA_CR9 9 /* Protection ID 2 */
565	#define HPPA_PIDR2 9
566
567	#define HPPA_CR10 10
568	#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
569
570	#define HPPA_CR11 11
571	#define HPPA_SAR 11 /* Shift Amount Register */
572
573	#define HPPA_CR12 12
574	#define HPPA_PIDR3 12 /* Protection ID 3 */
575
576	#define HPPA_CR13 13
577	#define HPPA_PIDR4 13 /* Protection ID 4 */
578
579	#define HPPA_CR14 14
580	#define HPPA_IVA 14 /* Interrupt Vector Address */
581
582	#define HPPA_CR15 15
583	#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
584
585	#define HPPA_CR16 16
586	#define HPPA_ITMR 16 /* Interval Timer */
587
588	#define HPPA_CR17 17
589	#define HPPA_PCSQ 17 /* Program Counter Space queue */
590
591	#define HPPA_CR18 18
592	#define HPPA_PCOQ 18 /* Program Counter Offset queue */
593
594	#define HPPA_CR19 19
595	#define HPPA_IIR 19 /* Interruption Instruction Register */
596
597	#define HPPA_CR20 20
598	#define HPPA_ISR 20 /* Interruption Space Register */
599
600	#define HPPA_CR21 21
601	#define HPPA_IOR 21 /* Interruption Offset Register */
602
603	#define HPPA_CR22 22
604	#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
605
606	#define HPPA_CR23 23
607	#define HPPA_EIRR 23 /* External Interrupt Request */
608
609	#define HPPA_CR24 24
610	#define HPPA_PPDA 24 /* Physcial Page Directory Address */
611	#define HPPA_TR0 24 /* Temporary register 0 */
612
613	#define HPPA_CR25 25
614	#define HPPA_HTA 25 /* Hash Table Address */
615	#define HPPA_TR1 25 /* Temporary register 1 */
616
617	#define HPPA_CR26 26
618	#define HPPA_TR2 26 /* Temporary register 2 */
619
620	#define HPPA_CR27 27
621	#define HPPA_TR3 27 /* Temporary register 3 */
622
623	#define HPPA_CR28 28
624	#define HPPA_TR4 28 /* Temporary register 4 */
625
626	#define HPPA_CR29 29
627	#define HPPA_TR5 29 /* Temporary register 5 */
628
629	#define HPPA_CR30 30
630	#define HPPA_TR6 30 /* Temporary register 6 */
631
632	#define HPPA_CR31 31
633	#define HPPA_CPUID 31 /* MP identifier */
634
635	/*
636	* Diagnose registers
637	*/
638
639	#define HPPA_DR0 0
640	#define HPPA_DR1 1
641	#define HPPA_DR8 8
642	#define HPPA_DR24 24
643	#define HPPA_DR25 25
644
645	/*
646	* Tear apart a break instruction to find its type.
647	*/
648	#define HPPA_BREAK5(x) ((x) & 0x1F)
649	#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
650
651	/* assemble a break instruction */
652	#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) \| (((i13) & 0x1FFF) << 13))
653
654
655	/*
656	* this won't work in ASM or non-GNU compilers
657	*/
658
659	#if !defined(ASM) && defined(__GNUC__)
660
661	/*
662	* static inline utility functions to get at control registers
663	*/
664
665	#define EMIT_GET_CONTROL(name, reg) \
666	static __inline__ unsigned int \
667	get_ ## name (void) \
668	{ \
669	unsigned int value; \
670	HPPA_ASM_MFCTL(reg, value); \
671	return value; \
672	}
673
674	#define EMIT_SET_CONTROL(name, reg) \
675	static __inline__ void \
676	set_ ## name (unsigned int new_value) \
677	{ \
678	HPPA_ASM_MTCTL(new_value, reg); \
679	}
680
681	#define EMIT_CONTROLS(name, reg) \
682	EMIT_GET_CONTROL(name, reg) \
683	EMIT_SET_CONTROL(name, reg)
684
685	EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
686	EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
687	EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
688	EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
689	EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
690	EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
691	EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
692	EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
693	EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
694	EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
695	EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
696	EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
697	EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
698	EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
699	EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
700	EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
701	EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
702	EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
703	EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
704	EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
705	EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
706	EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
707	EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
708	EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
709	EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
710	EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
711
712	#endif /* ASM and GNU */
713
714	/*
715	* If and How to invoke the debugger (a ROM debugger generally)
716	*/
717	#define CPU_INVOKE_DEBUGGER \
718	do { \
719	HPPA_ASM_BREAK(1,1); \
720	} while (0)
721
722	#ifdef __cplusplus
723	}
724	#endif
725
726	#endif /* ! _INCLUDE_HPPA_H */
727

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