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source: rtems/c/src/exec/score/cpu/hppa1.1/hppa.h @ d0b7c4e6

4.104.114.84.95

Last change on this file since d0b7c4e6 was d0b7c4e6, checked in by Joel Sherrill <joel.sherrill@…>, on 04/22/96 at 16:30:02
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1	/*
2	* Description:
3	*
4	* Definitions for HP PA Risc
5	* ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
6	*
7	* COPYRIGHT (c) 1994 by Division Incorporated
8	*
9	* To anyone who acknowledges that this file is provided "AS IS"
10	* without any express or implied warranty:
11	* permission to use, copy, modify, and distribute this file
12	* for any purpose is hereby granted without fee, provided that
13	* the above copyright notice and this notice appears in all
14	* copies, and that the name of Division Incorporated not be
15	* used in advertising or publicity pertaining to distribution
16	* of the software without specific, written prior permission.
17	* Division Incorporated makes no representations about the
18	* suitability of this software for any purpose.
19	*
20	*
21	* Note:
22	* This file is included by both C and assembler code ( -DASM )
23	*
24	* $Id$
25	*/
26
27	#ifndef _INCLUDE_HPPA_H
28	#define _INCLUDE_HPPA_H
29
30	#if defined(__cplusplus)
31	extern "C" {
32	#endif
33
34	/*
35	* The following define the CPU Family and Model within the family
36	*
37	* NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
38	* with the name of the appropriate macro for this target CPU.
39	*/
40
41	#ifdef hppa1_1
42	#undef hppa1_1
43	#endif
44	#define hppa1_1
45
46	#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
47	#undef REPLACE_THIS_WITH_THE_CPU_MODEL
48	#endif
49	#define REPLACE_THIS_WITH_THE_CPU_MODEL
50
51	#ifdef REPLACE_THIS_WITH_THE_BSP
52	#undef REPLACE_THIS_WITH_THE_BSP
53	#endif
54	#define REPLACE_THIS_WITH_THE_BSP
55
56	/*
57	* This section contains the information required to build
58	* RTEMS for a particular member of the Hewlett Packard
59	* PA-RISC family. It does this by setting variables to
60	* indicate which implementation dependent features are
61	* present in a particular member of the family.
62	*/
63
64	#if !defined(CPU_MODEL_NAME)
65
66	#if defined(hppa7100)
67
68	#define CPU_MODEL_NAME "hppa 7100"
69
70	#elif defined(hppa7200)
71
72	#define CPU_MODEL_NAME "hppa 7200"
73
74	#else
75
76	#define CPU_MODEL_NAME Unsupported CPU Model /* cause an error on usage */
77
78	#endif
79
80	#endif /* !defined(CPU_MODEL_NAME) */
81
82	/*
83	* Define the name of the CPU family.
84	*/
85
86	#if !defined(CPU_NAME)
87	#define CPU_NAME "HP PA-RISC 1.1"
88	#endif
89
90	/*
91	* Processor Status Word (PSW) Masks
92	*/
93
94	#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
95	#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
96	#define HPPA_PSW_r2 0x20000000 /* reserved */
97	#define HPPA_PSW_r3 0x10000000 /* reserved */
98	#define HPPA_PSW_r4 0x08000000 /* reserved */
99	#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
100	#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
101	#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
102	#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
103	#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
104	#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
105	#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
106	#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
107	#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
108	#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
109	#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
110	#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
111	#define HPPA_PSW_r24 0x00000080 /* reserved */
112	#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
113	#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
114	#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
115	#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
116	#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
117	#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
118	#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
119	/* Low-Priority Machine Check */
120	/* Interruption Enable */
121
122	/*
123	* HPPA traps and interrupts
124	* basic layout. Note numbers do not denote priority
125	*
126	* 0-31 basic traps and interrupts defined by HPPA architecture
127	* 32-63 32 external interrupts
128	* 64-... bsp defined
129	*/
130
131	#define HPPA_INTERRUPT_NON_EXISTENT 0
132	/* group 1 */
133	#define HPPA_INTERRUPT_HIGH_PRIORITY_MACHINE_CHECK 1
134	/* group 2 */
135	#define HPPA_INTERRUPT_POWER_FAIL 2
136	#define HPPA_INTERRUPT_RECOVERY_COUNTER 3
137	#define HPPA_INTERRUPT_EXTERNAL_INTERRUPT 4
138	#define HPPA_INTERRUPT_LOW_PRIORITY_MACHINE_CHECK 5
139	#define HPPA_INTERRUPT_PERFORMANCE_MONITOR 29
140	/* group 3 */
141	#define HPPA_INTERRUPT_INSTRUCTION_TLB_MISS 6
142	#define HPPA_INTERRUPT_INSTRUCTION_MEMORY_PROTECTION 7
143	#define HPPA_INTERRUPT_INSTRUCTION_DEBUG 30
144	#define HPPA_INTERRUPT_ILLEGAL_INSTRUCTION 8
145	#define HPPA_INTERRUPT_BREAK_INSTRUCTION 9
146	#define HPPA_INTERRUPT_PRIVILEGED_OPERATION 10
147	#define HPPA_INTERRUPT_PRIVILEGED_REGISTER 11
148	#define HPPA_INTERRUPT_OVERFLOW 12
149	#define HPPA_INTERRUPT_CONDITIONAL 13
150	#define HPPA_INTERRUPT_ASSIST_EXCEPTION 14
151	#define HPPA_INTERRUPT_DATA_TLB_MISS 15
152	#define HPPA_INTERRUPT_NON_ACCESS_INSTRUCTION_TLB_MISS 16
153	#define HPPA_INTERRUPT_NON_ACCESS_DATA_TLB_MISS 17
154	#define HPPA_INTERRUPT_DATA_MEMORY_ACCESS_RIGHTS 26
155	#define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION_ID 27
156	#define HPPA_INTERRUPT_UNALIGNED_DATA_REFERENCE 28
157	#define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION 18
158	#define HPPA_INTERRUPT_DATA_MEMORY_BREAK 19
159	#define HPPA_INTERRUPT_TLB_DIRTY_BIT 20
160	#define HPPA_INTERRUPT_PAGE_REFERENCE 21
161	#define HPPA_INTERRUPT_DATA_DEBUG 31
162	#define HPPA_INTERRUPT_ASSIST_EMULATION 22
163	/* group 4 */
164	#define HPPA_INTERRUPT_HIGHER_PRIVILEGE_TRANSFER 23
165	#define HPPA_INTERRUPT_LOWER_PRIVILEGE_TRANSFER 24
166	#define HPPA_INTERRUPT_TAKEN_BRANCH 25
167
168	#define HPPA_INTERRUPT_ON_CHIP_MAX 31
169
170	/* External Interrupts via interrupt 4 */
171
172	#define HPPA_INTERRUPT_EXTERNAL_BASE 32
173
174	#define HPPA_INTERRUPT_EXTERNAL_0 32
175	#define HPPA_INTERRUPT_EXTERNAL_1 33
176	#define HPPA_INTERRUPT_EXTERNAL_2 34
177	#define HPPA_INTERRUPT_EXTERNAL_3 35
178	#define HPPA_INTERRUPT_EXTERNAL_4 36
179	#define HPPA_INTERRUPT_EXTERNAL_5 37
180	#define HPPA_INTERRUPT_EXTERNAL_6 38
181	#define HPPA_INTERRUPT_EXTERNAL_7 39
182	#define HPPA_INTERRUPT_EXTERNAL_8 40
183	#define HPPA_INTERRUPT_EXTERNAL_9 41
184	#define HPPA_INTERRUPT_EXTERNAL_10 42
185	#define HPPA_INTERRUPT_EXTERNAL_11 43
186	#define HPPA_INTERRUPT_EXTERNAL_12 44
187	#define HPPA_INTERRUPT_EXTERNAL_13 45
188	#define HPPA_INTERRUPT_EXTERNAL_14 46
189	#define HPPA_INTERRUPT_EXTERNAL_15 47
190	#define HPPA_INTERRUPT_EXTERNAL_16 48
191	#define HPPA_INTERRUPT_EXTERNAL_17 49
192	#define HPPA_INTERRUPT_EXTERNAL_18 50
193	#define HPPA_INTERRUPT_EXTERNAL_19 51
194	#define HPPA_INTERRUPT_EXTERNAL_20 52
195	#define HPPA_INTERRUPT_EXTERNAL_21 53
196	#define HPPA_INTERRUPT_EXTERNAL_22 54
197	#define HPPA_INTERRUPT_EXTERNAL_23 55
198	#define HPPA_INTERRUPT_EXTERNAL_24 56
199	#define HPPA_INTERRUPT_EXTERNAL_25 57
200	#define HPPA_INTERRUPT_EXTERNAL_26 58
201	#define HPPA_INTERRUPT_EXTERNAL_27 59
202	#define HPPA_INTERRUPT_EXTERNAL_28 60
203	#define HPPA_INTERRUPT_EXTERNAL_29 61
204	#define HPPA_INTERRUPT_EXTERNAL_30 62
205	#define HPPA_INTERRUPT_EXTERNAL_31 63
206
207	#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
208	#define HPPA_EXTERNAL_INTERRUPTS 32
209	#define HPPA_INTERNAL_INTERRUPTS 32
210
211	/* BSP defined interrupts begin here */
212
213	#define HPPA_INTERRUPT_MAX 64
214
215	/*
216	* Cache characteristics
217	*/
218
219	#define HPPA_CACHELINE_SIZE 32
220	#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
221
222
223	/*
224	* TLB characteristics
225	*
226	* Flags and Access Control layout for using TLB protection insertion
227	*
228	* 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
229	* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
230	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
231	* \|?\|?\|T\|D\|B\|type \|PL1\|Pl2\|U\| access id \|?\|
232	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
233	*
234	*/
235
236	/*
237	* Access rights (type + PL1 + PL2)
238	*/
239	#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */
240	#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */
241	#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */
242	#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */
243	#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */
244	#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */
245	#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */
246	#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */
247
248
249	/*
250	* Inline macros for misc. interesting opcodes
251	*/
252
253	/* generate a global label */
254	#define HPPA_ASM_LABEL(label) \
255	asm(".export " label ", ! .label " label);
256
257	/* Return From Interrupt RFI */
258	#define HPPA_ASM_RFI() asm volatile ("rfi")
259
260	/* Set System Mask SSM i,t */
261	#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
262	: "=r" (gr) \
263	: "i" (i))
264	/* Reset System Mask RSM i,t */
265	#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
266	: "=r" (gr) \
267	: "i" (i))
268	/* Move To System Mask MTSM r */
269	#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
270	: : "r" (gr))
271
272	/* Load Space Identifier LDSID (s,b),t */
273	#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
274	: "=r" (grt) \
275	: "i" (sr), \
276	"r" (grb))
277
278	/*
279	* Gcc extended asm doesn't really allow for treatment of space registers
280	* as "registers", so we have to use "i" format.
281	* Unfortunately this means that the "=" constraint is not available.
282	*/
283
284	/* Move To Space Register MTSP r,sr */
285	#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
286	: : "i" (sr), \
287	"r" (gr))
288
289	/* Move From Space Register MFSP sr,t */
290	#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
291	: "=r" (gr) \
292	: "i" (sr))
293
294	/* Move To Control register MTCTL r,t */
295	#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
296	: : "i" (cr), \
297	"r" (gr))
298
299	/* Move From Control register MFCTL r,t */
300	#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
301	: "=r" (gr) \
302	: "i" (cr))
303
304	/* Synchronize caches SYNC */
305	#define HPPA_ASM_SYNC() asm volatile ("sync")
306
307	/* Probe Read Access PROBER (s,b),r,t */
308	#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
309	asm volatile ("prober (%1,%2),%3,%0" \
310	: "=r" (grt) \
311	: "i" (sr), \
312	"r" (groff), \
313	"r" (gracc))
314
315	/* Probe Read Access Immediate PROBERI (s,b),i,t*/
316	#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
317	asm volatile ("proberi (%1,%2),%3,%0" \
318	: "=r" (grt) \
319	: "i" (sr), \
320	"r" (groff), \
321	"i" (iacc))
322
323	/* Probe Write Access PROBEW (s,b),r,t */
324	#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
325	asm volatile ("probew (%1,%2),%3,%0" \
326	: "=r" (grt) \
327	: "i" (sr), \
328	"r" (groff), \
329	"r" (gracc))
330
331	/* Probe Write Access Immediate PROBEWI (s,b),i,t */
332	#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
333	asm volatile ("probewi (%1,%2),%3,%0" \
334	: "=r" (grt) \
335	: "i" (sr), \
336	"r" (groff), \
337	"i" (iacc))
338
339	/* Load Physical Address LPA x(s,b),t */
340	#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
341	: "=r" (grt) \
342	: "i" (sr), \
343	"r" (grb))
344
345	/* Load Coherence Index LCI x(s,b),t */
346	/* AKA: Load Hash Address LHA x(s,b),t */
347	#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
348	: "=r" (grt) \
349	: "r" (grx),\
350	"i" (sr), \
351	"r" (grb))
352	#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
353
354	/* Purge Data Tlb PDTLB x(s,b) */
355	#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
356	: : "r" (grx), \
357	"i" (sr), \
358	"r" (grb))
359
360	/* Purge Instruction Tlb PITLB x(s,b) */
361	#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
362	: : "r" (grx), \
363	"i" (sr), \
364	"r" (grb))
365
366	/* Purge Data Tlb Entry PDTLBE x(s,b) */
367	#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
368	: : "r" (grx), \
369	"i" (sr), \
370	"r" (grb))
371
372	/* Purge Instruction Tlb Entry PITLBE x(s,b) */
373	#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
374	: : "r" (grx), \
375	"i" (sr), \
376	"r" (grb))
377
378
379	/* Insert Data TLB Address IDTLBA r,(s,b) */
380	#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
381	: : "r" (gr), \
382	"i" (sr), \
383	"r" (grb))
384
385	/* Insert Instruction TLB Address IITLBA r,(s,b) */
386	#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
387	: : "r" (gr), \
388	"i" (sr), \
389	"r" (grb))
390
391	/* Insert Data TLB Protection IDTLBP r,(s,b) */
392	#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
393	: : "r" (gr), \
394	"i" (sr), \
395	"r" (grb))
396
397	/* Insert Instruction TLB Protection IITLBP r,(s,b) */
398	#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
399	: : "r" (gr), \
400	"i" (sr), \
401	"r" (grb))
402
403	/* Purge Data Cache PDC x(s,b) */
404	#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
405	: : "r" (grx), \
406	"i" (sr), \
407	"r" (grb))
408
409	/* Flush Data Cache FDC x(s,b) */
410	#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
411	: : "r" (grx), \
412	"i" (sr), \
413	"r" (grb))
414
415	/* Flush Instruction Cache FDC x(s,b) */
416	#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
417	: : "r" (grx), \
418	"i" (sr), \
419	"r" (grb))
420
421	/* Flush Data Cache Entry FDCE x(s,b) */
422	#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
423	: : "r" (grx), \
424	"i" (sr), \
425	"r" (grb))
426
427	/* Flush Instruction Cache Entry FICE x(s,b) */
428	#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
429	: : "r" (grx), \
430	"i" (sr), \
431	"r" (grb))
432
433	/* Break BREAK i5,i13 */
434	#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
435	: : "i" (i5), \
436	"i" (i13))
437
438	/* Load and Clear Word Short LDCWS d(s,b),t */
439	#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
440	: "=r" (grt) \
441	: "i" (i), \
442	"i" (sr), \
443	"r" (grb))
444
445	/* Load and Clear Word Indexed LDCWX x(s,b),t */
446	#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
447	: "=r" (grt) \
448	: "r" (grx), \
449	"i" (sr), \
450	"r" (grb))
451
452	/* Load Word Absolute Short LDWAS d(b),t */
453	/* NOTE: "short" here means "short displacement" */
454	#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
455	: "=r" (gr) \
456	: "i" (disp), \
457	"r" (grbase))
458
459	/* Store Word Absolute Short STWAS r,d(b) */
460	/* NOTE: "short" here means "short displacement" */
461	#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
462	: : "r" (gr), \
463	"i" (disp), \
464	"r" (grbase))
465
466	/*
467	* Swap bytes
468	* REFERENCE: PA72000 TRM -- Appendix C
469	*/
470	#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
471	" shd %1,%1,16,%0 \n\
472	dep %0,15,8,%0 \n\
473	shd %1,%0,8,%0" \
474	: "=r" (swapped) \
475	: "r" (value) \
476	)
477
478
479	/* 72000 Diagnose instructions follow
480	* These macros assume gas knows about these instructions.
481	* gas2.2.u1 did not.
482	* I added them to my copy and installed it locally.
483	*
484	* There are very special requirements for these guys
485	* ref: TRM 6.1.3 Programming Constraints
486	*
487	* The macros below handle the following rules
488	*
489	* Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
490	* Must never be nullified (hence the leading nop)
491	* NOP must preced every RDD,RDT,WDD,WDT,RDTLB
492	* Instruction preceeding GR_SHDW must not set any of the GR's saved
493	*
494	* The macros do NOT deal with the following problems
495	* doubled DIAGNOSE instructions must not straddle a page boundary
496	* if code translation enabled. (since 2nd could trap on ITLB)
497	* If you care about DHIT and DPE bits of DR0, then
498	* No store instruction in the 2 insn window before RDD
499	*/
500
501
502	/* Move To CPU/DIAG register MTCPU r,t */
503	#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
504	" mtcpu %1,%0 \n" \
505	" mtcpu %1,%0" \
506	: : "i" (dr), \
507	"r" (gr))
508
509	/* Move From CPU/DIAG register MFCPU r,t */
510	#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
511	" mfcpu %1,%0\n" \
512	" mfcpu %1,%0" \
513	: "=r" (gr) \
514	: "i" (dr))
515
516	/* Transfer of Control Enable TOC_EN */
517	#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
518	" tocen")
519
520	/* Transfer of Control Disable TOC_DIS */
521	#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
522	" tocdis")
523
524	/* Shadow Registers to General Register SHDW_GR */
525	#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
526	" shdwgr" \
527	::: "r1" "r8" "r9" "r16" \
528	"r17" "r24" "r25")
529
530	/* General Registers to Shadow Register GR_SHDW */
531	#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
532	" grshdw \n" \
533	" grshdw")
534
535	/*
536	* Definitions of special registers for use by the above macros.
537	*/
538
539	/* Hardware Space Registers */
540	#define HPPA_SR0 0
541	#define HPPA_SR1 1
542	#define HPPA_SR2 2
543	#define HPPA_SR3 3
544	#define HPPA_SR4 4
545	#define HPPA_SR5 5
546	#define HPPA_SR6 6
547	#define HPPA_SR7 7
548
549	/* Hardware Control Registers */
550	#define HPPA_CR0 0
551	#define HPPA_RCTR 0 /* Recovery Counter Register */
552
553	#define HPPA_CR8 8 /* Protection ID 1 */
554	#define HPPA_PIDR1 8
555
556	#define HPPA_CR9 9 /* Protection ID 2 */
557	#define HPPA_PIDR2 9
558
559	#define HPPA_CR10 10
560	#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
561
562	#define HPPA_CR11 11
563	#define HPPA_SAR 11 /* Shift Amount Register */
564
565	#define HPPA_CR12 12
566	#define HPPA_PIDR3 12 /* Protection ID 3 */
567
568	#define HPPA_CR13 13
569	#define HPPA_PIDR4 13 /* Protection ID 4 */
570
571	#define HPPA_CR14 14
572	#define HPPA_IVA 14 /* Interrupt Vector Address */
573
574	#define HPPA_CR15 15
575	#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
576
577	#define HPPA_CR16 16
578	#define HPPA_ITMR 16 /* Interval Timer */
579
580	#define HPPA_CR17 17
581	#define HPPA_PCSQ 17 /* Program Counter Space queue */
582
583	#define HPPA_CR18 18
584	#define HPPA_PCOQ 18 /* Program Counter Offset queue */
585
586	#define HPPA_CR19 19
587	#define HPPA_IIR 19 /* Interruption Instruction Register */
588
589	#define HPPA_CR20 20
590	#define HPPA_ISR 20 /* Interruption Space Register */
591
592	#define HPPA_CR21 21
593	#define HPPA_IOR 21 /* Interruption Offset Register */
594
595	#define HPPA_CR22 22
596	#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
597
598	#define HPPA_CR23 23
599	#define HPPA_EIRR 23 /* External Interrupt Request */
600
601	#define HPPA_CR24 24
602	#define HPPA_PPDA 24 /* Physcial Page Directory Address */
603	#define HPPA_TR0 24 /* Temporary register 0 */
604
605	#define HPPA_CR25 25
606	#define HPPA_HTA 25 /* Hash Table Address */
607	#define HPPA_TR1 25 /* Temporary register 1 */
608
609	#define HPPA_CR26 26
610	#define HPPA_TR2 26 /* Temporary register 2 */
611
612	#define HPPA_CR27 27
613	#define HPPA_TR3 27 /* Temporary register 3 */
614
615	#define HPPA_CR28 28
616	#define HPPA_TR4 28 /* Temporary register 4 */
617
618	#define HPPA_CR29 29
619	#define HPPA_TR5 29 /* Temporary register 5 */
620
621	#define HPPA_CR30 30
622	#define HPPA_TR6 30 /* Temporary register 6 */
623
624	#define HPPA_CR31 31
625	#define HPPA_CPUID 31 /* MP identifier */
626
627	/*
628	* Diagnose registers
629	*/
630
631	#define HPPA_DR0 0
632	#define HPPA_DR1 1
633	#define HPPA_DR8 8
634	#define HPPA_DR24 24
635	#define HPPA_DR25 25
636
637	/*
638	* Tear apart a break instruction to find its type.
639	*/
640	#define HPPA_BREAK5(x) ((x) & 0x1F)
641	#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
642
643	/* assemble a break instruction */
644	#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) \| (((i13) & 0x1FFF) << 13))
645
646
647	/*
648	* this won't work in ASM or non-GNU compilers
649	*/
650
651	#if !defined(ASM) && defined(__GNUC__)
652
653	/*
654	* static inline utility functions to get at control registers
655	*/
656
657	#define EMIT_GET_CONTROL(name, reg) \
658	static __inline__ unsigned int \
659	get_ ## name (void) \
660	{ \
661	unsigned int value; \
662	HPPA_ASM_MFCTL(reg, value); \
663	return value; \
664	}
665
666	#define EMIT_SET_CONTROL(name, reg) \
667	static __inline__ void \
668	set_ ## name (unsigned int new_value) \
669	{ \
670	HPPA_ASM_MTCTL(new_value, reg); \
671	}
672
673	#define EMIT_CONTROLS(name, reg) \
674	EMIT_GET_CONTROL(name, reg) \
675	EMIT_SET_CONTROL(name, reg)
676
677	EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
678	EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
679	EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
680	EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
681	EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
682	EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
683	EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
684	EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
685	EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
686	EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
687	EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
688	EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
689	EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
690	EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
691	EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
692	EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
693	EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
694	EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
695	EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
696	EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
697	EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
698	EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
699	EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
700	EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
701	EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
702	EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
703
704	#endif /* ASM and GNU */
705
706	/*
707	* If and How to invoke the debugger (a ROM debugger generally)
708	*/
709	#define CPU_INVOKE_DEBUGGER \
710	do { \
711	HPPA_ASM_BREAK(1,1); \
712	} while (0)
713
714	#ifdef __cplusplus
715	}
716	#endif
717
718	#endif /* ! _INCLUDE_HPPA_H */
719

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