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source: rtems/c/src/exec/score/cpu/hppa1.1/hppa.h @ c64e4ed4

4.104.114.84.95

Last change on this file since c64e4ed4 was c64e4ed4, checked in by Joel Sherrill <joel.sherrill@…>, on 01/15/96 at 21:50:28
updates from Tony Bennett for PA and UNIX ports
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File size: 29.7 KB

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1	/*
2	* @(#)hppa.h 1.17 - 95/12/13
3	*
4	*
5	* Description:
6	*
7	* Definitions for HP PA Risc
8	* ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
9	*
10	* COPYRIGHT (c) 1994 by Division Incorporated
11	*
12	* To anyone who acknowledges that this file is provided "AS IS"
13	* without any express or implied warranty:
14	* permission to use, copy, modify, and distribute this file
15	* for any purpose is hereby granted without fee, provided that
16	* the above copyright notice and this notice appears in all
17	* copies, and that the name of Division Incorporated not be
18	* used in advertising or publicity pertaining to distribution
19	* of the software without specific, written prior permission.
20	* Division Incorporated makes no representations about the
21	* suitability of this software for any purpose.
22	*
23	*
24	* Note:
25	* This file is included by both C and assembler code ( -DASM )
26	*
27	* $Id$
28	*/
29
30	#ifndef _INCLUDE_HPPA_H
31	#define _INCLUDE_HPPA_H
32
33	#if defined(__cplusplus)
34	extern "C" {
35	#endif
36
37	/*
38	* The following define the CPU Family and Model within the family
39	*
40	* NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
41	* with the name of the appropriate macro for this target CPU.
42	*/
43
44	#ifdef hppa1_1
45	#undef hppa1_1
46	#endif
47	#define hppa1_1
48
49	#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
50	#undef REPLACE_THIS_WITH_THE_CPU_MODEL
51	#endif
52	#define REPLACE_THIS_WITH_THE_CPU_MODEL
53
54	#ifdef REPLACE_THIS_WITH_THE_BSP
55	#undef REPLACE_THIS_WITH_THE_BSP
56	#endif
57	#define REPLACE_THIS_WITH_THE_BSP
58
59	/*
60	* This section contains the information required to build
61	* RTEMS for a particular member of the Hewlett Packard
62	* PA-RISC family. It does this by setting variables to
63	* indicate which implementation dependent features are
64	* present in a particular member of the family.
65	*/
66
67	#if !defined(CPU_MODEL_NAME)
68
69	#if defined(hppa7100)
70
71	#define CPU_MODEL_NAME "hppa 7100"
72
73	#elif defined(hppa7200)
74
75	#define CPU_MODEL_NAME "hppa 7200"
76
77	#else
78
79	#define CPU_MODEL_NAME Unsupported CPU Model /* cause an error on usage */
80
81	#endif
82
83	#endif /* !defined(CPU_MODEL_NAME) */
84
85	/*
86	* Define the name of the CPU family.
87	*/
88
89	#if !defined(CPU_NAME)
90	#define CPU_NAME "HP PA-RISC 1.1"
91	#endif
92
93	/*
94	* Processor Status Word (PSW) Masks
95	*/
96
97	#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
98	#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
99	#define HPPA_PSW_r2 0x20000000 /* reserved */
100	#define HPPA_PSW_r3 0x10000000 /* reserved */
101	#define HPPA_PSW_r4 0x08000000 /* reserved */
102	#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
103	#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
104	#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
105	#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
106	#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
107	#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
108	#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
109	#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
110	#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
111	#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
112	#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
113	#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
114	#define HPPA_PSW_r24 0x00000080 /* reserved */
115	#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
116	#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
117	#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
118	#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
119	#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
120	#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
121	#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
122	/* Low-Priority Machine Check */
123	/* Interruption Enable */
124
125	/*
126	* HPPA traps and interrupts
127	* basic layout. Note numbers do not denote priority
128	*
129	* 0-31 basic traps and interrupts defined by HPPA architecture
130	* 32-63 32 external interrupts
131	* 64-... bsp defined
132	*/
133
134	#define HPPA_INTERRUPT_NON_EXISTENT 0
135	/* group 1 */
136	#define HPPA_INTERRUPT_HIGH_PRIORITY_MACHINE_CHECK 1
137	/* group 2 */
138	#define HPPA_INTERRUPT_POWER_FAIL 2
139	#define HPPA_INTERRUPT_RECOVERY_COUNTER 3
140	#define HPPA_INTERRUPT_EXTERNAL_INTERRUPT 4
141	#define HPPA_INTERRUPT_LOW_PRIORITY_MACHINE_CHECK 5
142	#define HPPA_INTERRUPT_PERFORMANCE_MONITOR 29
143	/* group 3 */
144	#define HPPA_INTERRUPT_INSTRUCTION_TLB_MISS 6
145	#define HPPA_INTERRUPT_INSTRUCTION_MEMORY_PROTECTION 7
146	#define HPPA_INTERRUPT_INSTRUCTION_DEBUG 30
147	#define HPPA_INTERRUPT_ILLEGAL_INSTRUCTION 8
148	#define HPPA_INTERRUPT_BREAK_INSTRUCTION 9
149	#define HPPA_INTERRUPT_PRIVILEGED_OPERATION 10
150	#define HPPA_INTERRUPT_PRIVILEGED_REGISTER 11
151	#define HPPA_INTERRUPT_OVERFLOW 12
152	#define HPPA_INTERRUPT_CONDITIONAL 13
153	#define HPPA_INTERRUPT_ASSIST_EXCEPTION 14
154	#define HPPA_INTERRUPT_DATA_TLB_MISS 15
155	#define HPPA_INTERRUPT_NON_ACCESS_INSTRUCTION_TLB_MISS 16
156	#define HPPA_INTERRUPT_NON_ACCESS_DATA_TLB_MISS 17
157	#define HPPA_INTERRUPT_DATA_MEMORY_ACCESS_RIGHTS 26
158	#define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION_ID 27
159	#define HPPA_INTERRUPT_UNALIGNED_DATA_REFERENCE 28
160	#define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION 18
161	#define HPPA_INTERRUPT_DATA_MEMORY_BREAK 19
162	#define HPPA_INTERRUPT_TLB_DIRTY_BIT 20
163	#define HPPA_INTERRUPT_PAGE_REFERENCE 21
164	#define HPPA_INTERRUPT_DATA_DEBUG 31
165	#define HPPA_INTERRUPT_ASSIST_EMULATION 22
166	/* group 4 */
167	#define HPPA_INTERRUPT_HIGHER_PRIVILEGE_TRANSFER 23
168	#define HPPA_INTERRUPT_LOWER_PRIVILEGE_TRANSFER 24
169	#define HPPA_INTERRUPT_TAKEN_BRANCH 25
170
171	#define HPPA_INTERRUPT_ON_CHIP_MAX 31
172
173	/* External Interrupts via interrupt 4 */
174
175	#define HPPA_INTERRUPT_EXTERNAL_BASE 32
176
177	#define HPPA_INTERRUPT_EXTERNAL_0 32
178	#define HPPA_INTERRUPT_EXTERNAL_1 33
179	#define HPPA_INTERRUPT_EXTERNAL_2 34
180	#define HPPA_INTERRUPT_EXTERNAL_3 35
181	#define HPPA_INTERRUPT_EXTERNAL_4 36
182	#define HPPA_INTERRUPT_EXTERNAL_5 37
183	#define HPPA_INTERRUPT_EXTERNAL_6 38
184	#define HPPA_INTERRUPT_EXTERNAL_7 39
185	#define HPPA_INTERRUPT_EXTERNAL_8 40
186	#define HPPA_INTERRUPT_EXTERNAL_9 41
187	#define HPPA_INTERRUPT_EXTERNAL_10 42
188	#define HPPA_INTERRUPT_EXTERNAL_11 43
189	#define HPPA_INTERRUPT_EXTERNAL_12 44
190	#define HPPA_INTERRUPT_EXTERNAL_13 45
191	#define HPPA_INTERRUPT_EXTERNAL_14 46
192	#define HPPA_INTERRUPT_EXTERNAL_15 47
193	#define HPPA_INTERRUPT_EXTERNAL_16 48
194	#define HPPA_INTERRUPT_EXTERNAL_17 49
195	#define HPPA_INTERRUPT_EXTERNAL_18 50
196	#define HPPA_INTERRUPT_EXTERNAL_19 51
197	#define HPPA_INTERRUPT_EXTERNAL_20 52
198	#define HPPA_INTERRUPT_EXTERNAL_21 53
199	#define HPPA_INTERRUPT_EXTERNAL_22 54
200	#define HPPA_INTERRUPT_EXTERNAL_23 55
201	#define HPPA_INTERRUPT_EXTERNAL_24 56
202	#define HPPA_INTERRUPT_EXTERNAL_25 57
203	#define HPPA_INTERRUPT_EXTERNAL_26 58
204	#define HPPA_INTERRUPT_EXTERNAL_27 59
205	#define HPPA_INTERRUPT_EXTERNAL_28 60
206	#define HPPA_INTERRUPT_EXTERNAL_29 61
207	#define HPPA_INTERRUPT_EXTERNAL_30 62
208	#define HPPA_INTERRUPT_EXTERNAL_31 63
209
210	#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
211	#define HPPA_EXTERNAL_INTERRUPTS 32
212	#define HPPA_INTERNAL_INTERRUPTS 32
213
214	/* BSP defined interrupts begin here */
215
216	#define HPPA_INTERRUPT_MAX 64
217
218	/*
219	* Cache characteristics
220	*/
221
222	#define HPPA_CACHELINE_SIZE 32
223	#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
224
225
226	/*
227	* TLB characteristics
228	*
229	* Flags and Access Control layout for using TLB protection insertion
230	*
231	* 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
232	* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
233	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
234	* \|?\|?\|T\|D\|B\|type \|PL1\|Pl2\|U\| access id \|?\|
235	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
236	*
237	*/
238
239	/*
240	* Access rights (type + PL1 + PL2)
241	*/
242	#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */
243	#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */
244	#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */
245	#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */
246	#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */
247	#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */
248	#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */
249	#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */
250
251
252	/*
253	* Inline macros for misc. interesting opcodes
254	*/
255
256	/* generate a global label */
257	#define HPPA_ASM_LABEL(label) \
258	asm(".export " label ", ! .label " label);
259
260	/* Return From Interrupt RFI */
261	#define HPPA_ASM_RFI() asm volatile ("rfi")
262
263	/* Set System Mask SSM i,t */
264	#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
265	: "=r" (gr) \
266	: "i" (i))
267	/* Reset System Mask RSM i,t */
268	#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
269	: "=r" (gr) \
270	: "i" (i))
271	/* Move To System Mask MTSM r */
272	#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
273	: : "r" (gr))
274
275	/* Load Space Identifier LDSID (s,b),t */
276	#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
277	: "=r" (grt) \
278	: "i" (sr), \
279	"r" (grb))
280
281	/*
282	* Gcc extended asm doesn't really allow for treatment of space registers
283	* as "registers", so we have to use "i" format.
284	* Unfortunately this means that the "=" constraint is not available.
285	*/
286
287	/* Move To Space Register MTSP r,sr */
288	#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
289	: : "i" (sr), \
290	"r" (gr))
291
292	/* Move From Space Register MFSP sr,t */
293	#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
294	: "=r" (gr) \
295	: "i" (sr))
296
297	/* Move To Control register MTCTL r,t */
298	#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
299	: : "i" (cr), \
300	"r" (gr))
301
302	/* Move From Control register MFCTL r,t */
303	#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
304	: "=r" (gr) \
305	: "i" (cr))
306
307	/* Synchronize caches SYNC */
308	#define HPPA_ASM_SYNC() asm volatile ("sync")
309
310	/* Probe Read Access PROBER (s,b),r,t */
311	#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
312	asm volatile ("prober (%1,%2),%3,%0" \
313	: "=r" (grt) \
314	: "i" (sr), \
315	"r" (groff), \
316	"r" (gracc))
317
318	/* Probe Read Access Immediate PROBERI (s,b),i,t*/
319	#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
320	asm volatile ("proberi (%1,%2),%3,%0" \
321	: "=r" (grt) \
322	: "i" (sr), \
323	"r" (groff), \
324	"i" (iacc))
325
326	/* Probe Write Access PROBEW (s,b),r,t */
327	#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
328	asm volatile ("probew (%1,%2),%3,%0" \
329	: "=r" (grt) \
330	: "i" (sr), \
331	"r" (groff), \
332	"r" (gracc))
333
334	/* Probe Write Access Immediate PROBEWI (s,b),i,t */
335	#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
336	asm volatile ("probewi (%1,%2),%3,%0" \
337	: "=r" (grt) \
338	: "i" (sr), \
339	"r" (groff), \
340	"i" (iacc))
341
342	/* Load Physical Address LPA x(s,b),t */
343	#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
344	: "=r" (grt) \
345	: "i" (sr), \
346	"r" (grb))
347
348	/* Load Coherence Index LCI x(s,b),t */
349	/* AKA: Load Hash Address LHA x(s,b),t */
350	#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
351	: "=r" (grt) \
352	: "r" (grx),\
353	"i" (sr), \
354	"r" (grb))
355	#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
356
357	/* Purge Data Tlb PDTLB x(s,b) */
358	#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
359	: : "r" (grx), \
360	"i" (sr), \
361	"r" (grb))
362
363	/* Purge Instruction Tlb PITLB x(s,b) */
364	#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
365	: : "r" (grx), \
366	"i" (sr), \
367	"r" (grb))
368
369	/* Purge Data Tlb Entry PDTLBE x(s,b) */
370	#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
371	: : "r" (grx), \
372	"i" (sr), \
373	"r" (grb))
374
375	/* Purge Instruction Tlb Entry PITLBE x(s,b) */
376	#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
377	: : "r" (grx), \
378	"i" (sr), \
379	"r" (grb))
380
381
382	/* Insert Data TLB Address IDTLBA r,(s,b) */
383	#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
384	: : "r" (gr), \
385	"i" (sr), \
386	"r" (grb))
387
388	/* Insert Instruction TLB Address IITLBA r,(s,b) */
389	#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
390	: : "r" (gr), \
391	"i" (sr), \
392	"r" (grb))
393
394	/* Insert Data TLB Protection IDTLBP r,(s,b) */
395	#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
396	: : "r" (gr), \
397	"i" (sr), \
398	"r" (grb))
399
400	/* Insert Instruction TLB Protection IITLBP r,(s,b) */
401	#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
402	: : "r" (gr), \
403	"i" (sr), \
404	"r" (grb))
405
406	/* Purge Data Cache PDC x(s,b) */
407	#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
408	: : "r" (grx), \
409	"i" (sr), \
410	"r" (grb))
411
412	/* Flush Data Cache FDC x(s,b) */
413	#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
414	: : "r" (grx), \
415	"i" (sr), \
416	"r" (grb))
417
418	/* Flush Instruction Cache FDC x(s,b) */
419	#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
420	: : "r" (grx), \
421	"i" (sr), \
422	"r" (grb))
423
424	/* Flush Data Cache Entry FDCE x(s,b) */
425	#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
426	: : "r" (grx), \
427	"i" (sr), \
428	"r" (grb))
429
430	/* Flush Instruction Cache Entry FICE x(s,b) */
431	#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
432	: : "r" (grx), \
433	"i" (sr), \
434	"r" (grb))
435
436	/* Break BREAK i5,i13 */
437	#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
438	: : "i" (i5), \
439	"i" (i13))
440
441	/* Load and Clear Word Short LDCWS d(s,b),t */
442	#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
443	: "=r" (grt) \
444	: "i" (i), \
445	"i" (sr), \
446	"r" (grb))
447
448	/* Load and Clear Word Indexed LDCWX x(s,b),t */
449	#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
450	: "=r" (grt) \
451	: "r" (grx), \
452	"i" (sr), \
453	"r" (grb))
454
455	/* Load Word Absolute Short LDWAS d(b),t */
456	/* NOTE: "short" here means "short displacement" */
457	#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
458	: "=r" (gr) \
459	: "i" (disp), \
460	"r" (grbase))
461
462	/* Store Word Absolute Short STWAS r,d(b) */
463	/* NOTE: "short" here means "short displacement" */
464	#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
465	: : "r" (gr), \
466	"i" (disp), \
467	"r" (grbase))
468
469	/*
470	* Swap bytes
471	* REFERENCE: PA72000 TRM -- Appendix C
472	*/
473	#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
474	" shd %1,%1,16,%0 \n\
475	dep %0,15,8,%0 \n\
476	shd %1,%0,8,%0" \
477	: "=r" (swapped) \
478	: "r" (value) \
479	)
480
481
482	/* 72000 Diagnose instructions follow
483	* These macros assume gas knows about these instructions.
484	* gas2.2.u1 did not.
485	* I added them to my copy and installed it locally.
486	*
487	* There are very special requirements for these guys
488	* ref: TRM 6.1.3 Programming Constraints
489	*
490	* The macros below handle the following rules
491	*
492	* Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
493	* Must never be nullified (hence the leading nop)
494	* NOP must preced every RDD,RDT,WDD,WDT,RDTLB
495	* Instruction preceeding GR_SHDW must not set any of the GR's saved
496	*
497	* The macros do NOT deal with the following problems
498	* doubled DIAGNOSE instructions must not straddle a page boundary
499	* if code translation enabled. (since 2nd could trap on ITLB)
500	* If you care about DHIT and DPE bits of DR0, then
501	* No store instruction in the 2 insn window before RDD
502	*/
503
504
505	/* Move To CPU/DIAG register MTCPU r,t */
506	#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
507	" mtcpu %1,%0 \n" \
508	" mtcpu %1,%0" \
509	: : "i" (dr), \
510	"r" (gr))
511
512	/* Move From CPU/DIAG register MFCPU r,t */
513	#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
514	" mfcpu %1,%0\n" \
515	" mfcpu %1,%0" \
516	: "=r" (gr) \
517	: "i" (dr))
518
519	/* Transfer of Control Enable TOC_EN */
520	#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
521	" tocen")
522
523	/* Transfer of Control Disable TOC_DIS */
524	#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
525	" tocdis")
526
527	/* Shadow Registers to General Register SHDW_GR */
528	#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
529	" shdwgr" \
530	::: "r1" "r8" "r9" "r16" \
531	"r17" "r24" "r25")
532
533	/* General Registers to Shadow Register GR_SHDW */
534	#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
535	" grshdw \n" \
536	" grshdw")
537
538	/*
539	* Definitions of special registers for use by the above macros.
540	*/
541
542	/* Hardware Space Registers */
543	#define HPPA_SR0 0
544	#define HPPA_SR1 1
545	#define HPPA_SR2 2
546	#define HPPA_SR3 3
547	#define HPPA_SR4 4
548	#define HPPA_SR5 5
549	#define HPPA_SR6 6
550	#define HPPA_SR7 7
551
552	/* Hardware Control Registers */
553	#define HPPA_CR0 0
554	#define HPPA_RCTR 0 /* Recovery Counter Register */
555
556	#define HPPA_CR8 8 /* Protection ID 1 */
557	#define HPPA_PIDR1 8
558
559	#define HPPA_CR9 9 /* Protection ID 2 */
560	#define HPPA_PIDR2 9
561
562	#define HPPA_CR10 10
563	#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
564
565	#define HPPA_CR11 11
566	#define HPPA_SAR 11 /* Shift Amount Register */
567
568	#define HPPA_CR12 12
569	#define HPPA_PIDR3 12 /* Protection ID 3 */
570
571	#define HPPA_CR13 13
572	#define HPPA_PIDR4 13 /* Protection ID 4 */
573
574	#define HPPA_CR14 14
575	#define HPPA_IVA 14 /* Interrupt Vector Address */
576
577	#define HPPA_CR15 15
578	#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
579
580	#define HPPA_CR16 16
581	#define HPPA_ITMR 16 /* Interval Timer */
582
583	#define HPPA_CR17 17
584	#define HPPA_PCSQ 17 /* Program Counter Space queue */
585
586	#define HPPA_CR18 18
587	#define HPPA_PCOQ 18 /* Program Counter Offset queue */
588
589	#define HPPA_CR19 19
590	#define HPPA_IIR 19 /* Interruption Instruction Register */
591
592	#define HPPA_CR20 20
593	#define HPPA_ISR 20 /* Interruption Space Register */
594
595	#define HPPA_CR21 21
596	#define HPPA_IOR 21 /* Interruption Offset Register */
597
598	#define HPPA_CR22 22
599	#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
600
601	#define HPPA_CR23 23
602	#define HPPA_EIRR 23 /* External Interrupt Request */
603
604	#define HPPA_CR24 24
605	#define HPPA_PPDA 24 /* Physcial Page Directory Address */
606	#define HPPA_TR0 24 /* Temporary register 0 */
607
608	#define HPPA_CR25 25
609	#define HPPA_HTA 25 /* Hash Table Address */
610	#define HPPA_TR1 25 /* Temporary register 1 */
611
612	#define HPPA_CR26 26
613	#define HPPA_TR2 26 /* Temporary register 2 */
614
615	#define HPPA_CR27 27
616	#define HPPA_TR3 27 /* Temporary register 3 */
617
618	#define HPPA_CR28 28
619	#define HPPA_TR4 28 /* Temporary register 4 */
620
621	#define HPPA_CR29 29
622	#define HPPA_TR5 29 /* Temporary register 5 */
623
624	#define HPPA_CR30 30
625	#define HPPA_TR6 30 /* Temporary register 6 */
626
627	#define HPPA_CR31 31
628	#define HPPA_CPUID 31 /* MP identifier */
629
630	/*
631	* Diagnose registers
632	*/
633
634	#define HPPA_DR0 0
635	#define HPPA_DR1 1
636	#define HPPA_DR8 8
637	#define HPPA_DR24 24
638	#define HPPA_DR25 25
639
640	/*
641	* Tear apart a break instruction to find its type.
642	*/
643	#define HPPA_BREAK5(x) ((x) & 0x1F)
644	#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
645
646	/* assemble a break instruction */
647	#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) \| (((i13) & 0x1FFF) << 13))
648
649
650	/*
651	* this won't work in ASM or non-GNU compilers
652	*/
653
654	#if !defined(ASM) && defined(__GNUC__)
655
656	/*
657	* static inline utility functions to get at control registers
658	*/
659
660	#define EMIT_GET_CONTROL(name, reg) \
661	static __inline__ unsigned int \
662	get_ ## name (void) \
663	{ \
664	unsigned int value; \
665	HPPA_ASM_MFCTL(reg, value); \
666	return value; \
667	}
668
669	#define EMIT_SET_CONTROL(name, reg) \
670	static __inline__ void \
671	set_ ## name (unsigned int new_value) \
672	{ \
673	HPPA_ASM_MTCTL(new_value, reg); \
674	}
675
676	#define EMIT_CONTROLS(name, reg) \
677	EMIT_GET_CONTROL(name, reg) \
678	EMIT_SET_CONTROL(name, reg)
679
680	EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
681	EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
682	EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
683	EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
684	EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
685	EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
686	EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
687	EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
688	EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
689	EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
690	EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
691	EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
692	EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
693	EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
694	EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
695	EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
696	EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
697	EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
698	EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
699	EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
700	EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
701	EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
702	EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
703	EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
704	EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
705	EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
706
707	#endif /* ASM and GNU */
708
709	/*
710	* If and How to invoke the debugger (a ROM debugger generally)
711	*/
712	#define CPU_INVOKE_DEBUGGER \
713	do { \
714	HPPA_ASM_BREAK(1,1); \
715	} while (0)
716
717	#ifdef __cplusplus
718	}
719	#endif
720
721	#endif /* ! _INCLUDE_HPPA_H */
722

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