1 | /* |
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2 | * @(#)hppa.h 1.5 - 95/04/25 |
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3 | * |
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4 | * |
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5 | * File: $RCSfile$ |
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6 | * Project: PixelFlow |
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7 | * Created: 94/10/4 |
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8 | * RespEngr: tony bennett |
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9 | * Revision: $Revision$ |
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10 | * Last Mod: $Date$ |
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11 | * |
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12 | * Description: |
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13 | * |
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14 | * Definitions for HP PA Risc |
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15 | * ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual |
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16 | * |
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17 | * COPYRIGHT (c) 1994 by Division Incorporated |
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18 | * |
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19 | * To anyone who acknowledges that this file is provided "AS IS" |
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20 | * without any express or implied warranty: |
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21 | * permission to use, copy, modify, and distribute this file |
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22 | * for any purpose is hereby granted without fee, provided that |
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23 | * the above copyright notice and this notice appears in all |
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24 | * copies, and that the name of Division Incorporated not be |
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25 | * used in advertising or publicity pertaining to distribution |
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26 | * of the software without specific, written prior permission. |
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27 | * Division Incorporated makes no representations about the |
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28 | * suitability of this software for any purpose. |
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29 | * |
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30 | * |
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31 | * Note: |
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32 | * This file is included by both C and assembler code ( -DASM ) |
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33 | * |
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34 | * $Id$ |
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35 | */ |
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36 | |
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37 | #ifndef _INCLUDE_HPPA_H |
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38 | #define _INCLUDE_HPPA_H |
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39 | |
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40 | #if defined(__cplusplus) |
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41 | extern "C" { |
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42 | #endif |
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43 | |
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44 | /* |
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45 | * The following define the CPU Family and Model within the family |
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46 | * |
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47 | * NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced |
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48 | * with the name of the appropriate macro for this target CPU. |
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49 | */ |
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50 | |
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51 | #define hppa1_1 |
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52 | #define REPLACE_THIS_WITH_THE_CPU_MODEL |
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53 | #define REPLACE_THIS_WITH_THE_BSP |
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54 | |
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55 | /* |
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56 | * This section contains the information required to build |
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57 | * RTEMS for a particular member of the Hewlett Packard |
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58 | * PA-RISC family. It does this by setting variables to |
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59 | * indicate which implementation dependent features are |
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60 | * present in a particular member of the family. |
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61 | */ |
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62 | |
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63 | #if defined(hppa7100) |
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64 | |
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65 | #define RTEMS_MODEL_NAME "hppa 7100" |
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66 | |
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67 | #elif defined(hppa7200) |
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68 | |
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69 | #define RTEMS_MODEL_NAME "hppa 7200" |
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70 | |
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71 | #else |
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72 | |
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73 | #error "Unsupported CPU Model" |
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74 | |
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75 | #endif |
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76 | |
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77 | /* |
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78 | * Define the name of the CPU family. |
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79 | */ |
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80 | |
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81 | #define CPU_NAME "HP PA-RISC 1.1" |
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82 | |
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83 | #ifndef ASM |
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84 | /* |
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85 | * This section defines the basic types for this processor. |
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86 | */ |
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87 | |
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88 | typedef unsigned char unsigned8; /* 8-bit unsigned integer */ |
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89 | typedef unsigned short unsigned16; /* 16-bit unsigned integer */ |
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90 | typedef unsigned int unsigned32; /* 32-bit unsigned integer */ |
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91 | typedef unsigned long long unsigned64; /* 64-bit unsigned integer */ |
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92 | |
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93 | typedef unsigned16 Priority_Bit_map_control; |
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94 | |
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95 | typedef char signed8; /* 8-bit signed integer */ |
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96 | typedef short signed16; /* 16-bit signed integer */ |
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97 | typedef int signed32; /* 32-bit signed integer */ |
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98 | typedef long long signed64; /* 64 bit signed integer */ |
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99 | |
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100 | typedef unsigned32 boolean; /* Boolean value */ |
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101 | |
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102 | typedef float single_precision; /* single precision float */ |
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103 | typedef double double_precision; /* double precision float */ |
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104 | |
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105 | #endif /* !ASM */ |
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106 | |
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107 | |
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108 | /* |
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109 | * Processor Status Word (PSW) Masks |
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110 | */ |
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111 | |
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112 | #define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */ |
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113 | #define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */ |
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114 | #define HPPA_PSW_r2 0x20000000 /* reserved */ |
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115 | #define HPPA_PSW_r3 0x10000000 /* reserved */ |
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116 | #define HPPA_PSW_r4 0x08000000 /* reserved */ |
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117 | #define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */ |
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118 | #define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */ |
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119 | #define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */ |
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120 | #define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/ |
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121 | #define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */ |
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122 | #define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */ |
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123 | #define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */ |
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124 | #define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */ |
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125 | #define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */ |
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126 | #define HPPA_PSW_V 0x00020000 /* Divide Step Correction */ |
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127 | #define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */ |
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128 | #define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */ |
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129 | #define HPPA_PSW_r24 0x00000080 /* reserved */ |
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130 | #define HPPA_PSW_G 0x00000040 /* Debug trap Enable */ |
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131 | #define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */ |
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132 | #define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */ |
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133 | #define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */ |
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134 | #define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */ |
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135 | #define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */ |
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136 | #define HPPA_PSW_I 0x00000001 /* External, Power Failure, */ |
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137 | /* Low-Priority Machine Check */ |
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138 | /* Interruption Enable */ |
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139 | |
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140 | /* |
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141 | * HPPA traps and interrupts |
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142 | * basic layout. Note numbers do not denote priority |
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143 | * |
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144 | * 0-31 basic traps and interrupts defined by HPPA architecture |
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145 | * 32-63 32 external interrupts |
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146 | * 64-... bsp defined |
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147 | */ |
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148 | |
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149 | #define HPPA_INTERRUPT_NON_EXISTENT 0 |
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150 | /* group 1 */ |
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151 | #define HPPA_INTERRUPT_HIGH_PRIORITY_MACHINE_CHECK 1 |
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152 | /* group 2 */ |
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153 | #define HPPA_INTERRUPT_POWER_FAIL 2 |
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154 | #define HPPA_INTERRUPT_RECOVERY_COUNTER 3 |
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155 | #define HPPA_INTERRUPT_EXTERNAL_INTERRUPT 4 |
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156 | #define HPPA_INTERRUPT_LOW_PRIORITY_MACHINE_CHECK 5 |
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157 | #define HPPA_INTERRUPT_PERFORMANCE_MONITOR 29 |
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158 | /* group 3 */ |
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159 | #define HPPA_INTERRUPT_INSTRUCTION_TLB_MISS 6 |
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160 | #define HPPA_INTERRUPT_INSTRUCTION_MEMORY_PROTECTION 7 |
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161 | #define HPPA_INTERRUPT_INSTRUCTION_DEBUG 30 |
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162 | #define HPPA_INTERRUPT_ILLEGAL_INSTRUCTION 8 |
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163 | #define HPPA_INTERRUPT_BREAK_INSTRUCTION 9 |
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164 | #define HPPA_INTERRUPT_PRIVILEGED_OPERATION 10 |
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165 | #define HPPA_INTERRUPT_PRIVILEGED_REGISTER 11 |
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166 | #define HPPA_INTERRUPT_OVERFLOW 12 |
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167 | #define HPPA_INTERRUPT_CONDITIONAL 13 |
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168 | #define HPPA_INTERRUPT_ASSIST_EXCEPTION 14 |
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169 | #define HPPA_INTERRUPT_DATA_TLB_MISS 15 |
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170 | #define HPPA_INTERRUPT_NON_ACCESS_INSTRUCTION_TLB_MISS 16 |
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171 | #define HPPA_INTERRUPT_NON_ACCESS_DATA_TLB_MISS 17 |
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172 | #define HPPA_INTERRUPT_DATA_MEMORY_ACCESS_RIGHTS 26 |
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173 | #define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION_ID 27 |
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174 | #define HPPA_INTERRUPT_UNALIGNED_DATA_REFERENCE 28 |
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175 | #define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION 18 |
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176 | #define HPPA_INTERRUPT_DATA_MEMORY_BREAK 19 |
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177 | #define HPPA_INTERRUPT_TLB_DIRTY_BIT 20 |
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178 | #define HPPA_INTERRUPT_PAGE_REFERENCE 21 |
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179 | #define HPPA_INTERRUPT_DATA_DEBUG 31 |
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180 | #define HPPA_INTERRUPT_ASSIST_EMULATION 22 |
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181 | /* group 4 */ |
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182 | #define HPPA_INTERRUPT_HIGHER_PRIVILEGE_TRANSFER 23 |
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183 | #define HPPA_INTERRUPT_LOWER_PRIVILEGE_TRANSFER 24 |
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184 | #define HPPA_INTERRUPT_TAKEN_BRANCH 25 |
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185 | |
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186 | #define HPPA_INTERRUPT_ON_CHIP_MAX 31 |
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187 | |
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188 | /* External Interrupts via interrupt 4 */ |
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189 | |
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190 | #define HPPA_INTERRUPT_EXTERNAL_BASE 32 |
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191 | |
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192 | #define HPPA_INTERRUPT_EXTERNAL_0 32 |
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193 | #define HPPA_INTERRUPT_EXTERNAL_1 33 |
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194 | #define HPPA_INTERRUPT_EXTERNAL_2 34 |
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195 | #define HPPA_INTERRUPT_EXTERNAL_3 35 |
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196 | #define HPPA_INTERRUPT_EXTERNAL_4 36 |
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197 | #define HPPA_INTERRUPT_EXTERNAL_5 37 |
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198 | #define HPPA_INTERRUPT_EXTERNAL_6 38 |
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199 | #define HPPA_INTERRUPT_EXTERNAL_7 39 |
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200 | #define HPPA_INTERRUPT_EXTERNAL_8 40 |
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201 | #define HPPA_INTERRUPT_EXTERNAL_9 41 |
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202 | #define HPPA_INTERRUPT_EXTERNAL_10 42 |
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203 | #define HPPA_INTERRUPT_EXTERNAL_11 43 |
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204 | #define HPPA_INTERRUPT_EXTERNAL_12 44 |
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205 | #define HPPA_INTERRUPT_EXTERNAL_13 45 |
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206 | #define HPPA_INTERRUPT_EXTERNAL_14 46 |
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207 | #define HPPA_INTERRUPT_EXTERNAL_15 47 |
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208 | #define HPPA_INTERRUPT_EXTERNAL_16 48 |
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209 | #define HPPA_INTERRUPT_EXTERNAL_17 49 |
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210 | #define HPPA_INTERRUPT_EXTERNAL_18 50 |
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211 | #define HPPA_INTERRUPT_EXTERNAL_19 51 |
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212 | #define HPPA_INTERRUPT_EXTERNAL_20 52 |
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213 | #define HPPA_INTERRUPT_EXTERNAL_21 53 |
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214 | #define HPPA_INTERRUPT_EXTERNAL_22 54 |
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215 | #define HPPA_INTERRUPT_EXTERNAL_23 55 |
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216 | #define HPPA_INTERRUPT_EXTERNAL_24 56 |
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217 | #define HPPA_INTERRUPT_EXTERNAL_25 57 |
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218 | #define HPPA_INTERRUPT_EXTERNAL_26 58 |
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219 | #define HPPA_INTERRUPT_EXTERNAL_27 59 |
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220 | #define HPPA_INTERRUPT_EXTERNAL_28 60 |
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221 | #define HPPA_INTERRUPT_EXTERNAL_29 61 |
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222 | #define HPPA_INTERRUPT_EXTERNAL_30 62 |
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223 | #define HPPA_INTERRUPT_EXTERNAL_31 63 |
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224 | |
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225 | #define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0 |
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226 | #define HPPA_EXTERNAL_INTERRUPTS 32 |
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227 | |
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228 | /* BSP defined interrupts begin here */ |
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229 | |
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230 | #define HPPA_INTERRUPT_MAX 64 |
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231 | |
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232 | /* |
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233 | * Inline macros for misc. interesting opcodes |
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234 | */ |
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235 | |
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236 | /* generate a global label */ |
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237 | #define HPPA_ASM_LABEL(label) \ |
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238 | asm(".export " label ", ! .label " label); |
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239 | |
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240 | /* Return From Interrupt RFI */ |
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241 | #define HPPA_ASM_RFI() asm volatile ("rfi") |
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242 | |
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243 | /* Set System Mask SSM i,t */ |
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244 | #define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \ |
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245 | : "=r" (gr) \ |
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246 | : "i" (i)) |
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247 | /* Reset System Mask RSM i,t */ |
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248 | #define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \ |
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249 | : "=r" (gr) \ |
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250 | : "i" (i)) |
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251 | /* Move To System Mask MTSM r */ |
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252 | #define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \ |
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253 | : : "r" (gr)) |
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254 | |
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255 | /* Load Space Identifier LDSID (s,b),t */ |
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256 | #define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \ |
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257 | : "=r" (grt) \ |
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258 | : "i" (sr), \ |
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259 | "r" (grb)) |
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260 | |
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261 | /* |
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262 | * Gcc extended asm doesn't really allow for treatment of space registers |
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263 | * as "registers", so we have to use "i" format. |
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264 | * Unfortunately this means that the "=" constraint is not available. |
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265 | */ |
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266 | |
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267 | /* Move To Space Register MTSP r,sr */ |
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268 | #define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \ |
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269 | : : "i" (sr), \ |
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270 | "r" (gr)) |
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271 | |
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272 | /* Move From Space Register MFSP sr,t */ |
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273 | #define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \ |
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274 | : "=r" (gr) \ |
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275 | : "i" (sr)) |
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276 | |
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277 | /* Move To Control register MTCTL r,t */ |
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278 | #define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \ |
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279 | : : "i" (cr), \ |
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280 | "r" (gr)) |
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281 | |
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282 | /* Move From Control register MFCTL r,t */ |
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283 | #define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \ |
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284 | : "=r" (gr) \ |
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285 | : "i" (cr)) |
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286 | |
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287 | /* Synchronize caches SYNC */ |
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288 | #define HPPA_ASM_SYNC() asm volatile ("sync") |
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289 | |
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290 | /* Probe Read Access PROBER (s,b),r,t */ |
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291 | #define HPPA_ASM_PROBER(sr,groff,gracc,grt) \ |
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292 | asm volatile ("prober (%1,%2),%3,%0" \ |
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293 | : "=r" (grt) \ |
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294 | : "i" (sr), \ |
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295 | "r" (groff), \ |
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296 | "r" (gracc)) |
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297 | |
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298 | /* Probe Read Access Immediate PROBERI (s,b),i,t*/ |
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299 | #define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \ |
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300 | asm volatile ("proberi (%1,%2),%3,%0" \ |
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301 | : "=r" (grt) \ |
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302 | : "i" (sr), \ |
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303 | "r" (groff), \ |
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304 | "i" (iacc)) |
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305 | |
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306 | /* Probe Write Access PROBEW (s,b),r,t */ |
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307 | #define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \ |
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308 | asm volatile ("probew (%1,%2),%3,%0" \ |
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309 | : "=r" (grt) \ |
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310 | : "i" (sr), \ |
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311 | "r" (groff), \ |
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312 | "r" (gracc)) |
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313 | |
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314 | /* Probe Write Access Immediate PROBEWI (s,b),i,t */ |
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315 | #define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \ |
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316 | asm volatile ("probewi (%1,%2),%3,%0" \ |
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317 | : "=r" (grt) \ |
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318 | : "i" (sr), \ |
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319 | "r" (groff), \ |
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320 | "i" (iacc)) |
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321 | |
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322 | /* Load Physical Address LPA x(s,b),t */ |
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323 | #define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \ |
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324 | : "=r" (grt) \ |
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325 | : "i" (sr), \ |
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326 | "r" (grb)) |
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327 | |
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328 | /* Load Coherence Index LCI x(s,b),t */ |
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329 | /* AKA: Load Hash Address LHA x(s,b),t */ |
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330 | #define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \ |
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331 | : "=r" (grt) \ |
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332 | : "r" (grx),\ |
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333 | "i" (sr), \ |
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334 | "r" (grb)) |
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335 | #define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt) |
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336 | |
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337 | /* Purge Data Tlb PDTLB x(s,b) */ |
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338 | #define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \ |
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339 | : : "r" (grx), \ |
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340 | "i" (sr), \ |
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341 | "r" (grb)) |
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342 | |
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343 | /* Purge Instruction Tlb PITLB x(s,b) */ |
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344 | #define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \ |
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345 | : : "r" (grx), \ |
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346 | "i" (sr), \ |
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347 | "r" (grb)) |
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348 | |
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349 | /* Purge Data Tlb Entry PDTLBE x(s,b) */ |
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350 | #define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \ |
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351 | : : "r" (grx), \ |
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352 | "i" (sr), \ |
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353 | "r" (grb)) |
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354 | |
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355 | /* Purge Instruction Tlb Entry PITLBE x(s,b) */ |
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356 | #define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \ |
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357 | : : "r" (grx), \ |
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358 | "i" (sr), \ |
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359 | "r" (grb)) |
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360 | |
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361 | |
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362 | /* Insert Data TLB Address IDTLBA r,(s,b) */ |
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363 | #define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \ |
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364 | : : "r" (gr), \ |
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365 | "i" (sr), \ |
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366 | "r" (grb)) |
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367 | |
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368 | /* Insert Instruction TLB Address IITLBA r,(s,b) */ |
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369 | #define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \ |
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370 | : : "r" (gr), \ |
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371 | "i" (sr), \ |
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372 | "r" (grb)) |
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373 | |
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374 | /* Insert Data TLB Protection IDTLBP r,(s,b) */ |
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375 | #define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \ |
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376 | : : "r" (gr), \ |
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377 | "i" (sr), \ |
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378 | "r" (grb)) |
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379 | |
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380 | /* Insert Instruction TLB Protection IITLBP r,(s,b) */ |
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381 | #define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \ |
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382 | : : "r" (gr), \ |
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383 | "i" (sr), \ |
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384 | "r" (grb)) |
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385 | |
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386 | /* Purge Data Cache PDC x(s,b) */ |
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387 | #define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \ |
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388 | : : "r" (grx), \ |
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389 | "i" (sr), \ |
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390 | "r" (grb)) |
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391 | |
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392 | /* Flush Data Cache FDC x(s,b) */ |
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393 | #define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \ |
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394 | : : "r" (grx), \ |
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395 | "i" (sr), \ |
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396 | "r" (grb)) |
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397 | |
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398 | /* Flush Instruction Cache FDC x(s,b) */ |
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399 | #define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \ |
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400 | : : "r" (grx), \ |
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401 | "i" (sr), \ |
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402 | "r" (grb)) |
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403 | |
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404 | /* Flush Data Cache Entry FDCE x(s,b) */ |
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405 | #define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \ |
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406 | : : "r" (grx), \ |
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407 | "i" (sr), \ |
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408 | "r" (grb)) |
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409 | |
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410 | /* Flush Instruction Cache Entry FICE x(s,b) */ |
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411 | #define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \ |
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412 | : : "r" (grx), \ |
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413 | "i" (sr), \ |
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414 | "r" (grb)) |
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415 | |
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416 | /* Break BREAK i5,i13 */ |
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417 | #define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \ |
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418 | : : "i" (i5), \ |
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419 | "i" (i13)) |
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420 | |
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421 | /* Load and Clear Word Short LDCWS d(s,b),t */ |
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422 | #define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \ |
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423 | : "=r" (grt) \ |
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424 | : "i" (i), \ |
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425 | "i" (sr), \ |
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426 | "r" (grb)) |
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427 | |
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428 | /* Load and Clear Word Indexed LDCWX x(s,b),t */ |
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429 | #define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \ |
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430 | : "=r" (grt) \ |
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431 | : "r" (grx), \ |
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432 | "i" (sr), \ |
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433 | "r" (grb)) |
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434 | |
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435 | /* Load Word Absolute Short LDWAS d(b),t */ |
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436 | /* NOTE: "short" here means "short displacement" */ |
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437 | #define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \ |
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438 | : "=r" (gr) \ |
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439 | : "i" (disp), \ |
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440 | "r" (grbase)) |
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441 | |
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442 | /* Store Word Absolute Short STWAS r,d(b) */ |
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443 | /* NOTE: "short" here means "short displacement" */ |
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444 | #define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \ |
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445 | : : "r" (gr), \ |
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446 | "i" (disp), \ |
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447 | "r" (grbase)) |
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448 | |
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449 | /* |
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450 | * Swap bytes |
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451 | * REFERENCE: PA72000 TRM -- Appendix C |
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452 | */ |
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453 | #define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \ |
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454 | " shd %1,%1,16,%0 \n\ |
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455 | dep %0,15,8,%0 \n\ |
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456 | shd %1,%0,8,%0" \ |
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457 | : "=r" (swapped) \ |
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458 | : "r" (value) \ |
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459 | ) |
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460 | |
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461 | |
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462 | /* 72000 Diagnose instructions follow |
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463 | * These macros assume gas knows about these instructions. |
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464 | * gas2.2.u1 did not. |
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465 | * I added them to my copy and installed it locally. |
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466 | * |
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467 | * There are *very* special requirements for these guys |
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468 | * ref: TRM 6.1.3 Programming Constraints |
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469 | * |
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470 | * The macros below handle the following rules |
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471 | * |
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472 | * Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled. |
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473 | * Must never be nullified (hence the leading nop) |
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474 | * NOP must preced every RDD,RDT,WDD,WDT,RDTLB |
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475 | * Instruction preceeding GR_SHDW must not set any of the GR's saved |
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476 | * |
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477 | * The macros do *NOT* deal with the following problems |
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478 | * doubled DIAGNOSE instructions must not straddle a page boundary |
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479 | * if code translation enabled. (since 2nd could trap on ITLB) |
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480 | * If you care about DHIT and DPE bits of DR0, then |
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481 | * No store instruction in the 2 insn window before RDD |
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482 | */ |
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483 | |
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484 | |
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485 | /* Move To CPU/DIAG register MTCPU r,t */ |
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486 | #define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \ |
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487 | " mtcpu %1,%0 \n" \ |
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488 | " mtcpu %1,%0" \ |
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489 | : : "i" (dr), \ |
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490 | "r" (gr)) |
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491 | |
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492 | /* Move From CPU/DIAG register MFCPU r,t */ |
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493 | #define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \ |
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494 | " mfcpu %1,%0\n" \ |
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495 | " mfcpu %1,%0" \ |
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496 | : "=r" (gr) \ |
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497 | : "i" (dr)) |
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498 | |
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499 | /* Transfer of Control Enable TOC_EN */ |
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500 | #define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \ |
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501 | " tocen") |
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502 | |
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503 | /* Transfer of Control Disable TOC_DIS */ |
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504 | #define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \ |
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505 | " tocdis") |
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506 | |
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507 | /* Shadow Registers to General Register SHDW_GR */ |
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508 | #define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \ |
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509 | " shdwgr" \ |
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510 | ::: "r1" "r8" "r9" "r16" \ |
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511 | "r17" "r24" "r25") |
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512 | |
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513 | /* General Registers to Shadow Register GR_SHDW */ |
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514 | #define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \ |
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515 | " grshdw \n" \ |
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516 | " grshdw") |
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517 | |
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518 | /* |
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519 | * Definitions of special registers for use by the above macros. |
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520 | */ |
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521 | |
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522 | /* Hardware Space Registers */ |
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523 | #define SR0 0 |
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524 | #define SR1 1 |
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525 | #define SR2 2 |
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526 | #define SR3 3 |
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527 | #define SR4 4 |
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528 | #define SR5 5 |
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529 | #define SR6 6 |
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530 | #define SR7 7 |
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531 | |
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532 | /* Hardware Control Registers */ |
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533 | #define CR0 0 |
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534 | #define RCTR 0 /* Recovery Counter Register */ |
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535 | |
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536 | #define CR8 8 /* Protection ID 1 */ |
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537 | #define PIDR1 8 |
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538 | |
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539 | #define CR9 9 /* Protection ID 2 */ |
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540 | #define PIDR2 9 |
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541 | |
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542 | #define CR10 10 |
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543 | #define CCR 10 /* Coprocessor Confiquration Register */ |
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544 | |
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545 | #define CR11 11 |
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546 | #define SAR 11 /* Shift Amount Register */ |
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547 | |
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548 | #define CR12 12 |
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549 | #define PIDR3 12 /* Protection ID 3 */ |
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550 | |
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551 | #define CR13 13 |
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552 | #define PIDR4 13 /* Protection ID 4 */ |
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553 | |
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554 | #define CR14 14 |
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555 | #define IVA 14 /* Interrupt Vector Address */ |
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556 | |
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557 | #define CR15 15 |
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558 | #define EIEM 15 /* External Interrupt Enable Mask */ |
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559 | |
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560 | #define CR16 16 |
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561 | #define ITMR 16 /* Interval Timer */ |
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562 | |
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563 | #define CR17 17 |
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564 | #define PCSQ 17 /* Program Counter Space queue */ |
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565 | |
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566 | #define CR18 18 |
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567 | #define PCOQ 18 /* Program Counter Offset queue */ |
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568 | |
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569 | #define CR19 19 |
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570 | #define IIR 19 /* Interruption Instruction Register */ |
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571 | |
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572 | #define CR20 20 |
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573 | #define ISR 20 /* Interruption Space Register */ |
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574 | |
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575 | #define CR21 21 |
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576 | #define IOR 21 /* Interruption Offset Register */ |
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577 | |
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578 | #define CR22 22 |
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579 | #define IPSW 22 /* Interrpution Processor Status Word */ |
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580 | |
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581 | #define CR23 23 |
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582 | #define EIRR 23 /* External Interrupt Request */ |
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583 | |
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584 | #define CR24 24 |
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585 | #define PPDA 24 /* Physcial Page Directory Address */ |
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586 | #define TR0 24 /* Temporary register 0 */ |
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587 | |
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588 | #define CR25 25 |
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589 | #define HTA 25 /* Hash Table Address */ |
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590 | #define TR1 25 /* Temporary register 1 */ |
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591 | |
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592 | #define CR26 26 |
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593 | #define TR2 26 /* Temporary register 2 */ |
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594 | |
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595 | #define CR27 27 |
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596 | #define TR3 27 /* Temporary register 3 */ |
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597 | |
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598 | #define CR28 28 |
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599 | #define TR4 28 /* Temporary register 4 */ |
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600 | |
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601 | #define CR29 29 |
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602 | #define TR5 29 /* Temporary register 5 */ |
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603 | |
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604 | #define CR30 30 |
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605 | #define TR6 30 /* Temporary register 6 */ |
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606 | |
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607 | #define CR31 31 |
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608 | #define CPUID 31 /* MP identifier */ |
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609 | |
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610 | /* |
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611 | * Diagnose registers |
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612 | */ |
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613 | |
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614 | #define DR0 0 |
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615 | #define DR1 1 |
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616 | #define DR8 8 |
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617 | #define DR24 24 |
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618 | #define DR25 25 |
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619 | |
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620 | /* |
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621 | * Tear apart a break instruction to find its type. |
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622 | */ |
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623 | #define HPPA_BREAK5(x) ((x) & 0x1F) |
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624 | #define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF) |
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625 | |
---|
626 | /* assemble a break instruction */ |
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627 | #define HPPA_BREAK(i5,i13) (((i5) & 0x1F) | (((i13) & 0x1FFF) << 13)) |
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628 | |
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629 | |
---|
630 | #ifndef ASM |
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631 | |
---|
632 | /* |
---|
633 | * static inline utility functions to get at control registers |
---|
634 | */ |
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635 | |
---|
636 | #define EMIT_GET_CONTROL(name, reg) \ |
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637 | static __inline__ unsigned int \ |
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638 | get_ ## name (void) \ |
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639 | { \ |
---|
640 | unsigned int value; \ |
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641 | HPPA_ASM_MFCTL(reg, value); \ |
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642 | return value; \ |
---|
643 | } |
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644 | |
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645 | #define EMIT_SET_CONTROL(name, reg) \ |
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646 | static __inline__ unsigned int \ |
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647 | set_ ## name (unsigned int new_value) \ |
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648 | { \ |
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649 | HPPA_ASM_MTCTL(new_value, reg); \ |
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650 | } |
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651 | |
---|
652 | #define EMIT_CONTROLS(name, reg) \ |
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653 | EMIT_GET_CONTROL(name, reg) \ |
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654 | EMIT_SET_CONTROL(name, reg) |
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655 | |
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656 | EMIT_CONTROLS(recovery, RCTR); /* CR0 */ |
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657 | EMIT_CONTROLS(pid1, PIDR1); /* CR8 */ |
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658 | EMIT_CONTROLS(pid2, PIDR2); /* CR9 */ |
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659 | EMIT_CONTROLS(ccr, CCR); /* CR10; CCR and SCR share CR10 */ |
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660 | EMIT_CONTROLS(scr, CCR); /* CR10; CCR and SCR share CR10 */ |
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661 | EMIT_CONTROLS(sar, SAR); /* CR11 */ |
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662 | EMIT_CONTROLS(pid3, PIDR3); /* CR12 */ |
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663 | EMIT_CONTROLS(pid4, PIDR4); /* CR13 */ |
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664 | EMIT_CONTROLS(iva, IVA); /* CR14 */ |
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665 | EMIT_CONTROLS(eiem, EIEM); /* CR15 */ |
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666 | EMIT_CONTROLS(itimer, ITMR); /* CR16 */ |
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667 | EMIT_CONTROLS(pcsq, PCSQ); /* CR17 */ |
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668 | EMIT_CONTROLS(pcoq, PCOQ); /* CR18 */ |
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669 | EMIT_CONTROLS(iir, IIR); /* CR19 */ |
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670 | EMIT_CONTROLS(isr, ISR); /* CR20 */ |
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671 | EMIT_CONTROLS(ior, IOR); /* CR21 */ |
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672 | EMIT_CONTROLS(ipsw, IPSW); /* CR22 */ |
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673 | EMIT_CONTROLS(eirr, EIRR); /* CR23 */ |
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674 | EMIT_CONTROLS(tr0, TR0); /* CR24 */ |
---|
675 | EMIT_CONTROLS(tr1, TR1); /* CR25 */ |
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676 | EMIT_CONTROLS(tr2, TR2); /* CR26 */ |
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677 | EMIT_CONTROLS(tr3, TR3); /* CR27 */ |
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678 | EMIT_CONTROLS(tr4, TR4); /* CR28 */ |
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679 | EMIT_CONTROLS(tr5, TR5); /* CR29 */ |
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680 | EMIT_CONTROLS(tr6, TR6); /* CR30 */ |
---|
681 | EMIT_CONTROLS(tr7, CR31); /* CR31 */ |
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682 | |
---|
683 | /* |
---|
684 | * If and How to invoke the debugger (a ROM debugger generally) |
---|
685 | */ |
---|
686 | |
---|
687 | #ifdef SIMHPPA_ROM |
---|
688 | /* invoke the pflow debugger */ |
---|
689 | #define CPU_INVOKE_DEBUGGER \ |
---|
690 | do { \ |
---|
691 | extern void debugger_break(void); \ |
---|
692 | debugger_break(); \ |
---|
693 | } while (0) |
---|
694 | #endif |
---|
695 | |
---|
696 | |
---|
697 | #endif /* ASM */ |
---|
698 | |
---|
699 | #ifdef __cplusplus |
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700 | } |
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701 | #endif |
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702 | |
---|
703 | #endif /* ! _INCLUDE_HPPA_H */ |
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704 | |
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