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source: rtems/c/src/exec/score/cpu/hppa1.1/hppa.h @ 8b2ecf85

4.104.114.84.95

Last change on this file since 8b2ecf85 was 8b2ecf85, checked in by Joel Sherrill <joel.sherrill@…>, on 05/23/96 at 15:37:38
updates from Tony Bennett
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1	/*
2	* Description:
3	*
4	* Definitions for HP PA Risc
5	* ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
6	*
7	* COPYRIGHT (c) 1994 by Division Incorporated
8	*
9	* To anyone who acknowledges that this file is provided "AS IS"
10	* without any express or implied warranty:
11	* permission to use, copy, modify, and distribute this file
12	* for any purpose is hereby granted without fee, provided that
13	* the above copyright notice and this notice appears in all
14	* copies, and that the name of Division Incorporated not be
15	* used in advertising or publicity pertaining to distribution
16	* of the software without specific, written prior permission.
17	* Division Incorporated makes no representations about the
18	* suitability of this software for any purpose.
19	*
20	*
21	* Note:
22	* This file is included by both C and assembler code ( -DASM )
23	*
24	* $Id$
25	*/
26
27	#ifndef _INCLUDE_HPPA_H
28	#define _INCLUDE_HPPA_H
29
30	#if defined(__cplusplus)
31	extern "C" {
32	#endif
33
34	/*
35	* The following define the CPU Family and Model within the family
36	*
37	* NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
38	* with the name of the appropriate macro for this target CPU.
39	*/
40
41	#ifdef hppa1_1
42	#undef hppa1_1
43	#endif
44	#define hppa1_1
45
46	#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
47	#undef REPLACE_THIS_WITH_THE_CPU_MODEL
48	#endif
49	#define REPLACE_THIS_WITH_THE_CPU_MODEL
50
51	#ifdef REPLACE_THIS_WITH_THE_BSP
52	#undef REPLACE_THIS_WITH_THE_BSP
53	#endif
54	#define REPLACE_THIS_WITH_THE_BSP
55
56	/*
57	* This section contains the information required to build
58	* RTEMS for a particular member of the Hewlett Packard
59	* PA-RISC family. It does this by setting variables to
60	* indicate which implementation dependent features are
61	* present in a particular member of the family.
62	*/
63
64	#if !defined(CPU_MODEL_NAME)
65
66	#if defined(hppa7100)
67
68	#define CPU_MODEL_NAME "hppa 7100"
69
70	#elif defined(hppa7200)
71
72	#define CPU_MODEL_NAME "hppa 7200"
73
74	#else
75
76	#define CPU_MODEL_NAME Unsupported CPU Model /* cause an error on usage */
77
78	#endif
79
80	#endif /* !defined(CPU_MODEL_NAME) */
81
82	/*
83	* Define the name of the CPU family.
84	*/
85
86	#if !defined(CPU_NAME)
87	#define CPU_NAME "HP PA-RISC 1.1"
88	#endif
89
90	/*
91	* Processor Status Word (PSW) Masks
92	*/
93
94	#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
95	#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
96	#define HPPA_PSW_r2 0x20000000 /* reserved */
97	#define HPPA_PSW_r3 0x10000000 /* reserved */
98	#define HPPA_PSW_r4 0x08000000 /* reserved */
99	#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
100	#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
101	#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
102	#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
103	#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
104	#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
105	#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
106	#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
107	#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
108	#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
109	#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
110	#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
111	#define HPPA_PSW_r24 0x00000080 /* reserved */
112	#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
113	#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
114	#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
115	#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
116	#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
117	#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
118	#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
119	/* Low-Priority Machine Check */
120	/* Interruption Enable */
121
122	/*
123	* HPPA traps and interrupts
124	* basic layout. Note numbers do not denote priority
125	*
126	* 0-31 basic traps and interrupts defined by HPPA architecture
127	* 0-31 32 external interrupts
128	* 32-... bsp defined
129	*/
130
131	#define HPPA_TRAP_NON_EXISTENT 0
132	/* group 1 */
133	#define HPPA_TRAP_HIGH_PRIORITY_MACHINE_CHECK 1
134	/* group 2 */
135	#define HPPA_TRAP_POWER_FAIL 2
136	#define HPPA_TRAP_RECOVERY_COUNTER 3
137	#define HPPA_TRAP_EXTERNAL_INTERRUPT 4
138	#define HPPA_TRAP_LOW_PRIORITY_MACHINE_CHECK 5
139	#define HPPA_TRAP_PERFORMANCE_MONITOR 29
140	/* group 3 */
141	#define HPPA_TRAP_INSTRUCTION_TLB_MISS 6
142	#define HPPA_TRAP_INSTRUCTION_MEMORY_PROTECTION 7
143	#define HPPA_TRAP_INSTRUCTION_DEBUG 30
144	#define HPPA_TRAP_ILLEGAL_INSTRUCTION 8
145	#define HPPA_TRAP_BREAK_INSTRUCTION 9
146	#define HPPA_TRAP_PRIVILEGED_OPERATION 10
147	#define HPPA_TRAP_PRIVILEGED_REGISTER 11
148	#define HPPA_TRAP_OVERFLOW 12
149	#define HPPA_TRAP_CONDITIONAL 13
150	#define HPPA_TRAP_ASSIST_EXCEPTION 14
151	#define HPPA_TRAP_DATA_TLB_MISS 15
152	#define HPPA_TRAP_NON_ACCESS_INSTRUCTION_TLB_MISS 16
153	#define HPPA_TRAP_NON_ACCESS_DATA_TLB_MISS 17
154	#define HPPA_TRAP_DATA_MEMORY_ACCESS_RIGHTS 26
155	#define HPPA_TRAP_DATA_MEMORY_PROTECTION_ID 27
156	#define HPPA_TRAP_UNALIGNED_DATA_REFERENCE 28
157	#define HPPA_TRAP_DATA_MEMORY_PROTECTION 18
158	#define HPPA_TRAP_DATA_MEMORY_BREAK 19
159	#define HPPA_TRAP_TLB_DIRTY_BIT 20
160	#define HPPA_TRAP_PAGE_REFERENCE 21
161	#define HPPA_TRAP_DATA_DEBUG 31
162	#define HPPA_TRAP_ASSIST_EMULATION 22
163	/* group 4 */
164	#define HPPA_TRAP_HIGHER_PRIVILEGE_TRANSFER 23
165	#define HPPA_TRAP_LOWER_PRIVILEGE_TRANSFER 24
166	#define HPPA_TRAP_TAKEN_BRANCH 25
167
168	#define HPPA_INTERNAL_TRAPS 32
169
170	/* External Interrupts via interrupt 4 */
171
172	#define HPPA_INTERRUPT_EXTERNAL_0 0
173	#define HPPA_INTERRUPT_EXTERNAL_1 1
174	#define HPPA_INTERRUPT_EXTERNAL_2 2
175	#define HPPA_INTERRUPT_EXTERNAL_3 3
176	#define HPPA_INTERRUPT_EXTERNAL_4 4
177	#define HPPA_INTERRUPT_EXTERNAL_5 5
178	#define HPPA_INTERRUPT_EXTERNAL_6 6
179	#define HPPA_INTERRUPT_EXTERNAL_7 7
180	#define HPPA_INTERRUPT_EXTERNAL_8 8
181	#define HPPA_INTERRUPT_EXTERNAL_9 9
182	#define HPPA_INTERRUPT_EXTERNAL_10 10
183	#define HPPA_INTERRUPT_EXTERNAL_11 11
184	#define HPPA_INTERRUPT_EXTERNAL_12 12
185	#define HPPA_INTERRUPT_EXTERNAL_13 13
186	#define HPPA_INTERRUPT_EXTERNAL_14 14
187	#define HPPA_INTERRUPT_EXTERNAL_15 15
188	#define HPPA_INTERRUPT_EXTERNAL_16 16
189	#define HPPA_INTERRUPT_EXTERNAL_17 17
190	#define HPPA_INTERRUPT_EXTERNAL_18 18
191	#define HPPA_INTERRUPT_EXTERNAL_19 19
192	#define HPPA_INTERRUPT_EXTERNAL_20 20
193	#define HPPA_INTERRUPT_EXTERNAL_21 21
194	#define HPPA_INTERRUPT_EXTERNAL_22 22
195	#define HPPA_INTERRUPT_EXTERNAL_23 23
196	#define HPPA_INTERRUPT_EXTERNAL_24 24
197	#define HPPA_INTERRUPT_EXTERNAL_25 25
198	#define HPPA_INTERRUPT_EXTERNAL_26 26
199	#define HPPA_INTERRUPT_EXTERNAL_27 27
200	#define HPPA_INTERRUPT_EXTERNAL_28 28
201	#define HPPA_INTERRUPT_EXTERNAL_29 29
202	#define HPPA_INTERRUPT_EXTERNAL_30 30
203	#define HPPA_INTERRUPT_EXTERNAL_31 31
204
205	#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
206	#define HPPA_EXTERNAL_INTERRUPTS 32
207
208	/* BSP defined interrupts begin here */
209
210	#define HPPA_INTERRUPT_MAX 32
211
212	/*
213	* Cache characteristics
214	*/
215
216	#define HPPA_CACHELINE_SIZE 32
217	#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
218
219	/*
220	* page size characteristics
221	*/
222
223	#define HPPA_PAGE_SIZE 4096
224	#define HPPA_PAGE_MASK (0xfffff000)
225
226
227	/*
228	* TLB characteristics
229	*
230	* Flags and Access Control layout for using TLB protection insertion
231	*
232	* 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
233	* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
234	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
235	* \|?\|?\|T\|D\|B\|type \|PL1\|Pl2\|U\| access id \|?\|
236	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
237	*
238	*/
239
240	/*
241	* Access rights (type + PL1 + PL2)
242	*/
243	#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */
244	#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */
245	#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */
246	#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */
247	#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */
248	#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */
249	#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */
250	#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */
251
252
253	/*
254	* Inline macros for misc. interesting opcodes
255	*/
256
257	/* generate a global label */
258	#define HPPA_ASM_LABEL(label) \
259	asm(".export " label ", ! .label " label);
260
261	/* Return From Interrupt RFI */
262	#define HPPA_ASM_RFI() asm volatile ("rfi")
263
264	/* Set System Mask SSM i,t */
265	#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
266	: "=r" (gr) \
267	: "i" (i))
268	/* Reset System Mask RSM i,t */
269	#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
270	: "=r" (gr) \
271	: "i" (i))
272	/* Move To System Mask MTSM r */
273	#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
274	: : "r" (gr))
275
276	/* Load Space Identifier LDSID (s,b),t */
277	#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
278	: "=r" (grt) \
279	: "i" (sr), \
280	"r" (grb))
281
282	/*
283	* Gcc extended asm doesn't really allow for treatment of space registers
284	* as "registers", so we have to use "i" format.
285	* Unfortunately this means that the "=" constraint is not available.
286	*/
287
288	/* Move To Space Register MTSP r,sr */
289	#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
290	: : "i" (sr), \
291	"r" (gr))
292
293	/* Move From Space Register MFSP sr,t */
294	#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
295	: "=r" (gr) \
296	: "i" (sr))
297
298	/* Move To Control register MTCTL r,t */
299	#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
300	: : "i" (cr), \
301	"r" (gr))
302
303	/* Move From Control register MFCTL r,t */
304	#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
305	: "=r" (gr) \
306	: "i" (cr))
307
308	/* Synchronize caches SYNC */
309	#define HPPA_ASM_SYNC() asm volatile ("sync")
310
311	/* Probe Read Access PROBER (s,b),r,t */
312	#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
313	asm volatile ("prober (%1,%2),%3,%0" \
314	: "=r" (grt) \
315	: "i" (sr), \
316	"r" (groff), \
317	"r" (gracc))
318
319	/* Probe Read Access Immediate PROBERI (s,b),i,t*/
320	#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
321	asm volatile ("proberi (%1,%2),%3,%0" \
322	: "=r" (grt) \
323	: "i" (sr), \
324	"r" (groff), \
325	"i" (iacc))
326
327	/* Probe Write Access PROBEW (s,b),r,t */
328	#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
329	asm volatile ("probew (%1,%2),%3,%0" \
330	: "=r" (grt) \
331	: "i" (sr), \
332	"r" (groff), \
333	"r" (gracc))
334
335	/* Probe Write Access Immediate PROBEWI (s,b),i,t */
336	#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
337	asm volatile ("probewi (%1,%2),%3,%0" \
338	: "=r" (grt) \
339	: "i" (sr), \
340	"r" (groff), \
341	"i" (iacc))
342
343	/* Load Physical Address LPA x(s,b),t */
344	#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
345	: "=r" (grt) \
346	: "i" (sr), \
347	"r" (grb))
348
349	/* Load Coherence Index LCI x(s,b),t */
350	/* AKA: Load Hash Address LHA x(s,b),t */
351	#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
352	: "=r" (grt) \
353	: "r" (grx),\
354	"i" (sr), \
355	"r" (grb))
356	#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
357
358	/* Purge Data Tlb PDTLB x(s,b) */
359	#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
360	: : "r" (grx), \
361	"i" (sr), \
362	"r" (grb))
363
364	/* Purge Instruction Tlb PITLB x(s,b) */
365	#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
366	: : "r" (grx), \
367	"i" (sr), \
368	"r" (grb))
369
370	/* Purge Data Tlb Entry PDTLBE x(s,b) */
371	#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
372	: : "r" (grx), \
373	"i" (sr), \
374	"r" (grb))
375
376	/* Purge Instruction Tlb Entry PITLBE x(s,b) */
377	#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
378	: : "r" (grx), \
379	"i" (sr), \
380	"r" (grb))
381
382
383	/* Insert Data TLB Address IDTLBA r,(s,b) */
384	#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
385	: : "r" (gr), \
386	"i" (sr), \
387	"r" (grb))
388
389	/* Insert Instruction TLB Address IITLBA r,(s,b) */
390	#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
391	: : "r" (gr), \
392	"i" (sr), \
393	"r" (grb))
394
395	/* Insert Data TLB Protection IDTLBP r,(s,b) */
396	#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
397	: : "r" (gr), \
398	"i" (sr), \
399	"r" (grb))
400
401	/* Insert Instruction TLB Protection IITLBP r,(s,b) */
402	#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
403	: : "r" (gr), \
404	"i" (sr), \
405	"r" (grb))
406
407	/* Purge Data Cache PDC x(s,b) */
408	#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
409	: : "r" (grx), \
410	"i" (sr), \
411	"r" (grb))
412
413	/* Flush Data Cache FDC x(s,b) */
414	#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
415	: : "r" (grx), \
416	"i" (sr), \
417	"r" (grb))
418
419	/* Flush Instruction Cache FDC x(s,b) */
420	#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
421	: : "r" (grx), \
422	"i" (sr), \
423	"r" (grb))
424
425	/* Flush Data Cache Entry FDCE x(s,b) */
426	#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
427	: : "r" (grx), \
428	"i" (sr), \
429	"r" (grb))
430
431	/* Flush Instruction Cache Entry FICE x(s,b) */
432	#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
433	: : "r" (grx), \
434	"i" (sr), \
435	"r" (grb))
436
437	/* Break BREAK i5,i13 */
438	#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
439	: : "i" (i5), \
440	"i" (i13))
441
442	/* Load and Clear Word Short LDCWS d(s,b),t */
443	#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
444	: "=r" (grt) \
445	: "i" (i), \
446	"i" (sr), \
447	"r" (grb))
448
449	/* Load and Clear Word Indexed LDCWX x(s,b),t */
450	#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
451	: "=r" (grt) \
452	: "r" (grx), \
453	"i" (sr), \
454	"r" (grb))
455
456	/* Load Word Absolute Short LDWAS d(b),t */
457	/* NOTE: "short" here means "short displacement" */
458	#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
459	: "=r" (gr) \
460	: "i" (disp), \
461	"r" (grbase))
462
463	/* Store Word Absolute Short STWAS r,d(b) */
464	/* NOTE: "short" here means "short displacement" */
465	#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
466	: : "r" (gr), \
467	"i" (disp), \
468	"r" (grbase))
469
470	/*
471	* Swap bytes
472	* REFERENCE: PA72000 TRM -- Appendix C
473	*/
474	#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
475	" shd %1,%1,16,%0 \n\
476	dep %0,15,8,%0 \n\
477	shd %1,%0,8,%0" \
478	: "=r" (swapped) \
479	: "r" (value) \
480	)
481
482
483	/* 72000 Diagnose instructions follow
484	* These macros assume gas knows about these instructions.
485	* gas2.2.u1 did not.
486	* I added them to my copy and installed it locally.
487	*
488	* There are very special requirements for these guys
489	* ref: TRM 6.1.3 Programming Constraints
490	*
491	* The macros below handle the following rules
492	*
493	* Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
494	* Must never be nullified (hence the leading nop)
495	* NOP must preced every RDD,RDT,WDD,WDT,RDTLB
496	* Instruction preceeding GR_SHDW must not set any of the GR's saved
497	*
498	* The macros do NOT deal with the following problems
499	* doubled DIAGNOSE instructions must not straddle a page boundary
500	* if code translation enabled. (since 2nd could trap on ITLB)
501	* If you care about DHIT and DPE bits of DR0, then
502	* No store instruction in the 2 insn window before RDD
503	*/
504
505
506	/* Move To CPU/DIAG register MTCPU r,t */
507	#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
508	" mtcpu %1,%0 \n" \
509	" mtcpu %1,%0" \
510	: : "i" (dr), \
511	"r" (gr))
512
513	/* Move From CPU/DIAG register MFCPU r,t */
514	#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
515	" mfcpu %1,%0\n" \
516	" mfcpu %1,%0" \
517	: "=r" (gr) \
518	: "i" (dr))
519
520	/* Transfer of Control Enable TOC_EN */
521	#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
522	" tocen")
523
524	/* Transfer of Control Disable TOC_DIS */
525	#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
526	" tocdis")
527
528	/* Shadow Registers to General Register SHDW_GR */
529	#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
530	" shdwgr" \
531	::: "r1" "r8" "r9" "r16" \
532	"r17" "r24" "r25")
533
534	/* General Registers to Shadow Register GR_SHDW */
535	#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
536	" grshdw \n" \
537	" grshdw")
538
539	/*
540	* Definitions of special registers for use by the above macros.
541	*/
542
543	/* Hardware Space Registers */
544	#define HPPA_SR0 0
545	#define HPPA_SR1 1
546	#define HPPA_SR2 2
547	#define HPPA_SR3 3
548	#define HPPA_SR4 4
549	#define HPPA_SR5 5
550	#define HPPA_SR6 6
551	#define HPPA_SR7 7
552
553	/* Hardware Control Registers */
554	#define HPPA_CR0 0
555	#define HPPA_RCTR 0 /* Recovery Counter Register */
556
557	#define HPPA_CR8 8 /* Protection ID 1 */
558	#define HPPA_PIDR1 8
559
560	#define HPPA_CR9 9 /* Protection ID 2 */
561	#define HPPA_PIDR2 9
562
563	#define HPPA_CR10 10
564	#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
565
566	#define HPPA_CR11 11
567	#define HPPA_SAR 11 /* Shift Amount Register */
568
569	#define HPPA_CR12 12
570	#define HPPA_PIDR3 12 /* Protection ID 3 */
571
572	#define HPPA_CR13 13
573	#define HPPA_PIDR4 13 /* Protection ID 4 */
574
575	#define HPPA_CR14 14
576	#define HPPA_IVA 14 /* Interrupt Vector Address */
577
578	#define HPPA_CR15 15
579	#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
580
581	#define HPPA_CR16 16
582	#define HPPA_ITMR 16 /* Interval Timer */
583
584	#define HPPA_CR17 17
585	#define HPPA_PCSQ 17 /* Program Counter Space queue */
586
587	#define HPPA_CR18 18
588	#define HPPA_PCOQ 18 /* Program Counter Offset queue */
589
590	#define HPPA_CR19 19
591	#define HPPA_IIR 19 /* Interruption Instruction Register */
592
593	#define HPPA_CR20 20
594	#define HPPA_ISR 20 /* Interruption Space Register */
595
596	#define HPPA_CR21 21
597	#define HPPA_IOR 21 /* Interruption Offset Register */
598
599	#define HPPA_CR22 22
600	#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
601
602	#define HPPA_CR23 23
603	#define HPPA_EIRR 23 /* External Interrupt Request */
604
605	#define HPPA_CR24 24
606	#define HPPA_PPDA 24 /* Physcial Page Directory Address */
607	#define HPPA_TR0 24 /* Temporary register 0 */
608
609	#define HPPA_CR25 25
610	#define HPPA_HTA 25 /* Hash Table Address */
611	#define HPPA_TR1 25 /* Temporary register 1 */
612
613	#define HPPA_CR26 26
614	#define HPPA_TR2 26 /* Temporary register 2 */
615
616	#define HPPA_CR27 27
617	#define HPPA_TR3 27 /* Temporary register 3 */
618
619	#define HPPA_CR28 28
620	#define HPPA_TR4 28 /* Temporary register 4 */
621
622	#define HPPA_CR29 29
623	#define HPPA_TR5 29 /* Temporary register 5 */
624
625	#define HPPA_CR30 30
626	#define HPPA_TR6 30 /* Temporary register 6 */
627
628	#define HPPA_CR31 31
629	#define HPPA_CPUID 31 /* MP identifier */
630
631	/*
632	* Diagnose registers
633	*/
634
635	#define HPPA_DR0 0
636	#define HPPA_DR1 1
637	#define HPPA_DR8 8
638	#define HPPA_DR24 24
639	#define HPPA_DR25 25
640
641	/*
642	* Tear apart a break instruction to find its type.
643	*/
644	#define HPPA_BREAK5(x) ((x) & 0x1F)
645	#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
646
647	/* assemble a break instruction */
648	#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) \| (((i13) & 0x1FFF) << 13))
649
650
651	/*
652	* this won't work in ASM or non-GNU compilers
653	*/
654
655	#if !defined(ASM) && defined(__GNUC__)
656
657	/*
658	* static inline utility functions to get at control registers
659	*/
660
661	#define EMIT_GET_CONTROL(name, reg) \
662	static __inline__ unsigned int \
663	get_ ## name (void) \
664	{ \
665	unsigned int value; \
666	HPPA_ASM_MFCTL(reg, value); \
667	return value; \
668	}
669
670	#define EMIT_SET_CONTROL(name, reg) \
671	static __inline__ void \
672	set_ ## name (unsigned int new_value) \
673	{ \
674	HPPA_ASM_MTCTL(new_value, reg); \
675	}
676
677	#define EMIT_CONTROLS(name, reg) \
678	EMIT_GET_CONTROL(name, reg) \
679	EMIT_SET_CONTROL(name, reg)
680
681	EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
682	EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
683	EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
684	EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
685	EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
686	EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
687	EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
688	EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
689	EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
690	EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
691	EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
692	EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
693	EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
694	EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
695	EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
696	EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
697	EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
698	EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
699	EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
700	EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
701	EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
702	EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
703	EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
704	EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
705	EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
706	EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
707
708	#endif /* ASM and GNU */
709
710	/*
711	* If and How to invoke the debugger (a ROM debugger generally)
712	*/
713	#define CPU_INVOKE_DEBUGGER \
714	do { \
715	HPPA_ASM_BREAK(1,1); \
716	} while (0)
717
718	#ifdef __cplusplus
719	}
720	#endif
721
722	#endif /* ! _INCLUDE_HPPA_H */
723

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