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source: rtems/c/src/exec/score/cpu/hppa1.1/hppa.h @ 4ca27cf

4.104.114.84.95

Last change on this file since 4ca27cf was 88d594a, checked in by Joel Sherrill <joel.sherrill@…>, on 05/24/95 at 21:39:42
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1	/*
2	* @(#)hppa.h 1.7 - 95/05/16
3	*
4	*
5	* Description:
6	*
7	* Definitions for HP PA Risc
8	* ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
9	*
10	* COPYRIGHT (c) 1994 by Division Incorporated
11	*
12	* To anyone who acknowledges that this file is provided "AS IS"
13	* without any express or implied warranty:
14	* permission to use, copy, modify, and distribute this file
15	* for any purpose is hereby granted without fee, provided that
16	* the above copyright notice and this notice appears in all
17	* copies, and that the name of Division Incorporated not be
18	* used in advertising or publicity pertaining to distribution
19	* of the software without specific, written prior permission.
20	* Division Incorporated makes no representations about the
21	* suitability of this software for any purpose.
22	*
23	*
24	* Note:
25	* This file is included by both C and assembler code ( -DASM )
26	*
27	* hppa.h,v 1.2 1995/05/09 20:11:40 joel Exp
28	*/
29
30	#ifndef _INCLUDE_HPPA_H
31	#define _INCLUDE_HPPA_H
32
33	#if defined(__cplusplus)
34	extern "C" {
35	#endif
36
37	/*
38	* The following define the CPU Family and Model within the family
39	*
40	* NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
41	* with the name of the appropriate macro for this target CPU.
42	*/
43
44	#ifdef hppa1_1
45	#undef hppa1_1
46	#endif
47	#define hppa1_1
48
49	#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
50	#undef REPLACE_THIS_WITH_THE_CPU_MODEL
51	#endif
52	#define REPLACE_THIS_WITH_THE_CPU_MODEL
53
54	#ifdef REPLACE_THIS_WITH_THE_BSP
55	#undef REPLACE_THIS_WITH_THE_BSP
56	#endif
57	#define REPLACE_THIS_WITH_THE_BSP
58
59	/*
60	* This section contains the information required to build
61	* RTEMS for a particular member of the Hewlett Packard
62	* PA-RISC family. It does this by setting variables to
63	* indicate which implementation dependent features are
64	* present in a particular member of the family.
65	*/
66
67	#if defined(hppa7100)
68
69	#define RTEMS_MODEL_NAME "hppa 7100"
70
71	#elif defined(hppa7200)
72
73	#define RTEMS_MODEL_NAME "hppa 7200"
74
75	#else
76
77	#error "Unsupported CPU Model"
78
79	#endif
80
81	/*
82	* Define the name of the CPU family.
83	*/
84
85	#define CPU_NAME "HP PA-RISC 1.1"
86
87
88	/*
89	* Processor Status Word (PSW) Masks
90	*/
91
92	#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
93	#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
94	#define HPPA_PSW_r2 0x20000000 /* reserved */
95	#define HPPA_PSW_r3 0x10000000 /* reserved */
96	#define HPPA_PSW_r4 0x08000000 /* reserved */
97	#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
98	#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
99	#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
100	#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
101	#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
102	#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
103	#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
104	#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
105	#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
106	#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
107	#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
108	#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
109	#define HPPA_PSW_r24 0x00000080 /* reserved */
110	#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
111	#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
112	#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
113	#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
114	#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
115	#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
116	#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
117	/* Low-Priority Machine Check */
118	/* Interruption Enable */
119
120	/*
121	* HPPA traps and interrupts
122	* basic layout. Note numbers do not denote priority
123	*
124	* 0-31 basic traps and interrupts defined by HPPA architecture
125	* 32-63 32 external interrupts
126	* 64-... bsp defined
127	*/
128
129	#define HPPA_INTERRUPT_NON_EXISTENT 0
130	/* group 1 */
131	#define HPPA_INTERRUPT_HIGH_PRIORITY_MACHINE_CHECK 1
132	/* group 2 */
133	#define HPPA_INTERRUPT_POWER_FAIL 2
134	#define HPPA_INTERRUPT_RECOVERY_COUNTER 3
135	#define HPPA_INTERRUPT_EXTERNAL_INTERRUPT 4
136	#define HPPA_INTERRUPT_LOW_PRIORITY_MACHINE_CHECK 5
137	#define HPPA_INTERRUPT_PERFORMANCE_MONITOR 29
138	/* group 3 */
139	#define HPPA_INTERRUPT_INSTRUCTION_TLB_MISS 6
140	#define HPPA_INTERRUPT_INSTRUCTION_MEMORY_PROTECTION 7
141	#define HPPA_INTERRUPT_INSTRUCTION_DEBUG 30
142	#define HPPA_INTERRUPT_ILLEGAL_INSTRUCTION 8
143	#define HPPA_INTERRUPT_BREAK_INSTRUCTION 9
144	#define HPPA_INTERRUPT_PRIVILEGED_OPERATION 10
145	#define HPPA_INTERRUPT_PRIVILEGED_REGISTER 11
146	#define HPPA_INTERRUPT_OVERFLOW 12
147	#define HPPA_INTERRUPT_CONDITIONAL 13
148	#define HPPA_INTERRUPT_ASSIST_EXCEPTION 14
149	#define HPPA_INTERRUPT_DATA_TLB_MISS 15
150	#define HPPA_INTERRUPT_NON_ACCESS_INSTRUCTION_TLB_MISS 16
151	#define HPPA_INTERRUPT_NON_ACCESS_DATA_TLB_MISS 17
152	#define HPPA_INTERRUPT_DATA_MEMORY_ACCESS_RIGHTS 26
153	#define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION_ID 27
154	#define HPPA_INTERRUPT_UNALIGNED_DATA_REFERENCE 28
155	#define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION 18
156	#define HPPA_INTERRUPT_DATA_MEMORY_BREAK 19
157	#define HPPA_INTERRUPT_TLB_DIRTY_BIT 20
158	#define HPPA_INTERRUPT_PAGE_REFERENCE 21
159	#define HPPA_INTERRUPT_DATA_DEBUG 31
160	#define HPPA_INTERRUPT_ASSIST_EMULATION 22
161	/* group 4 */
162	#define HPPA_INTERRUPT_HIGHER_PRIVILEGE_TRANSFER 23
163	#define HPPA_INTERRUPT_LOWER_PRIVILEGE_TRANSFER 24
164	#define HPPA_INTERRUPT_TAKEN_BRANCH 25
165
166	#define HPPA_INTERRUPT_ON_CHIP_MAX 31
167
168	/* External Interrupts via interrupt 4 */
169
170	#define HPPA_INTERRUPT_EXTERNAL_BASE 32
171
172	#define HPPA_INTERRUPT_EXTERNAL_0 32
173	#define HPPA_INTERRUPT_EXTERNAL_1 33
174	#define HPPA_INTERRUPT_EXTERNAL_2 34
175	#define HPPA_INTERRUPT_EXTERNAL_3 35
176	#define HPPA_INTERRUPT_EXTERNAL_4 36
177	#define HPPA_INTERRUPT_EXTERNAL_5 37
178	#define HPPA_INTERRUPT_EXTERNAL_6 38
179	#define HPPA_INTERRUPT_EXTERNAL_7 39
180	#define HPPA_INTERRUPT_EXTERNAL_8 40
181	#define HPPA_INTERRUPT_EXTERNAL_9 41
182	#define HPPA_INTERRUPT_EXTERNAL_10 42
183	#define HPPA_INTERRUPT_EXTERNAL_11 43
184	#define HPPA_INTERRUPT_EXTERNAL_12 44
185	#define HPPA_INTERRUPT_EXTERNAL_13 45
186	#define HPPA_INTERRUPT_EXTERNAL_14 46
187	#define HPPA_INTERRUPT_EXTERNAL_15 47
188	#define HPPA_INTERRUPT_EXTERNAL_16 48
189	#define HPPA_INTERRUPT_EXTERNAL_17 49
190	#define HPPA_INTERRUPT_EXTERNAL_18 50
191	#define HPPA_INTERRUPT_EXTERNAL_19 51
192	#define HPPA_INTERRUPT_EXTERNAL_20 52
193	#define HPPA_INTERRUPT_EXTERNAL_21 53
194	#define HPPA_INTERRUPT_EXTERNAL_22 54
195	#define HPPA_INTERRUPT_EXTERNAL_23 55
196	#define HPPA_INTERRUPT_EXTERNAL_24 56
197	#define HPPA_INTERRUPT_EXTERNAL_25 57
198	#define HPPA_INTERRUPT_EXTERNAL_26 58
199	#define HPPA_INTERRUPT_EXTERNAL_27 59
200	#define HPPA_INTERRUPT_EXTERNAL_28 60
201	#define HPPA_INTERRUPT_EXTERNAL_29 61
202	#define HPPA_INTERRUPT_EXTERNAL_30 62
203	#define HPPA_INTERRUPT_EXTERNAL_31 63
204
205	#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
206	#define HPPA_EXTERNAL_INTERRUPTS 32
207
208	/* BSP defined interrupts begin here */
209
210	#define HPPA_INTERRUPT_MAX 64
211
212	/*
213	* Cache characteristics
214	*/
215
216	#define HPPA_CACHELINE_SIZE 32
217	#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
218
219
220	/*
221	* Inline macros for misc. interesting opcodes
222	*/
223
224	/* generate a global label */
225	#define HPPA_ASM_LABEL(label) \
226	asm(".export " label ", ! .label " label);
227
228	/* Return From Interrupt RFI */
229	#define HPPA_ASM_RFI() asm volatile ("rfi")
230
231	/* Set System Mask SSM i,t */
232	#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
233	: "=r" (gr) \
234	: "i" (i))
235	/* Reset System Mask RSM i,t */
236	#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
237	: "=r" (gr) \
238	: "i" (i))
239	/* Move To System Mask MTSM r */
240	#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
241	: : "r" (gr))
242
243	/* Load Space Identifier LDSID (s,b),t */
244	#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
245	: "=r" (grt) \
246	: "i" (sr), \
247	"r" (grb))
248
249	/*
250	* Gcc extended asm doesn't really allow for treatment of space registers
251	* as "registers", so we have to use "i" format.
252	* Unfortunately this means that the "=" constraint is not available.
253	*/
254
255	/* Move To Space Register MTSP r,sr */
256	#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
257	: : "i" (sr), \
258	"r" (gr))
259
260	/* Move From Space Register MFSP sr,t */
261	#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
262	: "=r" (gr) \
263	: "i" (sr))
264
265	/* Move To Control register MTCTL r,t */
266	#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
267	: : "i" (cr), \
268	"r" (gr))
269
270	/* Move From Control register MFCTL r,t */
271	#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
272	: "=r" (gr) \
273	: "i" (cr))
274
275	/* Synchronize caches SYNC */
276	#define HPPA_ASM_SYNC() asm volatile ("sync")
277
278	/* Probe Read Access PROBER (s,b),r,t */
279	#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
280	asm volatile ("prober (%1,%2),%3,%0" \
281	: "=r" (grt) \
282	: "i" (sr), \
283	"r" (groff), \
284	"r" (gracc))
285
286	/* Probe Read Access Immediate PROBERI (s,b),i,t*/
287	#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
288	asm volatile ("proberi (%1,%2),%3,%0" \
289	: "=r" (grt) \
290	: "i" (sr), \
291	"r" (groff), \
292	"i" (iacc))
293
294	/* Probe Write Access PROBEW (s,b),r,t */
295	#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
296	asm volatile ("probew (%1,%2),%3,%0" \
297	: "=r" (grt) \
298	: "i" (sr), \
299	"r" (groff), \
300	"r" (gracc))
301
302	/* Probe Write Access Immediate PROBEWI (s,b),i,t */
303	#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
304	asm volatile ("probewi (%1,%2),%3,%0" \
305	: "=r" (grt) \
306	: "i" (sr), \
307	"r" (groff), \
308	"i" (iacc))
309
310	/* Load Physical Address LPA x(s,b),t */
311	#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
312	: "=r" (grt) \
313	: "i" (sr), \
314	"r" (grb))
315
316	/* Load Coherence Index LCI x(s,b),t */
317	/* AKA: Load Hash Address LHA x(s,b),t */
318	#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
319	: "=r" (grt) \
320	: "r" (grx),\
321	"i" (sr), \
322	"r" (grb))
323	#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
324
325	/* Purge Data Tlb PDTLB x(s,b) */
326	#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
327	: : "r" (grx), \
328	"i" (sr), \
329	"r" (grb))
330
331	/* Purge Instruction Tlb PITLB x(s,b) */
332	#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
333	: : "r" (grx), \
334	"i" (sr), \
335	"r" (grb))
336
337	/* Purge Data Tlb Entry PDTLBE x(s,b) */
338	#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
339	: : "r" (grx), \
340	"i" (sr), \
341	"r" (grb))
342
343	/* Purge Instruction Tlb Entry PITLBE x(s,b) */
344	#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
345	: : "r" (grx), \
346	"i" (sr), \
347	"r" (grb))
348
349
350	/* Insert Data TLB Address IDTLBA r,(s,b) */
351	#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
352	: : "r" (gr), \
353	"i" (sr), \
354	"r" (grb))
355
356	/* Insert Instruction TLB Address IITLBA r,(s,b) */
357	#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
358	: : "r" (gr), \
359	"i" (sr), \
360	"r" (grb))
361
362	/* Insert Data TLB Protection IDTLBP r,(s,b) */
363	#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
364	: : "r" (gr), \
365	"i" (sr), \
366	"r" (grb))
367
368	/* Insert Instruction TLB Protection IITLBP r,(s,b) */
369	#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
370	: : "r" (gr), \
371	"i" (sr), \
372	"r" (grb))
373
374	/* Purge Data Cache PDC x(s,b) */
375	#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
376	: : "r" (grx), \
377	"i" (sr), \
378	"r" (grb))
379
380	/* Flush Data Cache FDC x(s,b) */
381	#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
382	: : "r" (grx), \
383	"i" (sr), \
384	"r" (grb))
385
386	/* Flush Instruction Cache FDC x(s,b) */
387	#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
388	: : "r" (grx), \
389	"i" (sr), \
390	"r" (grb))
391
392	/* Flush Data Cache Entry FDCE x(s,b) */
393	#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
394	: : "r" (grx), \
395	"i" (sr), \
396	"r" (grb))
397
398	/* Flush Instruction Cache Entry FICE x(s,b) */
399	#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
400	: : "r" (grx), \
401	"i" (sr), \
402	"r" (grb))
403
404	/* Break BREAK i5,i13 */
405	#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
406	: : "i" (i5), \
407	"i" (i13))
408
409	/* Load and Clear Word Short LDCWS d(s,b),t */
410	#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
411	: "=r" (grt) \
412	: "i" (i), \
413	"i" (sr), \
414	"r" (grb))
415
416	/* Load and Clear Word Indexed LDCWX x(s,b),t */
417	#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
418	: "=r" (grt) \
419	: "r" (grx), \
420	"i" (sr), \
421	"r" (grb))
422
423	/* Load Word Absolute Short LDWAS d(b),t */
424	/* NOTE: "short" here means "short displacement" */
425	#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
426	: "=r" (gr) \
427	: "i" (disp), \
428	"r" (grbase))
429
430	/* Store Word Absolute Short STWAS r,d(b) */
431	/* NOTE: "short" here means "short displacement" */
432	#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
433	: : "r" (gr), \
434	"i" (disp), \
435	"r" (grbase))
436
437	/*
438	* Swap bytes
439	* REFERENCE: PA72000 TRM -- Appendix C
440	*/
441	#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
442	" shd %1,%1,16,%0 \n\
443	dep %0,15,8,%0 \n\
444	shd %1,%0,8,%0" \
445	: "=r" (swapped) \
446	: "r" (value) \
447	)
448
449
450	/* 72000 Diagnose instructions follow
451	* These macros assume gas knows about these instructions.
452	* gas2.2.u1 did not.
453	* I added them to my copy and installed it locally.
454	*
455	* There are very special requirements for these guys
456	* ref: TRM 6.1.3 Programming Constraints
457	*
458	* The macros below handle the following rules
459	*
460	* Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
461	* Must never be nullified (hence the leading nop)
462	* NOP must preced every RDD,RDT,WDD,WDT,RDTLB
463	* Instruction preceeding GR_SHDW must not set any of the GR's saved
464	*
465	* The macros do NOT deal with the following problems
466	* doubled DIAGNOSE instructions must not straddle a page boundary
467	* if code translation enabled. (since 2nd could trap on ITLB)
468	* If you care about DHIT and DPE bits of DR0, then
469	* No store instruction in the 2 insn window before RDD
470	*/
471
472
473	/* Move To CPU/DIAG register MTCPU r,t */
474	#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
475	" mtcpu %1,%0 \n" \
476	" mtcpu %1,%0" \
477	: : "i" (dr), \
478	"r" (gr))
479
480	/* Move From CPU/DIAG register MFCPU r,t */
481	#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
482	" mfcpu %1,%0\n" \
483	" mfcpu %1,%0" \
484	: "=r" (gr) \
485	: "i" (dr))
486
487	/* Transfer of Control Enable TOC_EN */
488	#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
489	" tocen")
490
491	/* Transfer of Control Disable TOC_DIS */
492	#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
493	" tocdis")
494
495	/* Shadow Registers to General Register SHDW_GR */
496	#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
497	" shdwgr" \
498	::: "r1" "r8" "r9" "r16" \
499	"r17" "r24" "r25")
500
501	/* General Registers to Shadow Register GR_SHDW */
502	#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
503	" grshdw \n" \
504	" grshdw")
505
506	/*
507	* Definitions of special registers for use by the above macros.
508	*/
509
510	/* Hardware Space Registers */
511	#define HPPA_SR0 0
512	#define HPPA_SR1 1
513	#define HPPA_SR2 2
514	#define HPPA_SR3 3
515	#define HPPA_SR4 4
516	#define HPPA_SR5 5
517	#define HPPA_SR6 6
518	#define HPPA_SR7 7
519
520	/* Hardware Control Registers */
521	#define HPPA_CR0 0
522	#define HPPA_RCTR 0 /* Recovery Counter Register */
523
524	#define HPPA_CR8 8 /* Protection ID 1 */
525	#define HPPA_PIDR1 8
526
527	#define HPPA_CR9 9 /* Protection ID 2 */
528	#define HPPA_PIDR2 9
529
530	#define HPPA_CR10 10
531	#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
532
533	#define HPPA_CR11 11
534	#define HPPA_SAR 11 /* Shift Amount Register */
535
536	#define HPPA_CR12 12
537	#define HPPA_PIDR3 12 /* Protection ID 3 */
538
539	#define HPPA_CR13 13
540	#define HPPA_PIDR4 13 /* Protection ID 4 */
541
542	#define HPPA_CR14 14
543	#define HPPA_IVA 14 /* Interrupt Vector Address */
544
545	#define HPPA_CR15 15
546	#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
547
548	#define HPPA_CR16 16
549	#define HPPA_ITMR 16 /* Interval Timer */
550
551	#define HPPA_CR17 17
552	#define HPPA_PCSQ 17 /* Program Counter Space queue */
553
554	#define HPPA_CR18 18
555	#define HPPA_PCOQ 18 /* Program Counter Offset queue */
556
557	#define HPPA_CR19 19
558	#define HPPA_IIR 19 /* Interruption Instruction Register */
559
560	#define HPPA_CR20 20
561	#define HPPA_ISR 20 /* Interruption Space Register */
562
563	#define HPPA_CR21 21
564	#define HPPA_IOR 21 /* Interruption Offset Register */
565
566	#define HPPA_CR22 22
567	#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
568
569	#define HPPA_CR23 23
570	#define HPPA_EIRR 23 /* External Interrupt Request */
571
572	#define HPPA_CR24 24
573	#define HPPA_PPDA 24 /* Physcial Page Directory Address */
574	#define HPPA_TR0 24 /* Temporary register 0 */
575
576	#define HPPA_CR25 25
577	#define HPPA_HTA 25 /* Hash Table Address */
578	#define HPPA_TR1 25 /* Temporary register 1 */
579
580	#define HPPA_CR26 26
581	#define HPPA_TR2 26 /* Temporary register 2 */
582
583	#define HPPA_CR27 27
584	#define HPPA_TR3 27 /* Temporary register 3 */
585
586	#define HPPA_CR28 28
587	#define HPPA_TR4 28 /* Temporary register 4 */
588
589	#define HPPA_CR29 29
590	#define HPPA_TR5 29 /* Temporary register 5 */
591
592	#define HPPA_CR30 30
593	#define HPPA_TR6 30 /* Temporary register 6 */
594
595	#define HPPA_CR31 31
596	#define HPPA_CPUID 31 /* MP identifier */
597
598	/*
599	* Diagnose registers
600	*/
601
602	#define HPPA_DR0 0
603	#define HPPA_DR1 1
604	#define HPPA_DR8 8
605	#define HPPA_DR24 24
606	#define HPPA_DR25 25
607
608	/*
609	* Tear apart a break instruction to find its type.
610	*/
611	#define HPPA_BREAK5(x) ((x) & 0x1F)
612	#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
613
614	/* assemble a break instruction */
615	#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) \| (((i13) & 0x1FFF) << 13))
616
617
618	#ifndef ASM
619
620	/*
621	* static inline utility functions to get at control registers
622	*/
623
624	#define EMIT_GET_CONTROL(name, reg) \
625	static __inline__ unsigned int \
626	get_ ## name (void) \
627	{ \
628	unsigned int value; \
629	HPPA_ASM_MFCTL(reg, value); \
630	return value; \
631	}
632
633	#define EMIT_SET_CONTROL(name, reg) \
634	static __inline__ unsigned int \
635	set_ ## name (unsigned int new_value) \
636	{ \
637	HPPA_ASM_MTCTL(new_value, reg); \
638	}
639
640	#define EMIT_CONTROLS(name, reg) \
641	EMIT_GET_CONTROL(name, reg) \
642	EMIT_SET_CONTROL(name, reg)
643
644	EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
645	EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
646	EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
647	EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
648	EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
649	EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
650	EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
651	EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
652	EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
653	EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
654	EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
655	EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
656	EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
657	EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
658	EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
659	EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
660	EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
661	EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
662	EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
663	EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
664	EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
665	EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
666	EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
667	EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
668	EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
669	EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
670
671	/*
672	* If and How to invoke the debugger (a ROM debugger generally)
673	*/
674
675	#ifdef SIMHPPA_ROM
676	/* invoke the pflow debugger */
677	#define CPU_INVOKE_DEBUGGER \
678	do { \
679	extern void debugger_break(void); \
680	debugger_break(); \
681	} while (0)
682	#endif
683
684
685	#endif /* ASM */
686
687	#ifdef __cplusplus
688	}
689	#endif
690
691	#endif /* ! _INCLUDE_HPPA_H */
692

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