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source: rtems/c/src/exec/score/cpu/hppa1.1/hppa.h @ 3652ad35

4.104.114.84.95

Last change on this file since 3652ad35 was 3652ad35, checked in by Joel Sherrill <joel.sherrill@…>, on 09/19/95 at 14:53:29
Minor bug fixes to get all targets compilable and running. The single biggest changes were the expansion of the workspace size macro to include other types of objects and the increase in the minimum stack size for most CPUs.
Property mode set to `100644`
File size: 28.5 KB

Line
1	/*
2	* @(#)hppa.h 1.9 - 95/06/28
3	*
4	*
5	* Description:
6	*
7	* Definitions for HP PA Risc
8	* ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
9	*
10	* COPYRIGHT (c) 1994 by Division Incorporated
11	*
12	* To anyone who acknowledges that this file is provided "AS IS"
13	* without any express or implied warranty:
14	* permission to use, copy, modify, and distribute this file
15	* for any purpose is hereby granted without fee, provided that
16	* the above copyright notice and this notice appears in all
17	* copies, and that the name of Division Incorporated not be
18	* used in advertising or publicity pertaining to distribution
19	* of the software without specific, written prior permission.
20	* Division Incorporated makes no representations about the
21	* suitability of this software for any purpose.
22	*
23	*
24	* Note:
25	* This file is included by both C and assembler code ( -DASM )
26	*
27	* $Id$
28	*/
29
30	#ifndef _INCLUDE_HPPA_H
31	#define _INCLUDE_HPPA_H
32
33	#if defined(__cplusplus)
34	extern "C" {
35	#endif
36
37	/*
38	* The following define the CPU Family and Model within the family
39	*
40	* NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
41	* with the name of the appropriate macro for this target CPU.
42	*/
43
44	#ifdef hppa1_1
45	#undef hppa1_1
46	#endif
47	#define hppa1_1
48
49	#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
50	#undef REPLACE_THIS_WITH_THE_CPU_MODEL
51	#endif
52	#define REPLACE_THIS_WITH_THE_CPU_MODEL
53
54	#ifdef REPLACE_THIS_WITH_THE_BSP
55	#undef REPLACE_THIS_WITH_THE_BSP
56	#endif
57	#define REPLACE_THIS_WITH_THE_BSP
58
59	/*
60	* This section contains the information required to build
61	* RTEMS for a particular member of the Hewlett Packard
62	* PA-RISC family. It does this by setting variables to
63	* indicate which implementation dependent features are
64	* present in a particular member of the family.
65	*/
66
67	#if !defined(RTEMS_MODEL_NAME)
68
69	#if defined(hppa7100)
70
71	#define RTEMS_MODEL_NAME "hppa 7100"
72
73	#elif defined(hppa7200)
74
75	#define RTEMS_MODEL_NAME "hppa 7200"
76
77	#else
78
79	#error "Unsupported CPU Model"
80
81	#endif
82
83	#endif /* !defined(RTEMS_MODEL_NAME) */
84
85	/*
86	* Define the name of the CPU family.
87	*/
88
89	#if !defined(CPU_NAME)
90	#define CPU_NAME "HP PA-RISC 1.1"
91	#endif
92
93	/*
94	* Processor Status Word (PSW) Masks
95	*/
96
97	#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
98	#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
99	#define HPPA_PSW_r2 0x20000000 /* reserved */
100	#define HPPA_PSW_r3 0x10000000 /* reserved */
101	#define HPPA_PSW_r4 0x08000000 /* reserved */
102	#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
103	#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
104	#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
105	#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
106	#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
107	#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
108	#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
109	#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
110	#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
111	#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
112	#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
113	#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
114	#define HPPA_PSW_r24 0x00000080 /* reserved */
115	#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
116	#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
117	#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
118	#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
119	#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
120	#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
121	#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
122	/* Low-Priority Machine Check */
123	/* Interruption Enable */
124
125	/*
126	* HPPA traps and interrupts
127	* basic layout. Note numbers do not denote priority
128	*
129	* 0-31 basic traps and interrupts defined by HPPA architecture
130	* 32-63 32 external interrupts
131	* 64-... bsp defined
132	*/
133
134	#define HPPA_INTERRUPT_NON_EXISTENT 0
135	/* group 1 */
136	#define HPPA_INTERRUPT_HIGH_PRIORITY_MACHINE_CHECK 1
137	/* group 2 */
138	#define HPPA_INTERRUPT_POWER_FAIL 2
139	#define HPPA_INTERRUPT_RECOVERY_COUNTER 3
140	#define HPPA_INTERRUPT_EXTERNAL_INTERRUPT 4
141	#define HPPA_INTERRUPT_LOW_PRIORITY_MACHINE_CHECK 5
142	#define HPPA_INTERRUPT_PERFORMANCE_MONITOR 29
143	/* group 3 */
144	#define HPPA_INTERRUPT_INSTRUCTION_TLB_MISS 6
145	#define HPPA_INTERRUPT_INSTRUCTION_MEMORY_PROTECTION 7
146	#define HPPA_INTERRUPT_INSTRUCTION_DEBUG 30
147	#define HPPA_INTERRUPT_ILLEGAL_INSTRUCTION 8
148	#define HPPA_INTERRUPT_BREAK_INSTRUCTION 9
149	#define HPPA_INTERRUPT_PRIVILEGED_OPERATION 10
150	#define HPPA_INTERRUPT_PRIVILEGED_REGISTER 11
151	#define HPPA_INTERRUPT_OVERFLOW 12
152	#define HPPA_INTERRUPT_CONDITIONAL 13
153	#define HPPA_INTERRUPT_ASSIST_EXCEPTION 14
154	#define HPPA_INTERRUPT_DATA_TLB_MISS 15
155	#define HPPA_INTERRUPT_NON_ACCESS_INSTRUCTION_TLB_MISS 16
156	#define HPPA_INTERRUPT_NON_ACCESS_DATA_TLB_MISS 17
157	#define HPPA_INTERRUPT_DATA_MEMORY_ACCESS_RIGHTS 26
158	#define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION_ID 27
159	#define HPPA_INTERRUPT_UNALIGNED_DATA_REFERENCE 28
160	#define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION 18
161	#define HPPA_INTERRUPT_DATA_MEMORY_BREAK 19
162	#define HPPA_INTERRUPT_TLB_DIRTY_BIT 20
163	#define HPPA_INTERRUPT_PAGE_REFERENCE 21
164	#define HPPA_INTERRUPT_DATA_DEBUG 31
165	#define HPPA_INTERRUPT_ASSIST_EMULATION 22
166	/* group 4 */
167	#define HPPA_INTERRUPT_HIGHER_PRIVILEGE_TRANSFER 23
168	#define HPPA_INTERRUPT_LOWER_PRIVILEGE_TRANSFER 24
169	#define HPPA_INTERRUPT_TAKEN_BRANCH 25
170
171	#define HPPA_INTERRUPT_ON_CHIP_MAX 31
172
173	/* External Interrupts via interrupt 4 */
174
175	#define HPPA_INTERRUPT_EXTERNAL_BASE 32
176
177	#define HPPA_INTERRUPT_EXTERNAL_0 32
178	#define HPPA_INTERRUPT_EXTERNAL_1 33
179	#define HPPA_INTERRUPT_EXTERNAL_2 34
180	#define HPPA_INTERRUPT_EXTERNAL_3 35
181	#define HPPA_INTERRUPT_EXTERNAL_4 36
182	#define HPPA_INTERRUPT_EXTERNAL_5 37
183	#define HPPA_INTERRUPT_EXTERNAL_6 38
184	#define HPPA_INTERRUPT_EXTERNAL_7 39
185	#define HPPA_INTERRUPT_EXTERNAL_8 40
186	#define HPPA_INTERRUPT_EXTERNAL_9 41
187	#define HPPA_INTERRUPT_EXTERNAL_10 42
188	#define HPPA_INTERRUPT_EXTERNAL_11 43
189	#define HPPA_INTERRUPT_EXTERNAL_12 44
190	#define HPPA_INTERRUPT_EXTERNAL_13 45
191	#define HPPA_INTERRUPT_EXTERNAL_14 46
192	#define HPPA_INTERRUPT_EXTERNAL_15 47
193	#define HPPA_INTERRUPT_EXTERNAL_16 48
194	#define HPPA_INTERRUPT_EXTERNAL_17 49
195	#define HPPA_INTERRUPT_EXTERNAL_18 50
196	#define HPPA_INTERRUPT_EXTERNAL_19 51
197	#define HPPA_INTERRUPT_EXTERNAL_20 52
198	#define HPPA_INTERRUPT_EXTERNAL_21 53
199	#define HPPA_INTERRUPT_EXTERNAL_22 54
200	#define HPPA_INTERRUPT_EXTERNAL_23 55
201	#define HPPA_INTERRUPT_EXTERNAL_24 56
202	#define HPPA_INTERRUPT_EXTERNAL_25 57
203	#define HPPA_INTERRUPT_EXTERNAL_26 58
204	#define HPPA_INTERRUPT_EXTERNAL_27 59
205	#define HPPA_INTERRUPT_EXTERNAL_28 60
206	#define HPPA_INTERRUPT_EXTERNAL_29 61
207	#define HPPA_INTERRUPT_EXTERNAL_30 62
208	#define HPPA_INTERRUPT_EXTERNAL_31 63
209
210	#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
211	#define HPPA_EXTERNAL_INTERRUPTS 32
212
213	/* BSP defined interrupts begin here */
214
215	#define HPPA_INTERRUPT_MAX 64
216
217	/*
218	* Cache characteristics
219	*/
220
221	#define HPPA_CACHELINE_SIZE 32
222	#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
223
224
225	/*
226	* Inline macros for misc. interesting opcodes
227	*/
228
229	/* generate a global label */
230	#define HPPA_ASM_LABEL(label) \
231	asm(".export " label ", ! .label " label);
232
233	/* Return From Interrupt RFI */
234	#define HPPA_ASM_RFI() asm volatile ("rfi")
235
236	/* Set System Mask SSM i,t */
237	#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
238	: "=r" (gr) \
239	: "i" (i))
240	/* Reset System Mask RSM i,t */
241	#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
242	: "=r" (gr) \
243	: "i" (i))
244	/* Move To System Mask MTSM r */
245	#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
246	: : "r" (gr))
247
248	/* Load Space Identifier LDSID (s,b),t */
249	#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
250	: "=r" (grt) \
251	: "i" (sr), \
252	"r" (grb))
253
254	/*
255	* Gcc extended asm doesn't really allow for treatment of space registers
256	* as "registers", so we have to use "i" format.
257	* Unfortunately this means that the "=" constraint is not available.
258	*/
259
260	/* Move To Space Register MTSP r,sr */
261	#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
262	: : "i" (sr), \
263	"r" (gr))
264
265	/* Move From Space Register MFSP sr,t */
266	#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
267	: "=r" (gr) \
268	: "i" (sr))
269
270	/* Move To Control register MTCTL r,t */
271	#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
272	: : "i" (cr), \
273	"r" (gr))
274
275	/* Move From Control register MFCTL r,t */
276	#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
277	: "=r" (gr) \
278	: "i" (cr))
279
280	/* Synchronize caches SYNC */
281	#define HPPA_ASM_SYNC() asm volatile ("sync")
282
283	/* Probe Read Access PROBER (s,b),r,t */
284	#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
285	asm volatile ("prober (%1,%2),%3,%0" \
286	: "=r" (grt) \
287	: "i" (sr), \
288	"r" (groff), \
289	"r" (gracc))
290
291	/* Probe Read Access Immediate PROBERI (s,b),i,t*/
292	#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
293	asm volatile ("proberi (%1,%2),%3,%0" \
294	: "=r" (grt) \
295	: "i" (sr), \
296	"r" (groff), \
297	"i" (iacc))
298
299	/* Probe Write Access PROBEW (s,b),r,t */
300	#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
301	asm volatile ("probew (%1,%2),%3,%0" \
302	: "=r" (grt) \
303	: "i" (sr), \
304	"r" (groff), \
305	"r" (gracc))
306
307	/* Probe Write Access Immediate PROBEWI (s,b),i,t */
308	#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
309	asm volatile ("probewi (%1,%2),%3,%0" \
310	: "=r" (grt) \
311	: "i" (sr), \
312	"r" (groff), \
313	"i" (iacc))
314
315	/* Load Physical Address LPA x(s,b),t */
316	#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
317	: "=r" (grt) \
318	: "i" (sr), \
319	"r" (grb))
320
321	/* Load Coherence Index LCI x(s,b),t */
322	/* AKA: Load Hash Address LHA x(s,b),t */
323	#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
324	: "=r" (grt) \
325	: "r" (grx),\
326	"i" (sr), \
327	"r" (grb))
328	#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
329
330	/* Purge Data Tlb PDTLB x(s,b) */
331	#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
332	: : "r" (grx), \
333	"i" (sr), \
334	"r" (grb))
335
336	/* Purge Instruction Tlb PITLB x(s,b) */
337	#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
338	: : "r" (grx), \
339	"i" (sr), \
340	"r" (grb))
341
342	/* Purge Data Tlb Entry PDTLBE x(s,b) */
343	#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
344	: : "r" (grx), \
345	"i" (sr), \
346	"r" (grb))
347
348	/* Purge Instruction Tlb Entry PITLBE x(s,b) */
349	#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
350	: : "r" (grx), \
351	"i" (sr), \
352	"r" (grb))
353
354
355	/* Insert Data TLB Address IDTLBA r,(s,b) */
356	#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
357	: : "r" (gr), \
358	"i" (sr), \
359	"r" (grb))
360
361	/* Insert Instruction TLB Address IITLBA r,(s,b) */
362	#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
363	: : "r" (gr), \
364	"i" (sr), \
365	"r" (grb))
366
367	/* Insert Data TLB Protection IDTLBP r,(s,b) */
368	#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
369	: : "r" (gr), \
370	"i" (sr), \
371	"r" (grb))
372
373	/* Insert Instruction TLB Protection IITLBP r,(s,b) */
374	#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
375	: : "r" (gr), \
376	"i" (sr), \
377	"r" (grb))
378
379	/* Purge Data Cache PDC x(s,b) */
380	#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
381	: : "r" (grx), \
382	"i" (sr), \
383	"r" (grb))
384
385	/* Flush Data Cache FDC x(s,b) */
386	#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
387	: : "r" (grx), \
388	"i" (sr), \
389	"r" (grb))
390
391	/* Flush Instruction Cache FDC x(s,b) */
392	#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
393	: : "r" (grx), \
394	"i" (sr), \
395	"r" (grb))
396
397	/* Flush Data Cache Entry FDCE x(s,b) */
398	#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
399	: : "r" (grx), \
400	"i" (sr), \
401	"r" (grb))
402
403	/* Flush Instruction Cache Entry FICE x(s,b) */
404	#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
405	: : "r" (grx), \
406	"i" (sr), \
407	"r" (grb))
408
409	/* Break BREAK i5,i13 */
410	#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
411	: : "i" (i5), \
412	"i" (i13))
413
414	/* Load and Clear Word Short LDCWS d(s,b),t */
415	#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
416	: "=r" (grt) \
417	: "i" (i), \
418	"i" (sr), \
419	"r" (grb))
420
421	/* Load and Clear Word Indexed LDCWX x(s,b),t */
422	#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
423	: "=r" (grt) \
424	: "r" (grx), \
425	"i" (sr), \
426	"r" (grb))
427
428	/* Load Word Absolute Short LDWAS d(b),t */
429	/* NOTE: "short" here means "short displacement" */
430	#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
431	: "=r" (gr) \
432	: "i" (disp), \
433	"r" (grbase))
434
435	/* Store Word Absolute Short STWAS r,d(b) */
436	/* NOTE: "short" here means "short displacement" */
437	#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
438	: : "r" (gr), \
439	"i" (disp), \
440	"r" (grbase))
441
442	/*
443	* Swap bytes
444	* REFERENCE: PA72000 TRM -- Appendix C
445	*/
446	#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
447	" shd %1,%1,16,%0 \n\
448	dep %0,15,8,%0 \n\
449	shd %1,%0,8,%0" \
450	: "=r" (swapped) \
451	: "r" (value) \
452	)
453
454
455	/* 72000 Diagnose instructions follow
456	* These macros assume gas knows about these instructions.
457	* gas2.2.u1 did not.
458	* I added them to my copy and installed it locally.
459	*
460	* There are very special requirements for these guys
461	* ref: TRM 6.1.3 Programming Constraints
462	*
463	* The macros below handle the following rules
464	*
465	* Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
466	* Must never be nullified (hence the leading nop)
467	* NOP must preced every RDD,RDT,WDD,WDT,RDTLB
468	* Instruction preceeding GR_SHDW must not set any of the GR's saved
469	*
470	* The macros do NOT deal with the following problems
471	* doubled DIAGNOSE instructions must not straddle a page boundary
472	* if code translation enabled. (since 2nd could trap on ITLB)
473	* If you care about DHIT and DPE bits of DR0, then
474	* No store instruction in the 2 insn window before RDD
475	*/
476
477
478	/* Move To CPU/DIAG register MTCPU r,t */
479	#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
480	" mtcpu %1,%0 \n" \
481	" mtcpu %1,%0" \
482	: : "i" (dr), \
483	"r" (gr))
484
485	/* Move From CPU/DIAG register MFCPU r,t */
486	#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
487	" mfcpu %1,%0\n" \
488	" mfcpu %1,%0" \
489	: "=r" (gr) \
490	: "i" (dr))
491
492	/* Transfer of Control Enable TOC_EN */
493	#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
494	" tocen")
495
496	/* Transfer of Control Disable TOC_DIS */
497	#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
498	" tocdis")
499
500	/* Shadow Registers to General Register SHDW_GR */
501	#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
502	" shdwgr" \
503	::: "r1" "r8" "r9" "r16" \
504	"r17" "r24" "r25")
505
506	/* General Registers to Shadow Register GR_SHDW */
507	#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
508	" grshdw \n" \
509	" grshdw")
510
511	/*
512	* Definitions of special registers for use by the above macros.
513	*/
514
515	/* Hardware Space Registers */
516	#define HPPA_SR0 0
517	#define HPPA_SR1 1
518	#define HPPA_SR2 2
519	#define HPPA_SR3 3
520	#define HPPA_SR4 4
521	#define HPPA_SR5 5
522	#define HPPA_SR6 6
523	#define HPPA_SR7 7
524
525	/* Hardware Control Registers */
526	#define HPPA_CR0 0
527	#define HPPA_RCTR 0 /* Recovery Counter Register */
528
529	#define HPPA_CR8 8 /* Protection ID 1 */
530	#define HPPA_PIDR1 8
531
532	#define HPPA_CR9 9 /* Protection ID 2 */
533	#define HPPA_PIDR2 9
534
535	#define HPPA_CR10 10
536	#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
537
538	#define HPPA_CR11 11
539	#define HPPA_SAR 11 /* Shift Amount Register */
540
541	#define HPPA_CR12 12
542	#define HPPA_PIDR3 12 /* Protection ID 3 */
543
544	#define HPPA_CR13 13
545	#define HPPA_PIDR4 13 /* Protection ID 4 */
546
547	#define HPPA_CR14 14
548	#define HPPA_IVA 14 /* Interrupt Vector Address */
549
550	#define HPPA_CR15 15
551	#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
552
553	#define HPPA_CR16 16
554	#define HPPA_ITMR 16 /* Interval Timer */
555
556	#define HPPA_CR17 17
557	#define HPPA_PCSQ 17 /* Program Counter Space queue */
558
559	#define HPPA_CR18 18
560	#define HPPA_PCOQ 18 /* Program Counter Offset queue */
561
562	#define HPPA_CR19 19
563	#define HPPA_IIR 19 /* Interruption Instruction Register */
564
565	#define HPPA_CR20 20
566	#define HPPA_ISR 20 /* Interruption Space Register */
567
568	#define HPPA_CR21 21
569	#define HPPA_IOR 21 /* Interruption Offset Register */
570
571	#define HPPA_CR22 22
572	#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
573
574	#define HPPA_CR23 23
575	#define HPPA_EIRR 23 /* External Interrupt Request */
576
577	#define HPPA_CR24 24
578	#define HPPA_PPDA 24 /* Physcial Page Directory Address */
579	#define HPPA_TR0 24 /* Temporary register 0 */
580
581	#define HPPA_CR25 25
582	#define HPPA_HTA 25 /* Hash Table Address */
583	#define HPPA_TR1 25 /* Temporary register 1 */
584
585	#define HPPA_CR26 26
586	#define HPPA_TR2 26 /* Temporary register 2 */
587
588	#define HPPA_CR27 27
589	#define HPPA_TR3 27 /* Temporary register 3 */
590
591	#define HPPA_CR28 28
592	#define HPPA_TR4 28 /* Temporary register 4 */
593
594	#define HPPA_CR29 29
595	#define HPPA_TR5 29 /* Temporary register 5 */
596
597	#define HPPA_CR30 30
598	#define HPPA_TR6 30 /* Temporary register 6 */
599
600	#define HPPA_CR31 31
601	#define HPPA_CPUID 31 /* MP identifier */
602
603	/*
604	* Diagnose registers
605	*/
606
607	#define HPPA_DR0 0
608	#define HPPA_DR1 1
609	#define HPPA_DR8 8
610	#define HPPA_DR24 24
611	#define HPPA_DR25 25
612
613	/*
614	* Tear apart a break instruction to find its type.
615	*/
616	#define HPPA_BREAK5(x) ((x) & 0x1F)
617	#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
618
619	/* assemble a break instruction */
620	#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) \| (((i13) & 0x1FFF) << 13))
621
622
623	#ifndef ASM
624
625	/*
626	* static inline utility functions to get at control registers
627	*/
628
629	#define EMIT_GET_CONTROL(name, reg) \
630	static __inline__ unsigned int \
631	get_ ## name (void) \
632	{ \
633	unsigned int value; \
634	HPPA_ASM_MFCTL(reg, value); \
635	return value; \
636	}
637
638	#define EMIT_SET_CONTROL(name, reg) \
639	static __inline__ void \
640	set_ ## name (unsigned int new_value) \
641	{ \
642	HPPA_ASM_MTCTL(new_value, reg); \
643	}
644
645	#define EMIT_CONTROLS(name, reg) \
646	EMIT_GET_CONTROL(name, reg) \
647	EMIT_SET_CONTROL(name, reg)
648
649	EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
650	EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
651	EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
652	EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
653	EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
654	EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
655	EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
656	EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
657	EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
658	EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
659	EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
660	EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
661	EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
662	EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
663	EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
664	EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
665	EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
666	EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
667	EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
668	EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
669	EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
670	EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
671	EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
672	EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
673	EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
674	EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
675
676	/*
677	* If and How to invoke the debugger (a ROM debugger generally)
678	*/
679
680	#ifdef SIMHPPA_ROM
681	/* invoke the pflow debugger */
682	#define CPU_INVOKE_DEBUGGER \
683	do { \
684	extern void debugger_break(void); \
685	debugger_break(); \
686	} while (0)
687	#endif
688
689
690	#endif /* ASM */
691
692	#ifdef __cplusplus
693	}
694	#endif
695
696	#endif /* ! _INCLUDE_HPPA_H */
697

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