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source: rtems/c/src/exec/score/cpu/hppa1.1/hppa.h @ ca201c9

4.104.114.84.95

Last change on this file since ca201c9 was ca201c9, checked in by Joel Sherrill <joel.sherrill@…>, on 12/05/95 at 15:28:12
minor changes so it would compile
Property mode set to `100644`
File size: 29.6 KB

Rev	Line
[ac7d5ef0]	1	/*
[11290355]	2	* @(#)hppa.h 1.13 - 95/09/21
[ac7d5ef0]	3	*
	4	*
	5	* Description:
	6	*
	7	* Definitions for HP PA Risc
	8	* ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
	9	*
	10	* COPYRIGHT (c) 1994 by Division Incorporated
	11	*
	12	* To anyone who acknowledges that this file is provided "AS IS"
	13	* without any express or implied warranty:
	14	* permission to use, copy, modify, and distribute this file
	15	* for any purpose is hereby granted without fee, provided that
	16	* the above copyright notice and this notice appears in all
	17	* copies, and that the name of Division Incorporated not be
	18	* used in advertising or publicity pertaining to distribution
	19	* of the software without specific, written prior permission.
	20	* Division Incorporated makes no representations about the
	21	* suitability of this software for any purpose.
	22	*
	23	*
	24	* Note:
	25	* This file is included by both C and assembler code ( -DASM )
	26	*
[eb5a7e07]	27	* $Id$
[ac7d5ef0]	28	*/
	29
	30	#ifndef _INCLUDE_HPPA_H
	31	#define _INCLUDE_HPPA_H
	32
	33	#if defined(__cplusplus)
	34	extern "C" {
	35	#endif
	36
	37	/*
	38	* The following define the CPU Family and Model within the family
	39	*
	40	* NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
	41	* with the name of the appropriate macro for this target CPU.
	42	*/
	43
[88d594a]	44	#ifdef hppa1_1
	45	#undef hppa1_1
	46	#endif
[ac7d5ef0]	47	#define hppa1_1
[88d594a]	48
	49	#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
	50	#undef REPLACE_THIS_WITH_THE_CPU_MODEL
	51	#endif
[ac7d5ef0]	52	#define REPLACE_THIS_WITH_THE_CPU_MODEL
[88d594a]	53
	54	#ifdef REPLACE_THIS_WITH_THE_BSP
	55	#undef REPLACE_THIS_WITH_THE_BSP
	56	#endif
[ac7d5ef0]	57	#define REPLACE_THIS_WITH_THE_BSP
	58
	59	/*
	60	* This section contains the information required to build
	61	* RTEMS for a particular member of the Hewlett Packard
	62	* PA-RISC family. It does this by setting variables to
	63	* indicate which implementation dependent features are
	64	* present in a particular member of the family.
	65	*/
	66
[ca201c9]	67	#if !defined(CPU_MODEL_NAME)
[216ed54]	68
[ac7d5ef0]	69	#if defined(hppa7100)
	70
[ca201c9]	71	#define CPU_MODEL_NAME "hppa 7100"
[ac7d5ef0]	72
	73	#elif defined(hppa7200)
	74
[ca201c9]	75	#define CPU_MODEL_NAME "hppa 7200"
[ac7d5ef0]	76
	77	#else
	78
[ca201c9]	79	#define CPU_MODEL_NAME Unsupported CPU Model /* cause an error on usage */
[ac7d5ef0]	80
	81	#endif
[216ed54]	82
[ca201c9]	83	#endif /* !defined(CPU_MODEL_NAME) */
[216ed54]	84
[ac7d5ef0]	85	/*
	86	* Define the name of the CPU family.
	87	*/
	88
[216ed54]	89	#if !defined(CPU_NAME)
[ac7d5ef0]	90	#define CPU_NAME "HP PA-RISC 1.1"
[216ed54]	91	#endif
[ac7d5ef0]	92
	93	/*
	94	* Processor Status Word (PSW) Masks
	95	*/
	96
	97	#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
	98	#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
	99	#define HPPA_PSW_r2 0x20000000 /* reserved */
	100	#define HPPA_PSW_r3 0x10000000 /* reserved */
	101	#define HPPA_PSW_r4 0x08000000 /* reserved */
	102	#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
	103	#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
	104	#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
	105	#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
	106	#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
	107	#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
	108	#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
	109	#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
	110	#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
	111	#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
	112	#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
	113	#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
	114	#define HPPA_PSW_r24 0x00000080 /* reserved */
	115	#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
	116	#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
	117	#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
	118	#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
	119	#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
	120	#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
	121	#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
	122	/* Low-Priority Machine Check */
	123	/* Interruption Enable */
	124
	125	/*
	126	* HPPA traps and interrupts
	127	* basic layout. Note numbers do not denote priority
	128	*
	129	* 0-31 basic traps and interrupts defined by HPPA architecture
	130	* 32-63 32 external interrupts
	131	* 64-... bsp defined
	132	*/
	133
	134	#define HPPA_INTERRUPT_NON_EXISTENT 0
	135	/* group 1 */
	136	#define HPPA_INTERRUPT_HIGH_PRIORITY_MACHINE_CHECK 1
	137	/* group 2 */
	138	#define HPPA_INTERRUPT_POWER_FAIL 2
	139	#define HPPA_INTERRUPT_RECOVERY_COUNTER 3
	140	#define HPPA_INTERRUPT_EXTERNAL_INTERRUPT 4
	141	#define HPPA_INTERRUPT_LOW_PRIORITY_MACHINE_CHECK 5
	142	#define HPPA_INTERRUPT_PERFORMANCE_MONITOR 29
	143	/* group 3 */
	144	#define HPPA_INTERRUPT_INSTRUCTION_TLB_MISS 6
	145	#define HPPA_INTERRUPT_INSTRUCTION_MEMORY_PROTECTION 7
	146	#define HPPA_INTERRUPT_INSTRUCTION_DEBUG 30
	147	#define HPPA_INTERRUPT_ILLEGAL_INSTRUCTION 8
	148	#define HPPA_INTERRUPT_BREAK_INSTRUCTION 9
	149	#define HPPA_INTERRUPT_PRIVILEGED_OPERATION 10
	150	#define HPPA_INTERRUPT_PRIVILEGED_REGISTER 11
	151	#define HPPA_INTERRUPT_OVERFLOW 12
	152	#define HPPA_INTERRUPT_CONDITIONAL 13
	153	#define HPPA_INTERRUPT_ASSIST_EXCEPTION 14
	154	#define HPPA_INTERRUPT_DATA_TLB_MISS 15
	155	#define HPPA_INTERRUPT_NON_ACCESS_INSTRUCTION_TLB_MISS 16
	156	#define HPPA_INTERRUPT_NON_ACCESS_DATA_TLB_MISS 17
	157	#define HPPA_INTERRUPT_DATA_MEMORY_ACCESS_RIGHTS 26
	158	#define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION_ID 27
	159	#define HPPA_INTERRUPT_UNALIGNED_DATA_REFERENCE 28
	160	#define HPPA_INTERRUPT_DATA_MEMORY_PROTECTION 18
	161	#define HPPA_INTERRUPT_DATA_MEMORY_BREAK 19
	162	#define HPPA_INTERRUPT_TLB_DIRTY_BIT 20
	163	#define HPPA_INTERRUPT_PAGE_REFERENCE 21
	164	#define HPPA_INTERRUPT_DATA_DEBUG 31
	165	#define HPPA_INTERRUPT_ASSIST_EMULATION 22
	166	/* group 4 */
	167	#define HPPA_INTERRUPT_HIGHER_PRIVILEGE_TRANSFER 23
	168	#define HPPA_INTERRUPT_LOWER_PRIVILEGE_TRANSFER 24
	169	#define HPPA_INTERRUPT_TAKEN_BRANCH 25
	170
	171	#define HPPA_INTERRUPT_ON_CHIP_MAX 31
	172
	173	/* External Interrupts via interrupt 4 */
	174
	175	#define HPPA_INTERRUPT_EXTERNAL_BASE 32
	176
	177	#define HPPA_INTERRUPT_EXTERNAL_0 32
	178	#define HPPA_INTERRUPT_EXTERNAL_1 33
	179	#define HPPA_INTERRUPT_EXTERNAL_2 34
	180	#define HPPA_INTERRUPT_EXTERNAL_3 35
	181	#define HPPA_INTERRUPT_EXTERNAL_4 36
	182	#define HPPA_INTERRUPT_EXTERNAL_5 37
	183	#define HPPA_INTERRUPT_EXTERNAL_6 38
	184	#define HPPA_INTERRUPT_EXTERNAL_7 39
	185	#define HPPA_INTERRUPT_EXTERNAL_8 40
	186	#define HPPA_INTERRUPT_EXTERNAL_9 41
	187	#define HPPA_INTERRUPT_EXTERNAL_10 42
	188	#define HPPA_INTERRUPT_EXTERNAL_11 43
	189	#define HPPA_INTERRUPT_EXTERNAL_12 44
	190	#define HPPA_INTERRUPT_EXTERNAL_13 45
	191	#define HPPA_INTERRUPT_EXTERNAL_14 46
	192	#define HPPA_INTERRUPT_EXTERNAL_15 47
	193	#define HPPA_INTERRUPT_EXTERNAL_16 48
	194	#define HPPA_INTERRUPT_EXTERNAL_17 49
	195	#define HPPA_INTERRUPT_EXTERNAL_18 50
	196	#define HPPA_INTERRUPT_EXTERNAL_19 51
	197	#define HPPA_INTERRUPT_EXTERNAL_20 52
	198	#define HPPA_INTERRUPT_EXTERNAL_21 53
	199	#define HPPA_INTERRUPT_EXTERNAL_22 54
	200	#define HPPA_INTERRUPT_EXTERNAL_23 55
	201	#define HPPA_INTERRUPT_EXTERNAL_24 56
	202	#define HPPA_INTERRUPT_EXTERNAL_25 57
	203	#define HPPA_INTERRUPT_EXTERNAL_26 58
	204	#define HPPA_INTERRUPT_EXTERNAL_27 59
	205	#define HPPA_INTERRUPT_EXTERNAL_28 60
	206	#define HPPA_INTERRUPT_EXTERNAL_29 61
	207	#define HPPA_INTERRUPT_EXTERNAL_30 62
	208	#define HPPA_INTERRUPT_EXTERNAL_31 63
	209
	210	#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
	211	#define HPPA_EXTERNAL_INTERRUPTS 32
	212
	213	/* BSP defined interrupts begin here */
	214
	215	#define HPPA_INTERRUPT_MAX 64
	216
[88d594a]	217	/*
	218	* Cache characteristics
	219	*/
	220
	221	#define HPPA_CACHELINE_SIZE 32
	222	#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
	223
	224
[11290355]	225	/*
	226	* TLB characteristics
	227	*
	228	* Flags and Access Control layout for using TLB protection insertion
	229	*
	230	* 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
	231	* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
	232	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
	233	* \|?\|?\|T\|D\|B\|type \|PL1\|Pl2\|U\| access id \|?\|
	234	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
	235	*
	236	*/
	237
	238	/*
	239	* Access rights (type + PL1 + PL2)
	240	*/
	241	#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */
	242	#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */
	243	#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */
	244	#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */
	245	#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */
	246	#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */
	247	#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */
	248	#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */
	249
	250
[ac7d5ef0]	251	/*
	252	* Inline macros for misc. interesting opcodes
	253	*/
	254
	255	/* generate a global label */
	256	#define HPPA_ASM_LABEL(label) \
	257	asm(".export " label ", ! .label " label);
	258
	259	/* Return From Interrupt RFI */
	260	#define HPPA_ASM_RFI() asm volatile ("rfi")
	261
	262	/* Set System Mask SSM i,t */
	263	#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
	264	: "=r" (gr) \
	265	: "i" (i))
	266	/* Reset System Mask RSM i,t */
	267	#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
	268	: "=r" (gr) \
	269	: "i" (i))
	270	/* Move To System Mask MTSM r */
	271	#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
	272	: : "r" (gr))
	273
	274	/* Load Space Identifier LDSID (s,b),t */
	275	#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
	276	: "=r" (grt) \
	277	: "i" (sr), \
	278	"r" (grb))
	279
	280	/*
	281	* Gcc extended asm doesn't really allow for treatment of space registers
	282	* as "registers", so we have to use "i" format.
	283	* Unfortunately this means that the "=" constraint is not available.
	284	*/
	285
	286	/* Move To Space Register MTSP r,sr */
	287	#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
	288	: : "i" (sr), \
	289	"r" (gr))
	290
	291	/* Move From Space Register MFSP sr,t */
	292	#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
	293	: "=r" (gr) \
	294	: "i" (sr))
	295
	296	/* Move To Control register MTCTL r,t */
	297	#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
	298	: : "i" (cr), \
	299	"r" (gr))
	300
	301	/* Move From Control register MFCTL r,t */
	302	#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
	303	: "=r" (gr) \
	304	: "i" (cr))
	305
	306	/* Synchronize caches SYNC */
	307	#define HPPA_ASM_SYNC() asm volatile ("sync")
	308
	309	/* Probe Read Access PROBER (s,b),r,t */
	310	#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
	311	asm volatile ("prober (%1,%2),%3,%0" \
	312	: "=r" (grt) \
	313	: "i" (sr), \
	314	"r" (groff), \
	315	"r" (gracc))
	316
	317	/* Probe Read Access Immediate PROBERI (s,b),i,t*/
	318	#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
	319	asm volatile ("proberi (%1,%2),%3,%0" \
	320	: "=r" (grt) \
	321	: "i" (sr), \
	322	"r" (groff), \
	323	"i" (iacc))
	324
	325	/* Probe Write Access PROBEW (s,b),r,t */
	326	#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
	327	asm volatile ("probew (%1,%2),%3,%0" \
	328	: "=r" (grt) \
	329	: "i" (sr), \
	330	"r" (groff), \
	331	"r" (gracc))
	332
	333	/* Probe Write Access Immediate PROBEWI (s,b),i,t */
	334	#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
	335	asm volatile ("probewi (%1,%2),%3,%0" \
	336	: "=r" (grt) \
	337	: "i" (sr), \
	338	"r" (groff), \
	339	"i" (iacc))
	340
	341	/* Load Physical Address LPA x(s,b),t */
	342	#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
	343	: "=r" (grt) \
	344	: "i" (sr), \
	345	"r" (grb))
	346
	347	/* Load Coherence Index LCI x(s,b),t */
	348	/* AKA: Load Hash Address LHA x(s,b),t */
	349	#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
	350	: "=r" (grt) \
	351	: "r" (grx),\
	352	"i" (sr), \
	353	"r" (grb))
	354	#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
	355
	356	/* Purge Data Tlb PDTLB x(s,b) */
	357	#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
	358	: : "r" (grx), \
	359	"i" (sr), \
	360	"r" (grb))
	361
	362	/* Purge Instruction Tlb PITLB x(s,b) */
	363	#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
	364	: : "r" (grx), \
	365	"i" (sr), \
	366	"r" (grb))
	367
	368	/* Purge Data Tlb Entry PDTLBE x(s,b) */
	369	#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
	370	: : "r" (grx), \
	371	"i" (sr), \
	372	"r" (grb))
	373
	374	/* Purge Instruction Tlb Entry PITLBE x(s,b) */
	375	#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
	376	: : "r" (grx), \
	377	"i" (sr), \
	378	"r" (grb))
	379
	380
	381	/* Insert Data TLB Address IDTLBA r,(s,b) */
	382	#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
	383	: : "r" (gr), \
	384	"i" (sr), \
	385	"r" (grb))
	386
	387	/* Insert Instruction TLB Address IITLBA r,(s,b) */
	388	#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
	389	: : "r" (gr), \
	390	"i" (sr), \
	391	"r" (grb))
	392
	393	/* Insert Data TLB Protection IDTLBP r,(s,b) */
	394	#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
	395	: : "r" (gr), \
	396	"i" (sr), \
	397	"r" (grb))
	398
	399	/* Insert Instruction TLB Protection IITLBP r,(s,b) */
	400	#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
	401	: : "r" (gr), \
	402	"i" (sr), \
	403	"r" (grb))
	404
	405	/* Purge Data Cache PDC x(s,b) */
	406	#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
	407	: : "r" (grx), \
	408	"i" (sr), \
	409	"r" (grb))
	410
	411	/* Flush Data Cache FDC x(s,b) */
	412	#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
	413	: : "r" (grx), \
	414	"i" (sr), \
	415	"r" (grb))
	416
	417	/* Flush Instruction Cache FDC x(s,b) */
	418	#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
	419	: : "r" (grx), \
	420	"i" (sr), \
	421	"r" (grb))
	422
	423	/* Flush Data Cache Entry FDCE x(s,b) */
	424	#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
	425	: : "r" (grx), \
	426	"i" (sr), \
	427	"r" (grb))
	428
	429	/* Flush Instruction Cache Entry FICE x(s,b) */
	430	#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
	431	: : "r" (grx), \
	432	"i" (sr), \
	433	"r" (grb))
	434
	435	/* Break BREAK i5,i13 */
	436	#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
	437	: : "i" (i5), \
	438	"i" (i13))
	439
	440	/* Load and Clear Word Short LDCWS d(s,b),t */
	441	#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
	442	: "=r" (grt) \
	443	: "i" (i), \
	444	"i" (sr), \
	445	"r" (grb))
	446
	447	/* Load and Clear Word Indexed LDCWX x(s,b),t */
	448	#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
	449	: "=r" (grt) \
	450	: "r" (grx), \
	451	"i" (sr), \
	452	"r" (grb))
	453
	454	/* Load Word Absolute Short LDWAS d(b),t */
	455	/* NOTE: "short" here means "short displacement" */
	456	#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
	457	: "=r" (gr) \
	458	: "i" (disp), \
	459	"r" (grbase))
	460
	461	/* Store Word Absolute Short STWAS r,d(b) */
	462	/* NOTE: "short" here means "short displacement" */
	463	#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
	464	: : "r" (gr), \
	465	"i" (disp), \
	466	"r" (grbase))
	467
	468	/*
	469	* Swap bytes
	470	* REFERENCE: PA72000 TRM -- Appendix C
	471	*/
	472	#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
	473	" shd %1,%1,16,%0 \n\
	474	dep %0,15,8,%0 \n\
	475	shd %1,%0,8,%0" \
	476	: "=r" (swapped) \
	477	: "r" (value) \
	478	)
	479
	480
	481	/* 72000 Diagnose instructions follow
	482	* These macros assume gas knows about these instructions.
	483	* gas2.2.u1 did not.
	484	* I added them to my copy and installed it locally.
	485	*
	486	* There are very special requirements for these guys
	487	* ref: TRM 6.1.3 Programming Constraints
	488	*
	489	* The macros below handle the following rules
	490	*
	491	* Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
	492	* Must never be nullified (hence the leading nop)
	493	* NOP must preced every RDD,RDT,WDD,WDT,RDTLB
	494	* Instruction preceeding GR_SHDW must not set any of the GR's saved
	495	*
	496	* The macros do NOT deal with the following problems
	497	* doubled DIAGNOSE instructions must not straddle a page boundary
	498	* if code translation enabled. (since 2nd could trap on ITLB)
	499	* If you care about DHIT and DPE bits of DR0, then
	500	* No store instruction in the 2 insn window before RDD
	501	*/
	502
	503
	504	/* Move To CPU/DIAG register MTCPU r,t */
	505	#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
	506	" mtcpu %1,%0 \n" \
	507	" mtcpu %1,%0" \
	508	: : "i" (dr), \
	509	"r" (gr))
	510
	511	/* Move From CPU/DIAG register MFCPU r,t */
	512	#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
	513	" mfcpu %1,%0\n" \
	514	" mfcpu %1,%0" \
	515	: "=r" (gr) \
	516	: "i" (dr))
	517
	518	/* Transfer of Control Enable TOC_EN */
	519	#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
	520	" tocen")
	521
	522	/* Transfer of Control Disable TOC_DIS */
	523	#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
	524	" tocdis")
	525
	526	/* Shadow Registers to General Register SHDW_GR */
	527	#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
	528	" shdwgr" \
	529	::: "r1" "r8" "r9" "r16" \
	530	"r17" "r24" "r25")
	531
	532	/* General Registers to Shadow Register GR_SHDW */
	533	#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
	534	" grshdw \n" \
	535	" grshdw")
	536
	537	/*
	538	* Definitions of special registers for use by the above macros.
	539	*/
	540
	541	/* Hardware Space Registers */
[88d594a]	542	#define HPPA_SR0 0
	543	#define HPPA_SR1 1
	544	#define HPPA_SR2 2
	545	#define HPPA_SR3 3
	546	#define HPPA_SR4 4
	547	#define HPPA_SR5 5
	548	#define HPPA_SR6 6
	549	#define HPPA_SR7 7
[ac7d5ef0]	550
	551	/* Hardware Control Registers */
[88d594a]	552	#define HPPA_CR0 0
	553	#define HPPA_RCTR 0 /* Recovery Counter Register */
[ac7d5ef0]	554
[88d594a]	555	#define HPPA_CR8 8 /* Protection ID 1 */
	556	#define HPPA_PIDR1 8
[ac7d5ef0]	557
[88d594a]	558	#define HPPA_CR9 9 /* Protection ID 2 */
	559	#define HPPA_PIDR2 9
[ac7d5ef0]	560
[88d594a]	561	#define HPPA_CR10 10
	562	#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
[ac7d5ef0]	563
[88d594a]	564	#define HPPA_CR11 11
	565	#define HPPA_SAR 11 /* Shift Amount Register */
[ac7d5ef0]	566
[88d594a]	567	#define HPPA_CR12 12
	568	#define HPPA_PIDR3 12 /* Protection ID 3 */
[ac7d5ef0]	569
[88d594a]	570	#define HPPA_CR13 13
	571	#define HPPA_PIDR4 13 /* Protection ID 4 */
[ac7d5ef0]	572
[88d594a]	573	#define HPPA_CR14 14
	574	#define HPPA_IVA 14 /* Interrupt Vector Address */
[ac7d5ef0]	575
[88d594a]	576	#define HPPA_CR15 15
	577	#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
[ac7d5ef0]	578
[88d594a]	579	#define HPPA_CR16 16
	580	#define HPPA_ITMR 16 /* Interval Timer */
[ac7d5ef0]	581
[88d594a]	582	#define HPPA_CR17 17
	583	#define HPPA_PCSQ 17 /* Program Counter Space queue */
[ac7d5ef0]	584
[88d594a]	585	#define HPPA_CR18 18
	586	#define HPPA_PCOQ 18 /* Program Counter Offset queue */
[ac7d5ef0]	587
[88d594a]	588	#define HPPA_CR19 19
	589	#define HPPA_IIR 19 /* Interruption Instruction Register */
[ac7d5ef0]	590
[88d594a]	591	#define HPPA_CR20 20
	592	#define HPPA_ISR 20 /* Interruption Space Register */
[ac7d5ef0]	593
[88d594a]	594	#define HPPA_CR21 21
	595	#define HPPA_IOR 21 /* Interruption Offset Register */
[ac7d5ef0]	596
[88d594a]	597	#define HPPA_CR22 22
	598	#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
[ac7d5ef0]	599
[88d594a]	600	#define HPPA_CR23 23
	601	#define HPPA_EIRR 23 /* External Interrupt Request */
[ac7d5ef0]	602
[88d594a]	603	#define HPPA_CR24 24
	604	#define HPPA_PPDA 24 /* Physcial Page Directory Address */
	605	#define HPPA_TR0 24 /* Temporary register 0 */
[ac7d5ef0]	606
[88d594a]	607	#define HPPA_CR25 25
	608	#define HPPA_HTA 25 /* Hash Table Address */
	609	#define HPPA_TR1 25 /* Temporary register 1 */
[ac7d5ef0]	610
[88d594a]	611	#define HPPA_CR26 26
	612	#define HPPA_TR2 26 /* Temporary register 2 */
[ac7d5ef0]	613
[88d594a]	614	#define HPPA_CR27 27
	615	#define HPPA_TR3 27 /* Temporary register 3 */
[ac7d5ef0]	616
[88d594a]	617	#define HPPA_CR28 28
	618	#define HPPA_TR4 28 /* Temporary register 4 */
[ac7d5ef0]	619
[88d594a]	620	#define HPPA_CR29 29
	621	#define HPPA_TR5 29 /* Temporary register 5 */
[ac7d5ef0]	622
[88d594a]	623	#define HPPA_CR30 30
	624	#define HPPA_TR6 30 /* Temporary register 6 */
[ac7d5ef0]	625
[88d594a]	626	#define HPPA_CR31 31
	627	#define HPPA_CPUID 31 /* MP identifier */
[ac7d5ef0]	628
	629	/*
	630	* Diagnose registers
	631	*/
	632
[88d594a]	633	#define HPPA_DR0 0
	634	#define HPPA_DR1 1
	635	#define HPPA_DR8 8
	636	#define HPPA_DR24 24
	637	#define HPPA_DR25 25
[ac7d5ef0]	638
	639	/*
	640	* Tear apart a break instruction to find its type.
	641	*/
	642	#define HPPA_BREAK5(x) ((x) & 0x1F)
	643	#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
	644
	645	/* assemble a break instruction */
	646	#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) \| (((i13) & 0x1FFF) << 13))
	647
	648
	649	#ifndef ASM
	650
	651	/*
	652	* static inline utility functions to get at control registers
	653	*/
	654
	655	#define EMIT_GET_CONTROL(name, reg) \
	656	static __inline__ unsigned int \
	657	get_ ## name (void) \
	658	{ \
	659	unsigned int value; \
	660	HPPA_ASM_MFCTL(reg, value); \
	661	return value; \
	662	}
	663
	664	#define EMIT_SET_CONTROL(name, reg) \
[3652ad35]	665	static __inline__ void \
[ac7d5ef0]	666	set_ ## name (unsigned int new_value) \
	667	{ \
	668	HPPA_ASM_MTCTL(new_value, reg); \
	669	}
	670
	671	#define EMIT_CONTROLS(name, reg) \
	672	EMIT_GET_CONTROL(name, reg) \
	673	EMIT_SET_CONTROL(name, reg)
	674
[88d594a]	675	EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
	676	EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
	677	EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
	678	EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
	679	EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
	680	EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
	681	EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
	682	EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
	683	EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
	684	EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
	685	EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
	686	EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
	687	EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
	688	EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
	689	EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
	690	EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
	691	EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
	692	EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
	693	EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
	694	EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
	695	EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
	696	EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
	697	EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
	698	EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
	699	EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
	700	EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
[ac7d5ef0]	701
	702	/*
	703	* If and How to invoke the debugger (a ROM debugger generally)
	704	*/
	705
	706	#ifdef SIMHPPA_ROM
	707	/* invoke the pflow debugger */
	708	#define CPU_INVOKE_DEBUGGER \
	709	do { \
	710	extern void debugger_break(void); \
	711	debugger_break(); \
	712	} while (0)
	713	#endif
	714
	715
	716	#endif /* ASM */
	717
	718	#ifdef __cplusplus
	719	}
	720	#endif
	721
	722	#endif /* ! _INCLUDE_HPPA_H */
	723

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