1 | /* |
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2 | * TODO: |
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3 | * Context_switch needs to only save callee save registers |
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4 | * I think this means can skip: r1, r2, r19-29, r31 |
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5 | * Ref: p 3-2 of Procedure Calling Conventions Manual |
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6 | * This should be #ifndef DEBUG so that debugger has |
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7 | * accurate visibility into all registers |
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8 | * |
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9 | * This file contains the assembly code for the HPPA implementation |
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10 | * of RTEMS. |
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11 | * |
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12 | * COPYRIGHT (c) 1994,95 by Division Incorporated |
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13 | * |
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14 | * The license and distribution terms for this file may in |
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15 | * the file LICENSE in this distribution or at |
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16 | * http://www.OARcorp.com/rtems/license.html. |
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17 | * |
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18 | * $Id$ |
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19 | */ |
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20 | |
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21 | #include <rtems/score/hppa.h> |
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22 | #include <rtems/score/cpu_asm.h> |
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23 | #include <rtems/score/cpu.h> |
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24 | #include <rtems/score/offsets.h> |
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25 | |
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26 | .SPACE $PRIVATE$ |
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27 | .SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31 |
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28 | .SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82 |
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29 | .SPACE $TEXT$ |
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30 | .SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44 |
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31 | .SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY |
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32 | .SPACE $TEXT$ |
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33 | .SUBSPA $CODE$ |
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34 | |
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35 | /* |
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36 | * Special register usage for context switch and interrupts |
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37 | * Stay away from %cr28 which is used for TLB misses on 72000 |
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38 | */ |
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39 | |
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40 | isr_arg0 .reg %cr24 |
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41 | isr_r9 .reg %cr25 |
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42 | isr_r8 .reg %cr26 |
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43 | |
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44 | /* |
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45 | * Interrupt stack frame looks like this |
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46 | * |
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47 | * offset item |
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48 | * ----------------------------------------------------------------- |
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49 | * INTEGER_CONTEXT_OFFSET Context_Control |
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50 | * FP_CONTEXT_OFFSET Context_Control_fp |
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51 | * |
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52 | * It is padded out to a multiple of 64 |
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53 | */ |
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54 | |
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55 | |
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56 | /*PAGE^L |
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57 | * void _Generic_ISR_Handler() |
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58 | * |
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59 | * This routine provides the RTEMS interrupt management. |
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60 | * |
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61 | * We jump here from the interrupt vector. |
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62 | * The HPPA hardware has done some stuff for us: |
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63 | * PSW saved in IPSW |
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64 | * PSW set to 0 |
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65 | * PSW[E] set to default (0) |
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66 | * PSW[M] set to 1 iff this is HPMC |
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67 | * |
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68 | * IIA queue is frozen (since PSW[Q] is now 0) |
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69 | * privilege level promoted to 0 |
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70 | * IIR, ISR, IOR potentially updated if PSW[Q] was 1 at trap |
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71 | * registers GR 1,8,9,16,17,24,25 copied to shadow regs |
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72 | * SHR 0 1 2 3 4 5 6 |
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73 | * |
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74 | * Our vector stub (in the BSP) MUST have done the following: |
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75 | * |
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76 | * a) Saved the original %r9 into %isr_r9 (%cr25) |
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77 | * b) Placed the vector number in %r9 |
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78 | * c) Was allowed to also destroy $isr_r8 (%cr26), |
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79 | * but the stub was NOT allowed to destroy any other registers. |
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80 | * |
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81 | * The typical stub sequence (in the BSP) should look like this: |
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82 | * |
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83 | * a) mtctl %r9,isr_r9 ; (save r9 in cr25) |
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84 | * b) ldi vector,%r9 ; (load constant vector number in r9) |
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85 | * c) mtctl %r8,isr_r8 ; (save r8 in cr26) |
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86 | * d) ldil L%MY_BSP_first_level_interrupt_handler,%r8 |
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87 | * e) ldo R%MY_BSP_first_level_interrupt_handler(%r8),%r8 |
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88 | * ; (point to BSP raw handler table) |
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89 | * f) ldwx,s %r9(%r8),%r8 ; (load value from raw handler table) |
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90 | * g) bv 0(%r8) ; (call raw handler: _Generic_ISR_Handler) |
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91 | * h) mfctl isr_r8,%r8 ; (restore r8 from cr26 in delay slot) |
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92 | * |
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93 | * Optionally, steps (c) thru (h) _could_ be replaced with a single |
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94 | * bl,n _Generic_ISR_Handler,%r0 |
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95 | * |
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96 | * |
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97 | */ |
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98 | .EXPORT _Generic_ISR_Handler,ENTRY,PRIV_LEV=0 |
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99 | _Generic_ISR_Handler: |
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100 | .PROC |
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101 | .CALLINFO FRAME=0,NO_CALLS |
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102 | .ENTRY |
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103 | |
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104 | mtctl arg0, isr_arg0 |
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105 | |
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106 | /* |
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107 | * save interrupt state |
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108 | */ |
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109 | mfctl ipsw, arg0 |
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110 | stw arg0, IPSW_OFFSET(sp) |
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111 | |
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112 | mfctl iir, arg0 |
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113 | stw arg0, IIR_OFFSET(sp) |
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114 | |
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115 | mfctl ior, arg0 |
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116 | stw arg0, IOR_OFFSET(sp) |
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117 | |
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118 | mfctl pcoq, arg0 |
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119 | stw arg0, PCOQFRONT_OFFSET(sp) |
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120 | |
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121 | mtctl %r0, pcoq |
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122 | mfctl pcoq, arg0 |
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123 | stw arg0, PCOQBACK_OFFSET(sp) |
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124 | |
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125 | mfctl %sar, arg0 |
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126 | stw arg0, SAR_OFFSET(sp) |
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127 | |
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128 | /* |
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129 | * Build an interrupt frame to hold the contexts we will need. |
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130 | * We have already saved the interrupt items on the stack |
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131 | * |
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132 | * At this point the following registers are damaged wrt the interrupt |
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133 | * reg current value saved value |
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134 | * ------------------------------------------------ |
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135 | * arg0 scratch isr_arg0 (cr24) |
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136 | * r9 vector number isr_r9 (cr25) |
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137 | * |
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138 | * Point to beginning of integer context and |
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139 | * save the integer context |
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140 | */ |
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141 | stw %r1,R1_OFFSET(sp) |
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142 | stw %r2,R2_OFFSET(sp) |
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143 | stw %r3,R3_OFFSET(sp) |
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144 | stw %r4,R4_OFFSET(sp) |
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145 | stw %r5,R5_OFFSET(sp) |
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146 | stw %r6,R6_OFFSET(sp) |
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147 | stw %r7,R7_OFFSET(sp) |
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148 | stw %r8,R8_OFFSET(sp) |
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149 | /* |
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150 | * skip r9 |
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151 | */ |
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152 | stw %r10,R10_OFFSET(sp) |
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153 | stw %r11,R11_OFFSET(sp) |
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154 | stw %r12,R12_OFFSET(sp) |
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155 | stw %r13,R13_OFFSET(sp) |
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156 | stw %r14,R14_OFFSET(sp) |
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157 | stw %r15,R15_OFFSET(sp) |
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158 | stw %r16,R16_OFFSET(sp) |
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159 | stw %r17,R17_OFFSET(sp) |
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160 | stw %r18,R18_OFFSET(sp) |
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161 | stw %r19,R19_OFFSET(sp) |
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162 | stw %r20,R20_OFFSET(sp) |
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163 | stw %r21,R21_OFFSET(sp) |
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164 | stw %r22,R22_OFFSET(sp) |
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165 | stw %r23,R23_OFFSET(sp) |
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166 | stw %r24,R24_OFFSET(sp) |
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167 | stw %r25,R25_OFFSET(sp) |
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168 | /* |
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169 | * skip arg0 |
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170 | */ |
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171 | stw %r27,R27_OFFSET(sp) |
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172 | stw %r28,R28_OFFSET(sp) |
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173 | stw %r29,R29_OFFSET(sp) |
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174 | stw %r30,R30_OFFSET(sp) |
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175 | stw %r31,R31_OFFSET(sp) |
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176 | |
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177 | /* Now most registers are available since they have been saved |
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178 | * |
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179 | * The following items are currently wrong in the integer context |
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180 | * reg current value saved value |
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181 | * ------------------------------------------------ |
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182 | * arg0 scratch isr_arg0 (cr24) |
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183 | * r9 vector number isr_r9 (cr25) |
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184 | * |
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185 | * Fix them |
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186 | */ |
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187 | |
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188 | mfctl isr_arg0,%r3 |
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189 | stw %r3,ARG0_OFFSET(sp) |
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190 | |
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191 | mfctl isr_r9,%r3 |
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192 | stw %r3,R9_OFFSET(sp) |
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193 | |
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194 | /* |
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195 | * At this point we are done with isr_arg0, and isr_r9 control registers |
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196 | * |
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197 | * Prepare to re-enter virtual mode |
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198 | * We need Q in case the interrupt handler enables interrupts |
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199 | */ |
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200 | |
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201 | ldil L%CPU_PSW_DEFAULT, arg0 |
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202 | ldo R%CPU_PSW_DEFAULT(arg0), arg0 |
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203 | mtctl arg0, ipsw |
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204 | |
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205 | /* |
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206 | * Now jump to "rest_of_isr_handler" with the rfi |
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207 | * We are assuming the space queues are all correct already |
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208 | */ |
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209 | |
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210 | ldil L%rest_of_isr_handler, arg0 |
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211 | ldo R%rest_of_isr_handler(arg0), arg0 |
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212 | mtctl arg0, pcoq |
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213 | ldo 4(arg0), arg0 |
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214 | mtctl arg0, pcoq |
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215 | |
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216 | rfi |
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217 | nop |
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218 | |
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219 | /* |
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220 | * At this point we are back in virtual mode and all our |
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221 | * normal addressing is once again ok. |
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222 | * |
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223 | * It is now ok to take an exception or trap |
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224 | */ |
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225 | |
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226 | rest_of_isr_handler: |
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227 | |
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228 | /* |
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229 | * Point to beginning of float context and |
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230 | * save the floating point context -- doing whatever patches are necessary |
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231 | */ |
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232 | |
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233 | .call ARGW0=GR |
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234 | bl _CPU_Save_float_context,%r2 |
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235 | ldo FP_CONTEXT_OFFSET(sp),arg0 |
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236 | |
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237 | /* |
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238 | * save the ptr to interrupt frame as an argument for the interrupt handler |
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239 | */ |
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240 | |
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241 | copy sp, arg1 |
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242 | |
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243 | /* |
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244 | * Advance the frame to point beyond all interrupt contexts (integer & float) |
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245 | * this also includes the pad to align to 64byte stack boundary |
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246 | */ |
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247 | ldo CPU_INTERRUPT_FRAME_SIZE(sp), sp |
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248 | |
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249 | /* |
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250 | * r3 -- &_ISR_Nest_level |
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251 | * r5 -- value _ISR_Nest_level |
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252 | * r4 -- &_Thread_Dispatch_disable_level |
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253 | * r6 -- value _Thread_Dispatch_disable_level |
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254 | * r9 -- vector number |
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255 | */ |
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256 | |
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257 | .import _ISR_Nest_level,data |
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258 | ldil L%_ISR_Nest_level,%r3 |
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259 | ldo R%_ISR_Nest_level(%r3),%r3 |
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260 | ldw 0(%r3),%r5 |
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261 | |
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262 | .import _Thread_Dispatch_disable_level,data |
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263 | ldil L%_Thread_Dispatch_disable_level,%r4 |
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264 | ldo R%_Thread_Dispatch_disable_level(%r4),%r4 |
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265 | ldw 0(%r4),%r6 |
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266 | |
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267 | /* |
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268 | * increment interrupt nest level counter. If outermost interrupt |
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269 | * switch the stack and squirrel away the previous sp. |
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270 | */ |
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271 | addi 1,%r5,%r5 |
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272 | stw %r5, 0(%r3) |
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273 | |
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274 | /* |
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275 | * compute and save new stack (with frame) |
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276 | * just in case we are nested -- simpler this way |
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277 | */ |
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278 | comibf,= 1,%r5,stack_done |
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279 | ldo 128(sp),%r7 |
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280 | |
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281 | /* |
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282 | * Switch to interrupt stack allocated by the interrupt manager (intr.c) |
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283 | */ |
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284 | .import _CPU_Interrupt_stack_low,data |
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285 | ldil L%_CPU_Interrupt_stack_low,%r7 |
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286 | ldw R%_CPU_Interrupt_stack_low(%r7),%r7 |
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287 | ldo 128(%r7),%r7 |
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288 | |
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289 | stack_done: |
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290 | /* |
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291 | * save our current stack pointer where the "old sp" is supposed to be |
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292 | */ |
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293 | stw sp, -4(%r7) |
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294 | /* |
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295 | * and switch stacks (or advance old stack in nested case) |
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296 | */ |
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297 | copy %r7, sp |
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298 | |
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299 | /* |
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300 | * increment the dispatch disable level counter. |
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301 | */ |
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302 | addi 1,%r6,%r6 |
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303 | stw %r6, 0(%r4) |
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304 | |
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305 | /* |
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306 | * load address of user handler |
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307 | * Note: No error checking is done, it is assumed that the |
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308 | * vector table contains a valid address or a stub |
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309 | * spurious handler. |
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310 | */ |
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311 | .import _ISR_Vector_table,data |
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312 | ldil L%_ISR_Vector_table,%r8 |
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313 | ldo R%_ISR_Vector_table(%r8),%r8 |
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314 | ldwx,s %r9(%r8),%r8 |
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315 | |
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316 | /* |
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317 | * invoke user interrupt handler |
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318 | * Interrupts are currently disabled, as per RTEMS convention |
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319 | * The handler has the option of re-enabling interrupts |
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320 | * NOTE: can not use 'bl' since it uses "pc-relative" addressing |
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321 | * and we are using a hard coded address from a table |
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322 | * So... we fudge r2 ourselves (ala dynacall) |
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323 | * arg0 = vector number, arg1 = ptr to rtems_interrupt_frame |
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324 | */ |
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325 | copy %r9, %r26 |
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326 | .call ARGW0=GR, ARGW1=GR |
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327 | blr %r0, rp |
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328 | bv,n 0(%r8) |
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329 | |
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330 | post_user_interrupt_handler: |
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331 | |
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332 | /* |
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333 | * Back from user handler(s) |
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334 | * Disable external interrupts (since the interrupt handler could |
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335 | * have turned them on) and return to the interrupted task stack (assuming |
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336 | * (_ISR_Nest_level == 0) |
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337 | */ |
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338 | |
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339 | rsm HPPA_PSW_I + HPPA_PSW_R, %r0 |
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340 | ldw -4(sp), sp |
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341 | |
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342 | /* |
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343 | * r3 -- (most of) &_ISR_Nest_level |
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344 | * r5 -- value _ISR_Nest_level |
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345 | * r4 -- (most of) &_Thread_Dispatch_disable_level |
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346 | * r6 -- value _Thread_Dispatch_disable_level |
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347 | * r7 -- (most of) &_ISR_Signals_to_thread_executing |
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348 | * r8 -- value _ISR_Signals_to_thread_executing |
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349 | */ |
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350 | |
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351 | .import _ISR_Nest_level,data |
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352 | ldil L%_ISR_Nest_level,%r3 |
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353 | ldw R%_ISR_Nest_level(%r3),%r5 |
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354 | |
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355 | .import _Thread_Dispatch_disable_level,data |
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356 | ldil L%_Thread_Dispatch_disable_level,%r4 |
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357 | ldw R%_Thread_Dispatch_disable_level(%r4),%r6 |
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358 | |
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359 | .import _ISR_Signals_to_thread_executing,data |
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360 | ldil L%_ISR_Signals_to_thread_executing,%r7 |
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361 | |
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362 | /* |
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363 | * decrement isr nest level |
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364 | */ |
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365 | addi -1, %r5, %r5 |
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366 | stw %r5, R%_ISR_Nest_level(%r3) |
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367 | |
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368 | /* |
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369 | * decrement dispatch disable level counter and, if not 0, go on |
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370 | */ |
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371 | addi -1,%r6,%r6 |
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372 | comibf,= 0,%r6,isr_restore |
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373 | stw %r6, R%_Thread_Dispatch_disable_level(%r4) |
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374 | |
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375 | /* |
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376 | * check whether or not a context switch is necessary |
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377 | */ |
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378 | .import _Context_Switch_necessary,data |
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379 | ldil L%_Context_Switch_necessary,%r8 |
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380 | ldw R%_Context_Switch_necessary(%r8),%r8 |
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381 | comibf,=,n 0,%r8,ISR_dispatch |
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382 | |
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383 | /* |
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384 | * check whether or not a context switch is necessary because an ISR |
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385 | * sent signals to the interrupted task |
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386 | */ |
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387 | ldw R%_ISR_Signals_to_thread_executing(%r7),%r8 |
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388 | comibt,=,n 0,%r8,isr_restore |
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389 | |
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390 | |
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391 | /* |
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392 | * OK, something happened while in ISR and we need to switch to a task |
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393 | * other than the one which was interrupted or the |
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394 | * ISR_Signals_to_thread_executing case |
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395 | * We also turn on interrupts, since the interrupted task had them |
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396 | * on (obviously :-) and Thread_Dispatch is happy to leave ints on. |
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397 | */ |
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398 | |
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399 | ISR_dispatch: |
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400 | stw %r0, R%_ISR_Signals_to_thread_executing(%r7) |
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401 | |
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402 | ssm HPPA_PSW_I, %r0 |
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403 | |
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404 | .import _Thread_Dispatch,code |
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405 | .call |
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406 | bl _Thread_Dispatch,%r2 |
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407 | ldo 128(sp),sp |
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408 | |
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409 | ldo -128(sp),sp |
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410 | |
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411 | isr_restore: |
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412 | |
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413 | /* |
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414 | * enable interrupts during most of restore |
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415 | */ |
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416 | ssm HPPA_PSW_I, %r0 |
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417 | |
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418 | /* |
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419 | * Get a pointer to beginning of our stack frame |
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420 | */ |
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421 | ldo -CPU_INTERRUPT_FRAME_SIZE(sp), %arg1 |
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422 | |
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423 | /* |
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424 | * restore float |
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425 | */ |
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426 | .call ARGW0=GR |
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427 | bl _CPU_Restore_float_context,%r2 |
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428 | ldo FP_CONTEXT_OFFSET(%arg1), arg0 |
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429 | |
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430 | copy %arg1, %arg0 |
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431 | |
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432 | /* |
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433 | * ********** FALL THRU ********** |
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434 | */ |
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435 | |
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436 | /* |
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437 | * Jump here from bottom of Context_Switch |
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438 | * Also called directly by _CPU_Context_Restart_self via _Thread_Restart_self |
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439 | * restore interrupt state |
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440 | */ |
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441 | |
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442 | .EXPORT _CPU_Context_restore |
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443 | _CPU_Context_restore: |
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444 | |
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445 | /* |
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446 | * restore integer state |
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447 | */ |
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448 | ldw R1_OFFSET(arg0),%r1 |
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449 | ldw R2_OFFSET(arg0),%r2 |
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450 | ldw R3_OFFSET(arg0),%r3 |
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451 | ldw R4_OFFSET(arg0),%r4 |
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452 | ldw R5_OFFSET(arg0),%r5 |
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453 | ldw R6_OFFSET(arg0),%r6 |
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454 | ldw R7_OFFSET(arg0),%r7 |
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455 | ldw R8_OFFSET(arg0),%r8 |
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456 | ldw R9_OFFSET(arg0),%r9 |
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457 | ldw R10_OFFSET(arg0),%r10 |
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458 | ldw R11_OFFSET(arg0),%r11 |
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459 | ldw R12_OFFSET(arg0),%r12 |
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460 | ldw R13_OFFSET(arg0),%r13 |
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461 | ldw R14_OFFSET(arg0),%r14 |
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462 | ldw R15_OFFSET(arg0),%r15 |
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463 | ldw R16_OFFSET(arg0),%r16 |
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464 | ldw R17_OFFSET(arg0),%r17 |
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465 | ldw R18_OFFSET(arg0),%r18 |
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466 | ldw R19_OFFSET(arg0),%r19 |
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467 | ldw R20_OFFSET(arg0),%r20 |
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468 | ldw R21_OFFSET(arg0),%r21 |
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469 | ldw R22_OFFSET(arg0),%r22 |
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470 | ldw R23_OFFSET(arg0),%r23 |
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471 | ldw R24_OFFSET(arg0),%r24 |
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472 | /* |
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473 | * skipping r25; used as scratch register below |
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474 | * skipping r26 (arg0) until we are done with it |
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475 | */ |
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476 | ldw R27_OFFSET(arg0),%r27 |
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477 | ldw R28_OFFSET(arg0),%r28 |
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478 | ldw R29_OFFSET(arg0),%r29 |
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479 | /* |
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480 | * skipping r30 (sp) until we turn off interrupts |
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481 | */ |
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482 | ldw R31_OFFSET(arg0),%r31 |
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483 | |
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484 | /* |
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485 | * Turn off Q & R & I so we can write r30 and interrupt control registers |
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486 | */ |
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487 | rsm HPPA_PSW_Q + HPPA_PSW_R + HPPA_PSW_I, %r0 |
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488 | |
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489 | /* |
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490 | * now safe to restore r30 |
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491 | */ |
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492 | ldw R30_OFFSET(arg0),%r30 |
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493 | |
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494 | ldw IPSW_OFFSET(arg0), %r25 |
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495 | mtctl %r25, ipsw |
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496 | |
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497 | ldw SAR_OFFSET(arg0), %r25 |
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498 | mtctl %r25, sar |
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499 | |
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500 | ldw PCOQFRONT_OFFSET(arg0), %r25 |
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501 | mtctl %r25, pcoq |
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502 | |
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503 | ldw PCOQBACK_OFFSET(arg0), %r25 |
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504 | mtctl %r25, pcoq |
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505 | |
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506 | /* |
---|
507 | * Load r25 with interrupts off |
---|
508 | */ |
---|
509 | ldw R25_OFFSET(arg0),%r25 |
---|
510 | /* |
---|
511 | * Must load r26 (arg0) last |
---|
512 | */ |
---|
513 | ldw R26_OFFSET(arg0),%r26 |
---|
514 | |
---|
515 | isr_exit: |
---|
516 | rfi |
---|
517 | .EXIT |
---|
518 | .PROCEND |
---|
519 | |
---|
520 | /* |
---|
521 | * This section is used to context switch floating point registers. |
---|
522 | * Ref: 6-35 of Architecture 1.1 |
---|
523 | * |
---|
524 | * NOTE: since integer multiply uses the floating point unit, |
---|
525 | * we have to save/restore fp on every trap. We cannot |
---|
526 | * just try to keep track of fp usage. |
---|
527 | */ |
---|
528 | |
---|
529 | .align 32 |
---|
530 | .EXPORT _CPU_Save_float_context,ENTRY,PRIV_LEV=0 |
---|
531 | _CPU_Save_float_context: |
---|
532 | .PROC |
---|
533 | .CALLINFO FRAME=0,NO_CALLS |
---|
534 | .ENTRY |
---|
535 | fstds,ma %fr0,8(%arg0) |
---|
536 | fstds,ma %fr1,8(%arg0) |
---|
537 | fstds,ma %fr2,8(%arg0) |
---|
538 | fstds,ma %fr3,8(%arg0) |
---|
539 | fstds,ma %fr4,8(%arg0) |
---|
540 | fstds,ma %fr5,8(%arg0) |
---|
541 | fstds,ma %fr6,8(%arg0) |
---|
542 | fstds,ma %fr7,8(%arg0) |
---|
543 | fstds,ma %fr8,8(%arg0) |
---|
544 | fstds,ma %fr9,8(%arg0) |
---|
545 | fstds,ma %fr10,8(%arg0) |
---|
546 | fstds,ma %fr11,8(%arg0) |
---|
547 | fstds,ma %fr12,8(%arg0) |
---|
548 | fstds,ma %fr13,8(%arg0) |
---|
549 | fstds,ma %fr14,8(%arg0) |
---|
550 | fstds,ma %fr15,8(%arg0) |
---|
551 | fstds,ma %fr16,8(%arg0) |
---|
552 | fstds,ma %fr17,8(%arg0) |
---|
553 | fstds,ma %fr18,8(%arg0) |
---|
554 | fstds,ma %fr19,8(%arg0) |
---|
555 | fstds,ma %fr20,8(%arg0) |
---|
556 | fstds,ma %fr21,8(%arg0) |
---|
557 | fstds,ma %fr22,8(%arg0) |
---|
558 | fstds,ma %fr23,8(%arg0) |
---|
559 | fstds,ma %fr24,8(%arg0) |
---|
560 | fstds,ma %fr25,8(%arg0) |
---|
561 | fstds,ma %fr26,8(%arg0) |
---|
562 | fstds,ma %fr27,8(%arg0) |
---|
563 | fstds,ma %fr28,8(%arg0) |
---|
564 | fstds,ma %fr29,8(%arg0) |
---|
565 | fstds,ma %fr30,8(%arg0) |
---|
566 | fstds %fr31,0(%arg0) |
---|
567 | bv 0(%r2) |
---|
568 | addi -(31*8), %arg0, %arg0 ; restore arg0 just for fun |
---|
569 | .EXIT |
---|
570 | .PROCEND |
---|
571 | |
---|
572 | .align 32 |
---|
573 | .EXPORT _CPU_Restore_float_context,ENTRY,PRIV_LEV=0 |
---|
574 | _CPU_Restore_float_context: |
---|
575 | .PROC |
---|
576 | .CALLINFO FRAME=0,NO_CALLS |
---|
577 | .ENTRY |
---|
578 | addi (31*8), %arg0, %arg0 ; point at last double |
---|
579 | fldds 0(%arg0),%fr31 |
---|
580 | fldds,mb -8(%arg0),%fr30 |
---|
581 | fldds,mb -8(%arg0),%fr29 |
---|
582 | fldds,mb -8(%arg0),%fr28 |
---|
583 | fldds,mb -8(%arg0),%fr27 |
---|
584 | fldds,mb -8(%arg0),%fr26 |
---|
585 | fldds,mb -8(%arg0),%fr25 |
---|
586 | fldds,mb -8(%arg0),%fr24 |
---|
587 | fldds,mb -8(%arg0),%fr23 |
---|
588 | fldds,mb -8(%arg0),%fr22 |
---|
589 | fldds,mb -8(%arg0),%fr21 |
---|
590 | fldds,mb -8(%arg0),%fr20 |
---|
591 | fldds,mb -8(%arg0),%fr19 |
---|
592 | fldds,mb -8(%arg0),%fr18 |
---|
593 | fldds,mb -8(%arg0),%fr17 |
---|
594 | fldds,mb -8(%arg0),%fr16 |
---|
595 | fldds,mb -8(%arg0),%fr15 |
---|
596 | fldds,mb -8(%arg0),%fr14 |
---|
597 | fldds,mb -8(%arg0),%fr13 |
---|
598 | fldds,mb -8(%arg0),%fr12 |
---|
599 | fldds,mb -8(%arg0),%fr11 |
---|
600 | fldds,mb -8(%arg0),%fr10 |
---|
601 | fldds,mb -8(%arg0),%fr9 |
---|
602 | fldds,mb -8(%arg0),%fr8 |
---|
603 | fldds,mb -8(%arg0),%fr7 |
---|
604 | fldds,mb -8(%arg0),%fr6 |
---|
605 | fldds,mb -8(%arg0),%fr5 |
---|
606 | fldds,mb -8(%arg0),%fr4 |
---|
607 | fldds,mb -8(%arg0),%fr3 |
---|
608 | fldds,mb -8(%arg0),%fr2 |
---|
609 | fldds,mb -8(%arg0),%fr1 |
---|
610 | bv 0(%r2) |
---|
611 | fldds,mb -8(%arg0),%fr0 |
---|
612 | .EXIT |
---|
613 | .PROCEND |
---|
614 | |
---|
615 | /* |
---|
616 | * These 2 small routines are unused right now. |
---|
617 | * Normally we just go thru _CPU_Save_float_context (and Restore) |
---|
618 | * |
---|
619 | * Here we just deref the ptr and jump up, letting _CPU_Save_float_context |
---|
620 | * do the return for us. |
---|
621 | */ |
---|
622 | |
---|
623 | .EXPORT _CPU_Context_save_fp,ENTRY,PRIV_LEV=0 |
---|
624 | _CPU_Context_save_fp: |
---|
625 | .PROC |
---|
626 | .CALLINFO FRAME=0,NO_CALLS |
---|
627 | .ENTRY |
---|
628 | bl _CPU_Save_float_context, %r0 |
---|
629 | ldw 0(%arg0), %arg0 |
---|
630 | .EXIT |
---|
631 | .PROCEND |
---|
632 | |
---|
633 | .EXPORT _CPU_Context_restore_fp,ENTRY,PRIV_LEV=0 |
---|
634 | _CPU_Context_restore_fp: |
---|
635 | .PROC |
---|
636 | .CALLINFO FRAME=0,NO_CALLS |
---|
637 | .ENTRY |
---|
638 | bl _CPU_Restore_float_context, %r0 |
---|
639 | ldw 0(%arg0), %arg0 |
---|
640 | .EXIT |
---|
641 | .PROCEND |
---|
642 | |
---|
643 | |
---|
644 | /* |
---|
645 | * void _CPU_Context_switch( run_context, heir_context ) |
---|
646 | * |
---|
647 | * This routine performs a normal non-FP context switch. |
---|
648 | */ |
---|
649 | |
---|
650 | .align 32 |
---|
651 | .EXPORT _CPU_Context_switch,ENTRY,PRIV_LEV=0,ARGW0=GR,ARGW1=GR |
---|
652 | _CPU_Context_switch: |
---|
653 | .PROC |
---|
654 | .CALLINFO FRAME=64 |
---|
655 | .ENTRY |
---|
656 | |
---|
657 | /* |
---|
658 | * Save the integer context |
---|
659 | */ |
---|
660 | stw %r1,R1_OFFSET(arg0) |
---|
661 | stw %r2,R2_OFFSET(arg0) |
---|
662 | stw %r3,R3_OFFSET(arg0) |
---|
663 | stw %r4,R4_OFFSET(arg0) |
---|
664 | stw %r5,R5_OFFSET(arg0) |
---|
665 | stw %r6,R6_OFFSET(arg0) |
---|
666 | stw %r7,R7_OFFSET(arg0) |
---|
667 | stw %r8,R8_OFFSET(arg0) |
---|
668 | stw %r9,R9_OFFSET(arg0) |
---|
669 | stw %r10,R10_OFFSET(arg0) |
---|
670 | stw %r11,R11_OFFSET(arg0) |
---|
671 | stw %r12,R12_OFFSET(arg0) |
---|
672 | stw %r13,R13_OFFSET(arg0) |
---|
673 | stw %r14,R14_OFFSET(arg0) |
---|
674 | stw %r15,R15_OFFSET(arg0) |
---|
675 | stw %r16,R16_OFFSET(arg0) |
---|
676 | stw %r17,R17_OFFSET(arg0) |
---|
677 | stw %r18,R18_OFFSET(arg0) |
---|
678 | stw %r19,R19_OFFSET(arg0) |
---|
679 | stw %r20,R20_OFFSET(arg0) |
---|
680 | stw %r21,R21_OFFSET(arg0) |
---|
681 | stw %r22,R22_OFFSET(arg0) |
---|
682 | stw %r23,R23_OFFSET(arg0) |
---|
683 | stw %r24,R24_OFFSET(arg0) |
---|
684 | stw %r25,R25_OFFSET(arg0) |
---|
685 | stw %r26,R26_OFFSET(arg0) |
---|
686 | stw %r27,R27_OFFSET(arg0) |
---|
687 | stw %r28,R28_OFFSET(arg0) |
---|
688 | stw %r29,R29_OFFSET(arg0) |
---|
689 | stw %r30,R30_OFFSET(arg0) |
---|
690 | stw %r31,R31_OFFSET(arg0) |
---|
691 | |
---|
692 | /* |
---|
693 | * fill in interrupt context section |
---|
694 | */ |
---|
695 | stw %r2, PCOQFRONT_OFFSET(%arg0) |
---|
696 | ldo 4(%r2), %r2 |
---|
697 | stw %r2, PCOQBACK_OFFSET(%arg0) |
---|
698 | |
---|
699 | /* |
---|
700 | * Generate a suitable IPSW by using the system default psw |
---|
701 | * with the current low bits added in. |
---|
702 | */ |
---|
703 | |
---|
704 | ldil L%CPU_PSW_DEFAULT, %r2 |
---|
705 | ldo R%CPU_PSW_DEFAULT(%r2), %r2 |
---|
706 | ssm 0, %arg2 |
---|
707 | dep %arg2, 31, 8, %r2 |
---|
708 | stw %r2, IPSW_OFFSET(%arg0) |
---|
709 | |
---|
710 | /* |
---|
711 | * at this point, the running task context is completely saved |
---|
712 | * Now jump to the bottom of the interrupt handler to load the |
---|
713 | * heirs context |
---|
714 | */ |
---|
715 | |
---|
716 | b _CPU_Context_restore |
---|
717 | copy %arg1, %arg0 |
---|
718 | |
---|
719 | .EXIT |
---|
720 | .PROCEND |
---|
721 | |
---|
722 | |
---|
723 | /* |
---|
724 | * Find first bit |
---|
725 | * NOTE: |
---|
726 | * This is used (and written) only for the ready chain code and |
---|
727 | * priority bit maps. |
---|
728 | * Any other use constitutes fraud. |
---|
729 | * Returns first bit from the least significant side. |
---|
730 | * Eg: if input is 0x8001 |
---|
731 | * output will indicate the '1' bit and return 0. |
---|
732 | * This is counter to HPPA bit numbering which calls this |
---|
733 | * bit 31. This way simplifies the macros _CPU_Priority_Mask |
---|
734 | * and _CPU_Priority_Bits_index. |
---|
735 | * |
---|
736 | * NOTE: |
---|
737 | * We just use 16 bit version |
---|
738 | * does not handle zero case |
---|
739 | * |
---|
740 | * Based on the UTAH Mach libc version of ffs. |
---|
741 | */ |
---|
742 | |
---|
743 | .align 32 |
---|
744 | .EXPORT hppa_rtems_ffs,ENTRY,PRIV_LEV=0,ARGW0=GR |
---|
745 | hppa_rtems_ffs: |
---|
746 | .PROC |
---|
747 | .CALLINFO FRAME=0,NO_CALLS |
---|
748 | .ENTRY |
---|
749 | |
---|
750 | #ifdef RETURN_ERROR_ON_ZERO |
---|
751 | comb,= %arg0,%r0,ffsdone ; If arg0 is 0 |
---|
752 | ldi -1,%ret0 ; return -1 |
---|
753 | #endif |
---|
754 | |
---|
755 | #if BITFIELD_SIZE == 32 |
---|
756 | ldi 31,%ret0 ; Set return to high bit |
---|
757 | extru,= %arg0,31,16,%r0 ; If low 16 bits are non-zero |
---|
758 | addi,tr -16,%ret0,%ret0 ; subtract 16 from bitpos |
---|
759 | shd %r0,%arg0,16,%arg0 ; else shift right 16 bits |
---|
760 | #else |
---|
761 | ldi 15,%ret0 ; Set return to high bit |
---|
762 | #endif |
---|
763 | extru,= %arg0,31,8,%r0 ; If low 8 bits are non-zero |
---|
764 | addi,tr -8,%ret0,%ret0 ; subtract 8 from bitpos |
---|
765 | shd %r0,%arg0,8,%arg0 ; else shift right 8 bits |
---|
766 | extru,= %arg0,31,4,%r0 ; If low 4 bits are non-zero |
---|
767 | addi,tr -4,%ret0,%ret0 ; subtract 4 from bitpos |
---|
768 | shd %r0,%arg0,4,%arg0 ; else shift right 4 bits |
---|
769 | extru,= %arg0,31,2,%r0 ; If low 2 bits are non-zero |
---|
770 | addi,tr -2,%ret0,%ret0 ; subtract 2 from bitpos |
---|
771 | shd %r0,%arg0,2,%arg0 ; else shift right 2 bits |
---|
772 | extru,= %arg0,31,1,%r0 ; If low bit is non-zero |
---|
773 | addi -1,%ret0,%ret0 ; subtract 1 from bitpos |
---|
774 | ffsdone: |
---|
775 | bv,n 0(%r2) |
---|
776 | nop |
---|
777 | .EXIT |
---|
778 | .PROCEND |
---|