source: rtems/c/src/exec/score/cpu/hppa1.1/cpu.h @ dff5b40

4.104.114.84.95
Last change on this file since dff5b40 was dff5b40, checked in by Joel Sherrill <joel.sherrill@…>, on 10/06/98 at 20:54:36

Added missing field (idle_task_stack_size) to CPU Table.

  • Property mode set to 100644
File size: 17.8 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 * Note:
13 *      This file is included by both C and assembler code ( -DASM )
14 *
15 *  $Id$
16 */
17
18#ifndef __CPU_h
19#define __CPU_h
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25#include <rtems/score/hppa.h>              /* pick up machine definitions */
26#ifndef ASM
27#include <rtems/score/hppatypes.h>
28#endif
29
30/* conditional compilation parameters */
31
32#define CPU_INLINE_ENABLE_DISPATCH       FALSE
33#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
34
35/*
36 *  RTEMS manages an interrupt stack in software for the HPPA.
37 */
38
39#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
40#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
41#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
42
43/*
44 *  Does the RTEMS invoke the user's ISR with the vector number and
45 *  a pointer to the saved interrupt frame (1) or just the vector
46 *  number (0)?
47 */
48
49#define CPU_ISR_PASSES_FRAME_POINTER 0
50
51/*
52 *  HPPA has hardware FP, it is assumed to exist by GCC so all tasks
53 *  may implicitly use it (especially for integer multiplies).  Because
54 *  the FP context is technically part of the basic integer context
55 *  on this CPU, we cannot use the deferred FP context switch algorithm.
56 */
57
58#define CPU_HARDWARE_FP                  TRUE
59#define CPU_ALL_TASKS_ARE_FP             TRUE
60#define CPU_IDLE_TASK_IS_FP              FALSE
61#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
62
63#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
64#define CPU_STACK_GROWS_UP               TRUE
65#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((__aligned__ (32)))
66
67/*
68 *  Define what is required to specify how the network to host conversion
69 *  routines are handled.
70 */
71
72#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
73#define CPU_BIG_ENDIAN                           TRUE
74#define CPU_LITTLE_ENDIAN                        FALSE
75
76/* constants */
77
78#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
79#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
80
81/*
82 * PSW contstants
83 */
84
85#define CPU_PSW_BASE (HPPA_PSW_C | HPPA_PSW_Q | HPPA_PSW_P | HPPA_PSW_D)
86#define CPU_PSW_INTERRUPTS_ON    (CPU_PSW_BASE | HPPA_PSW_I)
87#define CPU_PSW_INTERRUPTS_OFF   (CPU_PSW_BASE)
88
89#define CPU_PSW_DEFAULT     CPU_PSW_BASE
90
91
92#ifndef ASM
93
94/*
95 * Contexts
96 *
97 *  This means we have the following context items:
98 *    1. task level context stuff::  Context_Control
99 *    2. floating point task stuff:: Context_Control_fp
100 *
101 *  The PA-RISC is very fast so the expense of saving an extra register
102 *  or two is not of great concern at the present.  So we are not making
103 *  a distinction between what is saved during a task switch and what is
104 *  saved at each interrupt.  Plus saving the entire context should make
105 *  it easier to make gdb aware of RTEMS tasks.
106 */
107
108typedef struct {
109    unsigned32 flags;      /* whatever */
110    unsigned32 gr1;        /* scratch -- caller saves */
111    unsigned32 gr2;        /* RP -- return pointer */
112    unsigned32 gr3;        /* scratch -- callee saves */
113    unsigned32 gr4;        /* scratch -- callee saves */
114    unsigned32 gr5;        /* scratch -- callee saves */
115    unsigned32 gr6;        /* scratch -- callee saves */
116    unsigned32 gr7;        /* scratch -- callee saves */
117    unsigned32 gr8;        /* scratch -- callee saves */
118    unsigned32 gr9;        /* scratch -- callee saves */
119    unsigned32 gr10;       /* scratch -- callee saves */
120    unsigned32 gr11;       /* scratch -- callee saves */
121    unsigned32 gr12;       /* scratch -- callee saves */
122    unsigned32 gr13;       /* scratch -- callee saves */
123    unsigned32 gr14;       /* scratch -- callee saves */
124    unsigned32 gr15;       /* scratch -- callee saves */
125    unsigned32 gr16;       /* scratch -- callee saves */
126    unsigned32 gr17;       /* scratch -- callee saves */
127    unsigned32 gr18;       /* scratch -- callee saves */
128    unsigned32 gr19;       /* scratch -- caller saves */
129    unsigned32 gr20;       /* scratch -- caller saves */
130    unsigned32 gr21;       /* scratch -- caller saves */
131    unsigned32 gr22;       /* scratch -- caller saves */
132    unsigned32 gr23;       /* argument 3 */
133    unsigned32 gr24;       /* argument 2 */
134    unsigned32 gr25;       /* argument 1 */
135    unsigned32 gr26;       /* argument 0 */
136    unsigned32 gr27;       /* DP -- global data pointer */
137    unsigned32 gr28;       /* return values -- caller saves */
138    unsigned32 gr29;       /* return values -- caller saves */
139    unsigned32 sp;         /* gr30 */
140    unsigned32 gr31;
141
142    /* Various control registers */
143
144    unsigned32 sar;         /* cr11 */
145    unsigned32 ipsw;        /* cr22; full 32 bits of psw */
146    unsigned32 iir;         /* cr19; interrupt instruction register */
147    unsigned32 ior;         /* cr21; interrupt offset register */
148    unsigned32 isr;         /* cr20; interrupt space register (not used) */
149    unsigned32 pcoqfront;   /* cr18; front que offset */
150    unsigned32 pcoqback;    /* cr18; back que offset */
151    unsigned32 pcsqfront;   /* cr17; front que space (not used) */
152    unsigned32 pcsqback;    /* cr17; back que space (not used) */
153    unsigned32 itimer;      /* cr16; itimer value */
154
155} Context_Control;
156
157
158/* Must be double word aligned.
159 * This will be ok since our allocator returns 8 byte aligned chunks
160 */
161
162typedef struct {
163    double      fr0;        /* status */
164    double      fr1;        /* exception information */
165    double      fr2;        /* exception information */
166    double      fr3;        /* exception information */
167    double      fr4;        /* argument */
168    double      fr5;        /* argument */
169    double      fr6;        /* argument */
170    double      fr7;        /* argument */
171    double      fr8;        /* scratch -- caller saves */
172    double      fr9;        /* scratch -- caller saves */
173    double      fr10;       /* scratch -- caller saves */
174    double      fr11;       /* scratch -- caller saves */
175    double      fr12;       /* callee saves -- (PA-RISC 1.1 CPUs) */
176    double      fr13;       /* callee saves -- (PA-RISC 1.1 CPUs) */
177    double      fr14;       /* callee saves -- (PA-RISC 1.1 CPUs) */
178    double      fr15;       /* callee saves -- (PA-RISC 1.1 CPUs) */
179    double      fr16;       /* callee saves -- (PA-RISC 1.1 CPUs) */
180    double      fr17;       /* callee saves -- (PA-RISC 1.1 CPUs) */
181    double      fr18;       /* callee saves -- (PA-RISC 1.1 CPUs) */
182    double      fr19;       /* callee saves -- (PA-RISC 1.1 CPUs) */
183    double      fr20;       /* callee saves -- (PA-RISC 1.1 CPUs) */
184    double      fr21;       /* callee saves -- (PA-RISC 1.1 CPUs) */
185    double      fr22;       /* caller saves -- (PA-RISC 1.1 CPUs) */
186    double      fr23;       /* caller saves -- (PA-RISC 1.1 CPUs) */
187    double      fr24;       /* caller saves -- (PA-RISC 1.1 CPUs) */
188    double      fr25;       /* caller saves -- (PA-RISC 1.1 CPUs) */
189    double      fr26;       /* caller saves -- (PA-RISC 1.1 CPUs) */
190    double      fr27;       /* caller saves -- (PA-RISC 1.1 CPUs) */
191    double      fr28;       /* caller saves -- (PA-RISC 1.1 CPUs) */
192    double      fr29;       /* caller saves -- (PA-RISC 1.1 CPUs) */
193    double      fr30;       /* caller saves -- (PA-RISC 1.1 CPUs) */
194    double      fr31;       /* caller saves -- (PA-RISC 1.1 CPUs) */
195} Context_Control_fp;
196
197/*
198 *  The following structure defines the set of information saved
199 *  on the current stack by RTEMS upon receipt of each interrupt.
200 */
201
202typedef struct {
203  Context_Control             Integer;
204  Context_Control_fp          Floating_Point;
205} CPU_Interrupt_frame;
206
207/*
208 * Our interrupt handlers take a 2nd argument:
209 *   a pointer to a CPU_Interrupt_frame
210 * So we use our own prototype instead of rtems_isr_entry
211 */
212
213typedef void ( *hppa_rtems_isr_entry )(
214    unsigned32,
215    CPU_Interrupt_frame *
216 );
217
218/*
219 * The following table contains the information required to configure
220 * the HPPA specific parameters.
221 */
222
223typedef struct {
224  void       (*pretasking_hook)( void );
225  void       (*predriver_hook)( void );
226  void       (*postdriver_hook)( void );
227  void       (*idle_task)( void );
228  boolean      do_zero_of_workspace;
229  unsigned32   idle_task_stack_size;
230  unsigned32   interrupt_stack_size;
231  unsigned32   extra_mpci_receive_server_stack;
232  void *     (*stack_allocate_hook)( unsigned32 );
233  void       (*stack_free_hook)( void * );
234  /* end of fields required on all CPUs */
235
236  hppa_rtems_isr_entry spurious_handler;
237
238  unsigned32   itimer_clicks_per_microsecond; /* for use by Clock driver */
239}   rtems_cpu_table;
240
241/* variables */
242
243SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
244SCORE_EXTERN unsigned32          _CPU_Default_gr27;
245SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
246SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
247
248#endif          /* ! ASM */
249
250/*
251 *  context sizes
252 */
253
254#ifndef ASM
255#define CPU_CONTEXT_SIZE     sizeof( Context_Control )
256#define CPU_CONTEXT_FP_SIZE  sizeof( Context_Control_fp )
257#endif
258
259/*
260 *  size of a frame on the stack
261 */
262
263#define CPU_FRAME_SIZE (16 * 4)
264
265/*
266 * (Optional) # of bytes for libmisc/stackchk to check
267 * If not specifed, then it defaults to something reasonable
268 * for most architectures.
269 */
270
271#define CPU_STACK_CHECK_SIZE    (CPU_FRAME_SIZE * 2)
272
273/*
274 *  extra stack required by the MPCI receive server thread
275 */
276
277#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
278
279/*
280 * HPPA has 32 traps, then 32 external interrupts
281 * Rtems (_ISR_Vector_Table) is aware ONLY of the first 32
282 * The BSP is aware of the external interrupts and possibly more.
283 *
284 */
285
286#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (HPPA_INTERNAL_TRAPS)
287#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
288
289/*
290 * Don't be chintzy here; we don't want to debug these problems
291 * Some of the tests eat almost 4k.
292 * Plus, the HPPA always allocates chunks of 64 bytes for stack
293 *       growth.
294 */
295
296#define CPU_STACK_MINIMUM_SIZE          (8 * 1024)
297
298/*
299 * HPPA double's must be on 8 byte boundary
300 */
301
302#define CPU_ALIGNMENT              8
303
304/*
305 * just follow the basic HPPA alignment for the heap and partition
306 */
307
308#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
309#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
310
311/*
312 * HPPA stack is best when 64 byte aligned.
313 */
314
315#define CPU_STACK_ALIGNMENT        64
316
317#ifndef ASM
318
319/* macros */
320
321/*
322 *  ISR handler macros
323 *
324 *  These macros perform the following functions:
325 *     + disable all maskable CPU interrupts
326 *     + restore previous interrupt level (enable)
327 *     + temporarily restore interrupts (flash)
328 *     + set a particular level
329 */
330
331/* Disable interrupts; returning previous psw bits in _isr_level */
332#define _CPU_ISR_Disable( _isr_level ) \
333  do { \
334         HPPA_ASM_RSM(HPPA_PSW_I, _isr_level);         \
335         if (_isr_level & HPPA_PSW_I) _isr_level = 0;  \
336         else                          _isr_level = 1; \
337  } while(0)
338
339/* Enable interrupts to previous level from _CPU_ISR_Disable
340 * does not change 'level' */
341#define _CPU_ISR_Enable( _isr_level )  \
342  { \
343        register int _ignore; \
344        if (_isr_level == 0) HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
345        else                 HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
346  }
347
348/* restore, then disable interrupts; does not change level */
349#define _CPU_ISR_Flash( _isr_level ) \
350  { \
351        if (_isr_level == 0) \
352        { \
353              register int _ignore;  \
354              HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
355              HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
356        } \
357  }
358
359/*
360 * Interrupt task levels
361 *
362 * Future scheme proposal
363 *      level will be an index into a array.
364 *      Each entry of array will be the interrupt bits
365 *        enabled for that level.  There will be 32 bits of external
366 *        interrupts (to be placed in EIEM) and some (optional) bsp
367 *        specific bits
368 *
369 * For pixel flow this *may* mean something like:
370 *      level 0:   all interrupts enabled (external + rhino)
371 *      level 1:   rhino disabled
372 *      level 2:   all io interrupts disabled (timer still enabled)
373 *      level 7:   *ALL* disabled (timer disabled)
374 */
375
376/* set interrupts on or off; does not return new level */
377#define _CPU_ISR_Set_level( new_level ) \
378  { \
379        volatile int ignore; \
380        if ( new_level )  HPPA_ASM_RSM(HPPA_PSW_I, ignore); \
381        else              HPPA_ASM_SSM(HPPA_PSW_I, ignore); \
382  }
383
384/* return current level */
385unsigned32 _CPU_ISR_Get_level( void );
386
387/* end of ISR handler macros */
388
389/*
390 *  Context handler macros
391 *
392 *  These macros perform the following functions:
393 *     + initialize a context area
394 *     + restart the current thread
395 *     + calculate the initial pointer into a FP context area
396 *     + initialize an FP context area
397 *
398 *  HPPA port adds two macros which hide the "indirectness" of the
399 *  pointer passed the save/restore FP context assembly routines.
400 */
401
402#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
403                                  _new_level, _entry_point, _is_fp ) \
404  do { \
405    unsigned32 _stack; \
406    \
407    (_the_context)->flags = 0xfeedf00d; \
408    (_the_context)->pcoqfront = (unsigned32)(_entry_point); \
409    (_the_context)->pcoqback  = (unsigned32)(_entry_point) + 4; \
410    (_the_context)->pcsqfront = 0; \
411    (_the_context)->pcsqback  = 0; \
412    if ( (_new_level) ) \
413        (_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \
414    else \
415        (_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \
416    \
417    _stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \
418    _stack &= ~(CPU_STACK_ALIGNMENT - 1); \
419    if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \
420       _stack += CPU_FRAME_SIZE; \
421    \
422    (_the_context)->sp = (_stack); \
423    (_the_context)->gr27 = _CPU_Default_gr27; \
424  } while (0)
425
426#define _CPU_Context_Restart_self( _the_context ) \
427    do { \
428         _CPU_Context_restore( (_the_context) ); \
429    } while (0)
430
431#define _CPU_Context_Fp_start( _base, _offset ) \
432   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
433
434#define _CPU_Context_Initialize_fp( _destination ) \
435  do { \
436    *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\
437  } while(0)
438
439#define _CPU_Context_save_fp( _fp_context ) \
440   _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context) )
441
442#define _CPU_Context_restore_fp( _fp_context ) \
443   _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context) )
444
445/* end of Context handler macros */
446
447/*
448 *  Fatal Error manager macros
449 *
450 *  These macros perform the following functions:
451 *    + disable interrupts and halt the CPU
452 */
453
454void    hppa_cpu_halt(unsigned32 the_error);
455#define _CPU_Fatal_halt( _error ) \
456    hppa_cpu_halt(_error)
457
458/* end of Fatal Error manager macros */
459
460/*
461 *  Bitfield handler macros
462 *
463 *  These macros perform the following functions:
464 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
465 *
466 *  NOTE:
467 *
468 *  The HPPA does not have a scan instruction.  This functionality
469 *  is implemented in software.
470 */
471
472#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
473#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
474
475int hppa_rtems_ffs(unsigned int value);
476#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
477    _output = hppa_rtems_ffs(_value)
478
479/* end of Bitfield handler macros */
480
481/*
482 *  Priority handler macros
483 *
484 *  These macros perform the following functions:
485 *    + return a mask with the bit for this major/minor portion of
486 *      of thread priority set.
487 *    + translate the bit number returned by "Bitfield_find_first_bit"
488 *      into an index into the thread ready chain bit maps
489 *
490 *  Note: 255 is the lowest priority
491 */
492
493#define _CPU_Priority_Mask( _bit_number ) \
494  ( 1 << (_bit_number) )
495
496#define _CPU_Priority_bits_index( _priority ) \
497  (_priority)
498
499/* end of Priority handler macros */
500
501/* functions */
502
503/*
504 *  _CPU_Initialize
505 *
506 *  This routine performs CPU dependent initialization.
507 */
508
509void _CPU_Initialize(
510  rtems_cpu_table  *cpu_table,
511  void      (*thread_dispatch)
512);
513
514/*
515 *  _CPU_ISR_install_raw_handler
516 *
517 *  This routine installs a "raw" interrupt handler directly into the
518 *  processor's vector table.
519 */
520 
521void _CPU_ISR_install_raw_handler(
522  unsigned32  vector,
523  proc_ptr    new_handler,
524  proc_ptr   *old_handler
525);
526
527/*
528 *  _CPU_ISR_install_vector
529 *
530 *  This routine installs an interrupt vector.
531 */
532
533void _CPU_ISR_install_vector(
534  unsigned32  vector,
535  proc_ptr    new_handler,
536  proc_ptr   *old_handler
537);
538
539/*
540 *  _CPU_Context_switch
541 *
542 *  This routine switches from the run context to the heir context.
543 */
544
545void _CPU_Context_switch(
546  Context_Control  *run,
547  Context_Control  *heir
548);
549
550/*
551 *  _CPU_Context_restore
552 *
553 *  This routine is generally used only to restart self in an
554 *  efficient manner and avoid stack conflicts.
555 */
556
557void _CPU_Context_restore(
558  Context_Control *new_context
559);
560
561/*
562 *  _CPU_Save_float_context
563 *
564 *  This routine saves the floating point context passed to it.
565 *
566 *  NOTE:  _CPU_Context_save_fp is implemented as a macro on the HPPA
567 *         which dereferences the pointer before calling this.
568 */
569
570void _CPU_Save_float_context(
571  Context_Control_fp *fp_context
572);
573
574/*
575 *  _CPU_Restore_float_context
576 *
577 *  This routine restores the floating point context passed to it.
578 *
579 *  NOTE:  _CPU_Context_save_fp is implemented as a macro on the HPPA
580 *         which dereferences the pointer before calling this.
581 */
582
583void _CPU_Restore_float_context(
584  Context_Control_fp *fp_context
585);
586
587
588/*
589 * The raw interrupt handler for external interrupts
590 */
591
592extern void _Generic_ISR_Handler(
593    void
594);
595
596
597/*  The following routine swaps the endian format of an unsigned int.
598 *  It must be static so it can be referenced indirectly.
599 */
600
601static inline unsigned int
602CPU_swap_u32(unsigned32 value)
603{
604  unsigned32 swapped;
605
606  HPPA_ASM_SWAPBYTES(value, swapped);
607
608  return( swapped );
609}
610
611#define CPU_swap_u16( value ) \
612  (((value&0xff) << 8) | ((value >> 8)&0xff))
613
614#endif   /* ! ASM */
615
616#ifdef __cplusplus
617}
618#endif
619
620#endif   /* ! __CPU_h */
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