source: rtems/c/src/exec/score/cpu/hppa1.1/cpu.h @ 8b2ecf85

4.104.114.84.95
Last change on this file since 8b2ecf85 was 8b2ecf85, checked in by Joel Sherrill <joel.sherrill@…>, on May 23, 1996 at 3:37:38 PM

updates from Tony Bennett

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File size: 17.7 KB
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1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of Division Incorporated not be
14 *      used in advertising or publicity pertaining to distribution
15 *      of the software without specific, written prior permission.
16 *      Division Incorporated makes no representations about the
17 *      suitability of this software for any purpose.
18 *
19 *
20 * Note:
21 *      This file is included by both C and assembler code ( -DASM )
22 *
23 *  $Id$
24 */
25
26#ifndef __CPU_h
27#define __CPU_h
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33#include <rtems/score/hppa.h>              /* pick up machine definitions */
34#ifndef ASM
35#include <rtems/score/hppatypes.h>
36#endif
37
38/* conditional compilation parameters */
39
40#define CPU_INLINE_ENABLE_DISPATCH       FALSE
41#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
42
43/*
44 *  RTEMS manages an interrupt stack in software for the HPPA.
45 */
46
47#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
48#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
49#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
50
51/*
52 *  HPPA has hardware FP, it is assumed to exist by GCC so all tasks
53 *  may implicitly use it (especially for integer multiplies).  Because
54 *  the FP context is technically part of the basic integer context
55 *  on this CPU, we cannot use the deferred FP context switch algorithm.
56 */
57
58#define CPU_HARDWARE_FP                  TRUE
59#define CPU_ALL_TASKS_ARE_FP             TRUE
60#define CPU_IDLE_TASK_IS_FP              FALSE
61#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
62
63#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
64#define CPU_STACK_GROWS_UP               TRUE
65#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((__aligned__ (32)))
66
67/* constants */
68
69#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
70#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
71
72/*
73 * PSW contstants
74 */
75
76#define CPU_PSW_BASE (HPPA_PSW_C | HPPA_PSW_Q | HPPA_PSW_P | HPPA_PSW_D)
77#define CPU_PSW_INTERRUPTS_ON    (CPU_PSW_BASE | HPPA_PSW_I)
78#define CPU_PSW_INTERRUPTS_OFF   (CPU_PSW_BASE)
79
80#define CPU_PSW_DEFAULT     CPU_PSW_BASE
81
82
83#ifndef ASM
84
85/*
86 * Contexts
87 *
88 *  This means we have the following context items:
89 *    1. task level context stuff::  Context_Control
90 *    2. floating point task stuff:: Context_Control_fp
91 *
92 *  The PA-RISC is very fast so the expense of saving an extra register
93 *  or two is not of great concern at the present.  So we are not making
94 *  a distinction between what is saved during a task switch and what is
95 *  saved at each interrupt.  Plus saving the entire context should make
96 *  it easier to make gdb aware of RTEMS tasks.
97 */
98
99typedef struct {
100    unsigned32 flags;      /* whatever */
101    unsigned32 gr1;        /* scratch -- caller saves */
102    unsigned32 gr2;        /* RP -- return pointer */
103    unsigned32 gr3;        /* scratch -- callee saves */
104    unsigned32 gr4;        /* scratch -- callee saves */
105    unsigned32 gr5;        /* scratch -- callee saves */
106    unsigned32 gr6;        /* scratch -- callee saves */
107    unsigned32 gr7;        /* scratch -- callee saves */
108    unsigned32 gr8;        /* scratch -- callee saves */
109    unsigned32 gr9;        /* scratch -- callee saves */
110    unsigned32 gr10;       /* scratch -- callee saves */
111    unsigned32 gr11;       /* scratch -- callee saves */
112    unsigned32 gr12;       /* scratch -- callee saves */
113    unsigned32 gr13;       /* scratch -- callee saves */
114    unsigned32 gr14;       /* scratch -- callee saves */
115    unsigned32 gr15;       /* scratch -- callee saves */
116    unsigned32 gr16;       /* scratch -- callee saves */
117    unsigned32 gr17;       /* scratch -- callee saves */
118    unsigned32 gr18;       /* scratch -- callee saves */
119    unsigned32 gr19;       /* scratch -- caller saves */
120    unsigned32 gr20;       /* scratch -- caller saves */
121    unsigned32 gr21;       /* scratch -- caller saves */
122    unsigned32 gr22;       /* scratch -- caller saves */
123    unsigned32 gr23;       /* argument 3 */
124    unsigned32 gr24;       /* argument 2 */
125    unsigned32 gr25;       /* argument 1 */
126    unsigned32 gr26;       /* argument 0 */
127    unsigned32 gr27;       /* DP -- global data pointer */
128    unsigned32 gr28;       /* return values -- caller saves */
129    unsigned32 gr29;       /* return values -- caller saves */
130    unsigned32 sp;         /* gr30 */
131    unsigned32 gr31;
132
133    /* Various control registers */
134
135    unsigned32 sar;         /* cr11 */
136    unsigned32 ipsw;        /* cr22; full 32 bits of psw */
137    unsigned32 iir;         /* cr19; interrupt instruction register */
138    unsigned32 ior;         /* cr21; interrupt offset register */
139    unsigned32 isr;         /* cr20; interrupt space register (not used) */
140    unsigned32 pcoqfront;   /* cr18; front que offset */
141    unsigned32 pcoqback;    /* cr18; back que offset */
142    unsigned32 pcsqfront;   /* cr17; front que space (not used) */
143    unsigned32 pcsqback;    /* cr17; back que space (not used) */
144    unsigned32 itimer;      /* cr16; itimer value */
145
146} Context_Control;
147
148
149/* Must be double word aligned.
150 * This will be ok since our allocator returns 8 byte aligned chunks
151 */
152
153typedef struct {
154    double      fr0;        /* status */
155    double      fr1;        /* exception information */
156    double      fr2;        /* exception information */
157    double      fr3;        /* exception information */
158    double      fr4;        /* argument */
159    double      fr5;        /* argument */
160    double      fr6;        /* argument */
161    double      fr7;        /* argument */
162    double      fr8;        /* scratch -- caller saves */
163    double      fr9;        /* scratch -- caller saves */
164    double      fr10;       /* scratch -- caller saves */
165    double      fr11;       /* scratch -- caller saves */
166    double      fr12;       /* callee saves -- (PA-RISC 1.1 CPUs) */
167    double      fr13;       /* callee saves -- (PA-RISC 1.1 CPUs) */
168    double      fr14;       /* callee saves -- (PA-RISC 1.1 CPUs) */
169    double      fr15;       /* callee saves -- (PA-RISC 1.1 CPUs) */
170    double      fr16;       /* callee saves -- (PA-RISC 1.1 CPUs) */
171    double      fr17;       /* callee saves -- (PA-RISC 1.1 CPUs) */
172    double      fr18;       /* callee saves -- (PA-RISC 1.1 CPUs) */
173    double      fr19;       /* callee saves -- (PA-RISC 1.1 CPUs) */
174    double      fr20;       /* callee saves -- (PA-RISC 1.1 CPUs) */
175    double      fr21;       /* callee saves -- (PA-RISC 1.1 CPUs) */
176    double      fr22;       /* caller saves -- (PA-RISC 1.1 CPUs) */
177    double      fr23;       /* caller saves -- (PA-RISC 1.1 CPUs) */
178    double      fr24;       /* caller saves -- (PA-RISC 1.1 CPUs) */
179    double      fr25;       /* caller saves -- (PA-RISC 1.1 CPUs) */
180    double      fr26;       /* caller saves -- (PA-RISC 1.1 CPUs) */
181    double      fr27;       /* caller saves -- (PA-RISC 1.1 CPUs) */
182    double      fr28;       /* caller saves -- (PA-RISC 1.1 CPUs) */
183    double      fr29;       /* caller saves -- (PA-RISC 1.1 CPUs) */
184    double      fr30;       /* caller saves -- (PA-RISC 1.1 CPUs) */
185    double      fr31;       /* caller saves -- (PA-RISC 1.1 CPUs) */
186} Context_Control_fp;
187
188/*
189 *  The following structure defines the set of information saved
190 *  on the current stack by RTEMS upon receipt of each interrupt.
191 */
192
193typedef struct {
194  Context_Control             Integer;
195  Context_Control_fp          Floating_Point;
196} CPU_Interrupt_frame;
197
198/*
199 * Our interrupt handlers take a 2nd argument:
200 *   a pointer to a CPU_Interrupt_frame
201 * So we use our own prototype instead of rtems_isr_entry
202 */
203
204typedef void ( *hppa_rtems_isr_entry )(
205    unsigned32,
206    CPU_Interrupt_frame *
207 );
208
209/*
210 * The following table contains the information required to configure
211 * the HPPA specific parameters.
212 */
213
214typedef struct {
215  void       (*pretasking_hook)( void );
216  void       (*predriver_hook)( void );
217  void       (*postdriver_hook)( void );
218  void       (*idle_task)( void );
219  boolean      do_zero_of_workspace;
220  unsigned32   interrupt_stack_size;
221  unsigned32   extra_mpci_receive_server_stack;
222  void *     (*stack_allocate_hook)( unsigned32 );
223  void       (*stack_free_hook)( void * );
224  /* end of fields required on all CPUs */
225
226  hppa_rtems_isr_entry spurious_handler;
227
228  unsigned32   itimer_clicks_per_microsecond; /* for use by Clock driver */
229}   rtems_cpu_table;
230
231/* variables */
232
233EXTERN Context_Control_fp  _CPU_Null_fp_context;
234EXTERN unsigned32          _CPU_Default_gr27;
235EXTERN void               *_CPU_Interrupt_stack_low;
236EXTERN void               *_CPU_Interrupt_stack_high;
237
238#endif          /* ! ASM */
239
240/*
241 *  context sizes
242 */
243
244#ifndef ASM
245#define CPU_CONTEXT_SIZE     sizeof( Context_Control )
246#define CPU_CONTEXT_FP_SIZE  sizeof( Context_Control_fp )
247#endif
248
249/*
250 *  size of a frame on the stack
251 */
252
253#define CPU_FRAME_SIZE (16 * 4)
254
255/*
256 * (Optional) # of bytes for libmisc/stackchk to check
257 * If not specifed, then it defaults to something reasonable
258 * for most architectures.
259 */
260
261#define CPU_STACK_CHECK_SIZE    (CPU_FRAME_SIZE * 2)
262
263/*
264 *  extra stack required by the MPCI receive server thread
265 */
266
267#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
268
269/*
270 * HPPA has 32 traps, then 32 external interrupts
271 * Rtems (_ISR_Vector_Table) is aware ONLY of the first 32
272 * The BSP is aware of the external interrupts and possibly more.
273 *
274 */
275
276#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (HPPA_INTERNAL_TRAPS)
277#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
278
279/*
280 * Don't be chintzy here; we don't want to debug these problems
281 * Some of the tests eat almost 4k.
282 * Plus, the HPPA always allocates chunks of 64 bytes for stack
283 *       growth.
284 */
285
286#define CPU_STACK_MINIMUM_SIZE          (8 * 1024)
287
288/*
289 * HPPA double's must be on 8 byte boundary
290 */
291
292#define CPU_ALIGNMENT              8
293
294/*
295 * just follow the basic HPPA alignment for the heap and partition
296 */
297
298#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
299#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
300
301/*
302 * HPPA stack is best when 64 byte aligned.
303 */
304
305#define CPU_STACK_ALIGNMENT        64
306
307#ifndef ASM
308
309/* macros */
310
311/*
312 *  ISR handler macros
313 *
314 *  These macros perform the following functions:
315 *     + disable all maskable CPU interrupts
316 *     + restore previous interrupt level (enable)
317 *     + temporarily restore interrupts (flash)
318 *     + set a particular level
319 */
320
321/* Disable interrupts; returning previous psw bits in _isr_level */
322#define _CPU_ISR_Disable( _isr_level ) \
323  do { \
324         HPPA_ASM_RSM(HPPA_PSW_I, _isr_level);         \
325         if (_isr_level & HPPA_PSW_I) _isr_level = 0;  \
326         else                          _isr_level = 1; \
327  } while(0)
328
329/* Enable interrupts to previous level from _CPU_ISR_Disable
330 * does not change 'level' */
331#define _CPU_ISR_Enable( _isr_level )  \
332  { \
333        register int _ignore; \
334        if (_isr_level == 0) HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
335        else                 HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
336  }
337
338/* restore, then disable interrupts; does not change level */
339#define _CPU_ISR_Flash( _isr_level ) \
340  { \
341        if (_isr_level == 0) \
342        { \
343              register int _ignore;  \
344              HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
345              HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
346        } \
347  }
348
349/*
350 * Interrupt task levels
351 *
352 * Future scheme proposal
353 *      level will be an index into a array.
354 *      Each entry of array will be the interrupt bits
355 *        enabled for that level.  There will be 32 bits of external
356 *        interrupts (to be placed in EIEM) and some (optional) bsp
357 *        specific bits
358 *
359 * For pixel flow this *may* mean something like:
360 *      level 0:   all interrupts enabled (external + rhino)
361 *      level 1:   rhino disabled
362 *      level 2:   all io interrupts disabled (timer still enabled)
363 *      level 7:   *ALL* disabled (timer disabled)
364 */
365
366/* set interrupts on or off; does not return new level */
367#define _CPU_ISR_Set_level( new_level ) \
368  { \
369        volatile int ignore; \
370        if ( new_level )  HPPA_ASM_RSM(HPPA_PSW_I, ignore); \
371        else              HPPA_ASM_SSM(HPPA_PSW_I, ignore); \
372  }
373
374/* return current level */
375unsigned32 _CPU_ISR_Get_level( void );
376
377/* end of ISR handler macros */
378
379/*
380 *  Context handler macros
381 *
382 *  These macros perform the following functions:
383 *     + initialize a context area
384 *     + restart the current thread
385 *     + calculate the initial pointer into a FP context area
386 *     + initialize an FP context area
387 *
388 *  HPPA port adds two macros which hide the "indirectness" of the
389 *  pointer passed the save/restore FP context assembly routines.
390 */
391
392#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
393                                  _new_level, _entry_point, _is_fp ) \
394  do { \
395    unsigned32 _stack; \
396    \
397    (_the_context)->flags = 0xfeedf00d; \
398    (_the_context)->pcoqfront = (unsigned32)(_entry_point); \
399    (_the_context)->pcoqback  = (unsigned32)(_entry_point) + 4; \
400    (_the_context)->pcsqfront = 0; \
401    (_the_context)->pcsqback  = 0; \
402    if ( (_new_level) ) \
403        (_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \
404    else \
405        (_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \
406    \
407    _stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \
408    _stack &= ~(CPU_STACK_ALIGNMENT - 1); \
409    if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \
410       _stack += CPU_FRAME_SIZE; \
411    \
412    (_the_context)->sp = (_stack); \
413    (_the_context)->gr27 = _CPU_Default_gr27; \
414  } while (0)
415
416#define _CPU_Context_Restart_self( _the_context ) \
417    do { \
418         _CPU_Context_restore( (_the_context) ); \
419    } while (0)
420
421#define _CPU_Context_Fp_start( _base, _offset ) \
422   ( (void *) (_base) + (_offset) )
423
424#define _CPU_Context_Initialize_fp( _destination ) \
425  do { \
426    *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\
427  } while(0)
428
429#define _CPU_Context_save_fp( _fp_context ) \
430   _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context) )
431
432#define _CPU_Context_restore_fp( _fp_context ) \
433   _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context) )
434
435/* end of Context handler macros */
436
437/*
438 *  Fatal Error manager macros
439 *
440 *  These macros perform the following functions:
441 *    + disable interrupts and halt the CPU
442 */
443
444void    hppa_cpu_halt(unsigned32 the_error);
445#define _CPU_Fatal_halt( _error ) \
446    hppa_cpu_halt(_error)
447
448/* end of Fatal Error manager macros */
449
450/*
451 *  Bitfield handler macros
452 *
453 *  These macros perform the following functions:
454 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
455 *
456 *  NOTE:
457 *
458 *  The HPPA does not have a scan instruction.  This functionality
459 *  is implemented in software.
460 */
461
462#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
463#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
464
465int hppa_rtems_ffs(unsigned int value);
466#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
467    _output = hppa_rtems_ffs(_value)
468
469/* end of Bitfield handler macros */
470
471/*
472 *  Priority handler macros
473 *
474 *  These macros perform the following functions:
475 *    + return a mask with the bit for this major/minor portion of
476 *      of thread priority set.
477 *    + translate the bit number returned by "Bitfield_find_first_bit"
478 *      into an index into the thread ready chain bit maps
479 *
480 *  Note: 255 is the lowest priority
481 */
482
483#define _CPU_Priority_Mask( _bit_number ) \
484  ( 1 << (_bit_number) )
485
486#define _CPU_Priority_bits_index( _priority ) \
487  (_priority)
488
489/* end of Priority handler macros */
490
491/* functions */
492
493/*
494 *  _CPU_Initialize
495 *
496 *  This routine performs CPU dependent initialization.
497 */
498
499void _CPU_Initialize(
500  rtems_cpu_table  *cpu_table,
501  void      (*thread_dispatch)
502);
503
504/*
505 *  _CPU_ISR_install_raw_handler
506 *
507 *  This routine installs a "raw" interrupt handler directly into the
508 *  processor's vector table.
509 */
510 
511void _CPU_ISR_install_raw_handler(
512  unsigned32  vector,
513  proc_ptr    new_handler,
514  proc_ptr   *old_handler
515);
516
517/*
518 *  _CPU_ISR_install_vector
519 *
520 *  This routine installs an interrupt vector.
521 */
522
523void _CPU_ISR_install_vector(
524  unsigned32  vector,
525  proc_ptr    new_handler,
526  proc_ptr   *old_handler
527);
528
529/*
530 *  _CPU_Context_switch
531 *
532 *  This routine switches from the run context to the heir context.
533 */
534
535void _CPU_Context_switch(
536  Context_Control  *run,
537  Context_Control  *heir
538);
539
540/*
541 *  _CPU_Context_restore
542 *
543 *  This routine is generally used only to restart self in an
544 *  efficient manner and avoid stack conflicts.
545 */
546
547void _CPU_Context_restore(
548  Context_Control *new_context
549);
550
551/*
552 *  _CPU_Save_float_context
553 *
554 *  This routine saves the floating point context passed to it.
555 *
556 *  NOTE:  _CPU_Context_save_fp is implemented as a macro on the HPPA
557 *         which dereferences the pointer before calling this.
558 */
559
560void _CPU_Save_float_context(
561  Context_Control_fp *fp_context
562);
563
564/*
565 *  _CPU_Restore_float_context
566 *
567 *  This routine restores the floating point context passed to it.
568 *
569 *  NOTE:  _CPU_Context_save_fp is implemented as a macro on the HPPA
570 *         which dereferences the pointer before calling this.
571 */
572
573void _CPU_Restore_float_context(
574  Context_Control_fp *fp_context
575);
576
577
578/*
579 * The raw interrupt handler for external interrupts
580 */
581
582extern void _Generic_ISR_Handler(
583    void
584);
585
586
587/*  The following routine swaps the endian format of an unsigned int.
588 *  It must be static so it can be referenced indirectly.
589 */
590
591static inline unsigned int
592CPU_swap_u32(unsigned32 value)
593{
594  unsigned32 swapped;
595
596  HPPA_ASM_SWAPBYTES(value, swapped);
597
598  return( swapped );
599}
600
601#endif   /* ! ASM */
602
603#ifdef __cplusplus
604}
605#endif
606
607#endif   /* ! __CPU_h */
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