[ac7d5ef0] | 1 | /* cpu.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the HP |
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| 4 | * PA-RISC processor (Level 1.1). |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 1994 by Division Incorporated |
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| 7 | * |
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| 8 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 9 | * without any express or implied warranty: |
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| 10 | * permission to use, copy, modify, and distribute this file |
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| 11 | * for any purpose is hereby granted without fee, provided that |
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| 12 | * the above copyright notice and this notice appears in all |
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| 13 | * copies, and that the name of Division Incorporated not be |
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| 14 | * used in advertising or publicity pertaining to distribution |
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| 15 | * of the software without specific, written prior permission. |
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| 16 | * Division Incorporated makes no representations about the |
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| 17 | * suitability of this software for any purpose. |
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| 18 | * |
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| 19 | * |
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| 20 | * Note: |
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| 21 | * This file is included by both C and assembler code ( -DASM ) |
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| 22 | * |
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[eb5a7e07] | 23 | * $Id$ |
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[ac7d5ef0] | 24 | */ |
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| 25 | |
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| 26 | #ifndef __CPU_h |
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| 27 | #define __CPU_h |
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| 28 | |
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| 29 | #ifdef __cplusplus |
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| 30 | extern "C" { |
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| 31 | #endif |
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| 32 | |
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[ca201c9] | 33 | #include <rtems/score/hppa.h> /* pick up machine definitions */ |
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[88d594a] | 34 | #ifndef ASM |
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[ca201c9] | 35 | #include <rtems/score/hppatypes.h> |
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[88d594a] | 36 | #endif |
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[ac7d5ef0] | 37 | |
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| 38 | /* conditional compilation parameters */ |
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| 39 | |
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| 40 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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| 41 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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| 42 | |
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| 43 | /* |
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| 44 | * RTEMS manages an interrupt stack in software for the HPPA. |
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| 45 | */ |
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| 46 | |
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| 47 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 48 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 49 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 50 | |
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| 51 | /* |
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| 52 | * HPPA has hardware FP, it is assumed to exist by GCC so all tasks |
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| 53 | * may implicitly use it (especially for integer multiplies). Because |
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| 54 | * the FP context is technically part of the basic integer context |
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| 55 | * on this CPU, we cannot use the deferred FP context switch algorithm. |
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| 56 | */ |
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| 57 | |
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| 58 | #define CPU_HARDWARE_FP TRUE |
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| 59 | #define CPU_ALL_TASKS_ARE_FP TRUE |
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| 60 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 61 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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| 62 | |
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| 63 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 64 | #define CPU_STACK_GROWS_UP TRUE |
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| 65 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((__aligned__ (32))) |
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| 66 | |
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| 67 | /* constants */ |
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| 68 | |
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| 69 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
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| 70 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
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| 71 | |
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| 72 | /* |
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| 73 | * PSW contstants |
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| 74 | */ |
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| 75 | |
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| 76 | #define CPU_PSW_BASE (HPPA_PSW_C | HPPA_PSW_Q | HPPA_PSW_P | HPPA_PSW_D) |
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| 77 | #define CPU_PSW_INTERRUPTS_ON (CPU_PSW_BASE | HPPA_PSW_I) |
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| 78 | #define CPU_PSW_INTERRUPTS_OFF (CPU_PSW_BASE) |
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| 79 | |
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| 80 | #define CPU_PSW_DEFAULT CPU_PSW_BASE |
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| 81 | |
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| 82 | |
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| 83 | #ifndef ASM |
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| 84 | |
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| 85 | /* |
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| 86 | * Contexts |
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| 87 | * |
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| 88 | * This means we have the following context items: |
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| 89 | * 1. task level context stuff:: Context_Control |
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| 90 | * 2. floating point task stuff:: Context_Control_fp |
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| 91 | * |
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| 92 | * The PA-RISC is very fast so the expense of saving an extra register |
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| 93 | * or two is not of great concern at the present. So we are not making |
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| 94 | * a distinction between what is saved during a task switch and what is |
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| 95 | * saved at each interrupt. Plus saving the entire context should make |
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| 96 | * it easier to make gdb aware of RTEMS tasks. |
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| 97 | */ |
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| 98 | |
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| 99 | typedef struct { |
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| 100 | unsigned32 flags; /* whatever */ |
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| 101 | unsigned32 gr1; /* scratch -- caller saves */ |
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| 102 | unsigned32 gr2; /* RP -- return pointer */ |
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| 103 | unsigned32 gr3; /* scratch -- callee saves */ |
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| 104 | unsigned32 gr4; /* scratch -- callee saves */ |
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| 105 | unsigned32 gr5; /* scratch -- callee saves */ |
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| 106 | unsigned32 gr6; /* scratch -- callee saves */ |
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| 107 | unsigned32 gr7; /* scratch -- callee saves */ |
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| 108 | unsigned32 gr8; /* scratch -- callee saves */ |
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| 109 | unsigned32 gr9; /* scratch -- callee saves */ |
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| 110 | unsigned32 gr10; /* scratch -- callee saves */ |
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| 111 | unsigned32 gr11; /* scratch -- callee saves */ |
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| 112 | unsigned32 gr12; /* scratch -- callee saves */ |
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| 113 | unsigned32 gr13; /* scratch -- callee saves */ |
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| 114 | unsigned32 gr14; /* scratch -- callee saves */ |
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| 115 | unsigned32 gr15; /* scratch -- callee saves */ |
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| 116 | unsigned32 gr16; /* scratch -- callee saves */ |
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| 117 | unsigned32 gr17; /* scratch -- callee saves */ |
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| 118 | unsigned32 gr18; /* scratch -- callee saves */ |
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| 119 | unsigned32 gr19; /* scratch -- caller saves */ |
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| 120 | unsigned32 gr20; /* scratch -- caller saves */ |
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| 121 | unsigned32 gr21; /* scratch -- caller saves */ |
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| 122 | unsigned32 gr22; /* scratch -- caller saves */ |
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| 123 | unsigned32 gr23; /* argument 3 */ |
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| 124 | unsigned32 gr24; /* argument 2 */ |
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| 125 | unsigned32 gr25; /* argument 1 */ |
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| 126 | unsigned32 gr26; /* argument 0 */ |
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| 127 | unsigned32 gr27; /* DP -- global data pointer */ |
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| 128 | unsigned32 gr28; /* return values -- caller saves */ |
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| 129 | unsigned32 gr29; /* return values -- caller saves */ |
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| 130 | unsigned32 sp; /* gr30 */ |
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| 131 | unsigned32 gr31; |
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| 132 | |
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| 133 | /* Various control registers */ |
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| 134 | |
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| 135 | unsigned32 sar; /* cr11 */ |
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| 136 | unsigned32 ipsw; /* cr22; full 32 bits of psw */ |
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| 137 | unsigned32 iir; /* cr19; interrupt instruction register */ |
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| 138 | unsigned32 ior; /* cr21; interrupt offset register */ |
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| 139 | unsigned32 isr; /* cr20; interrupt space register (not used) */ |
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| 140 | unsigned32 pcoqfront; /* cr18; front que offset */ |
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| 141 | unsigned32 pcoqback; /* cr18; back que offset */ |
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| 142 | unsigned32 pcsqfront; /* cr17; front que space (not used) */ |
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| 143 | unsigned32 pcsqback; /* cr17; back que space (not used) */ |
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| 144 | unsigned32 itimer; /* cr16; itimer value */ |
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| 145 | |
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| 146 | } Context_Control; |
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| 147 | |
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| 148 | |
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| 149 | /* Must be double word aligned. |
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| 150 | * This will be ok since our allocator returns 8 byte aligned chunks |
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| 151 | */ |
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| 152 | |
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| 153 | typedef struct { |
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| 154 | double fr0; /* status */ |
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| 155 | double fr1; /* exception information */ |
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| 156 | double fr2; /* exception information */ |
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| 157 | double fr3; /* exception information */ |
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| 158 | double fr4; /* argument */ |
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| 159 | double fr5; /* argument */ |
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| 160 | double fr6; /* argument */ |
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| 161 | double fr7; /* argument */ |
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| 162 | double fr8; /* scratch -- caller saves */ |
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| 163 | double fr9; /* scratch -- caller saves */ |
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| 164 | double fr10; /* scratch -- caller saves */ |
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| 165 | double fr11; /* scratch -- caller saves */ |
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| 166 | double fr12; /* callee saves -- (PA-RISC 1.1 CPUs) */ |
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| 167 | double fr13; /* callee saves -- (PA-RISC 1.1 CPUs) */ |
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| 168 | double fr14; /* callee saves -- (PA-RISC 1.1 CPUs) */ |
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| 169 | double fr15; /* callee saves -- (PA-RISC 1.1 CPUs) */ |
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| 170 | double fr16; /* callee saves -- (PA-RISC 1.1 CPUs) */ |
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| 171 | double fr17; /* callee saves -- (PA-RISC 1.1 CPUs) */ |
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| 172 | double fr18; /* callee saves -- (PA-RISC 1.1 CPUs) */ |
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| 173 | double fr19; /* callee saves -- (PA-RISC 1.1 CPUs) */ |
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| 174 | double fr20; /* callee saves -- (PA-RISC 1.1 CPUs) */ |
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| 175 | double fr21; /* callee saves -- (PA-RISC 1.1 CPUs) */ |
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| 176 | double fr22; /* caller saves -- (PA-RISC 1.1 CPUs) */ |
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| 177 | double fr23; /* caller saves -- (PA-RISC 1.1 CPUs) */ |
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| 178 | double fr24; /* caller saves -- (PA-RISC 1.1 CPUs) */ |
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| 179 | double fr25; /* caller saves -- (PA-RISC 1.1 CPUs) */ |
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| 180 | double fr26; /* caller saves -- (PA-RISC 1.1 CPUs) */ |
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| 181 | double fr27; /* caller saves -- (PA-RISC 1.1 CPUs) */ |
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| 182 | double fr28; /* caller saves -- (PA-RISC 1.1 CPUs) */ |
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| 183 | double fr29; /* caller saves -- (PA-RISC 1.1 CPUs) */ |
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| 184 | double fr30; /* caller saves -- (PA-RISC 1.1 CPUs) */ |
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| 185 | double fr31; /* caller saves -- (PA-RISC 1.1 CPUs) */ |
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| 186 | } Context_Control_fp; |
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| 187 | |
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| 188 | /* |
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| 189 | * The following structure defines the set of information saved |
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| 190 | * on the current stack by RTEMS upon receipt of each interrupt. |
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| 191 | */ |
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| 192 | |
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| 193 | typedef struct { |
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| 194 | Context_Control Integer; |
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| 195 | Context_Control_fp Floating_Point; |
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| 196 | } CPU_Interrupt_frame; |
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| 197 | |
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[c64e4ed4] | 198 | /* |
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| 199 | * Our interrupt handlers take a 2nd argument: |
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| 200 | * a pointer to a CPU_Interrupt_frame |
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| 201 | * So we use our own prototype instead of rtems_isr_entry |
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| 202 | */ |
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| 203 | |
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| 204 | typedef void ( *hppa_rtems_isr_entry )( |
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| 205 | unsigned32, |
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| 206 | CPU_Interrupt_frame * |
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| 207 | ); |
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| 208 | |
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[ac7d5ef0] | 209 | /* |
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| 210 | * The following table contains the information required to configure |
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| 211 | * the HPPA specific parameters. |
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| 212 | */ |
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| 213 | |
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| 214 | typedef struct { |
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| 215 | void (*pretasking_hook)( void ); |
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| 216 | void (*predriver_hook)( void ); |
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| 217 | void (*postdriver_hook)( void ); |
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| 218 | void (*idle_task)( void ); |
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| 219 | boolean do_zero_of_workspace; |
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| 220 | unsigned32 interrupt_stack_size; |
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[75f09e5] | 221 | unsigned32 extra_mpci_receive_server_stack; |
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[d0b7c4e6] | 222 | void * (*stack_allocate_hook)( unsigned32 ); |
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| 223 | void (*stack_free_hook)( void * ); |
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| 224 | /* end of fields required on all CPUs */ |
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[ac7d5ef0] | 225 | |
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[c64e4ed4] | 226 | hppa_rtems_isr_entry spurious_handler; |
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[ac7d5ef0] | 227 | |
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| 228 | unsigned32 itimer_clicks_per_microsecond; /* for use by Clock driver */ |
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| 229 | } rtems_cpu_table; |
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| 230 | |
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| 231 | /* variables */ |
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| 232 | |
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| 233 | EXTERN Context_Control_fp _CPU_Null_fp_context; |
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| 234 | EXTERN unsigned32 _CPU_Default_gr27; |
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| 235 | EXTERN void *_CPU_Interrupt_stack_low; |
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| 236 | EXTERN void *_CPU_Interrupt_stack_high; |
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| 237 | |
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| 238 | #endif /* ! ASM */ |
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| 239 | |
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| 240 | /* |
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[c64e4ed4] | 241 | * context sizes |
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[ac7d5ef0] | 242 | */ |
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| 243 | |
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| 244 | #ifndef ASM |
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[c64e4ed4] | 245 | #define CPU_CONTEXT_SIZE sizeof( Context_Control ) |
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| 246 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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[ac7d5ef0] | 247 | #endif |
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| 248 | |
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| 249 | /* |
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| 250 | * size of a frame on the stack |
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| 251 | */ |
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| 252 | |
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| 253 | #define CPU_FRAME_SIZE (16 * 4) |
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| 254 | |
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| 255 | /* |
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| 256 | * (Optional) # of bytes for libmisc/stackchk to check |
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| 257 | * If not specifed, then it defaults to something reasonable |
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| 258 | * for most architectures. |
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| 259 | */ |
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| 260 | |
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| 261 | #define CPU_STACK_CHECK_SIZE (CPU_FRAME_SIZE * 2) |
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| 262 | |
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| 263 | /* |
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[75f09e5] | 264 | * extra stack required by the MPCI receive server thread |
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[ac7d5ef0] | 265 | */ |
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| 266 | |
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[75f09e5] | 267 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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[ac7d5ef0] | 268 | |
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| 269 | /* |
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| 270 | * HPPA has 32 interrupts, then 32 external interrupts |
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[d0b7c4e6] | 271 | * Rtems (_ISR_Vector_Table) is aware ONLY of the first 32 |
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| 272 | * The BSP is aware of the external interrupts and possibly more. |
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[ac7d5ef0] | 273 | * |
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| 274 | */ |
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| 275 | |
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[d0b7c4e6] | 276 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS (HPPA_INTERNAL_INTERRUPTS) |
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[9700578] | 277 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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[ac7d5ef0] | 278 | |
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| 279 | /* |
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| 280 | * Don't be chintzy here; we don't want to debug these problems |
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| 281 | * Some of the tests eat almost 4k. |
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| 282 | * Plus, the HPPA always allocates chunks of 64 bytes for stack |
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| 283 | * growth. |
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| 284 | */ |
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| 285 | |
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| 286 | #define CPU_STACK_MINIMUM_SIZE (8 * 1024) |
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| 287 | |
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| 288 | /* |
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| 289 | * HPPA double's must be on 8 byte boundary |
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| 290 | */ |
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| 291 | |
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| 292 | #define CPU_ALIGNMENT 8 |
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| 293 | |
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| 294 | /* |
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| 295 | * just follow the basic HPPA alignment for the heap and partition |
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| 296 | */ |
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| 297 | |
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| 298 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 299 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 300 | |
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| 301 | /* |
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| 302 | * HPPA stack is best when 64 byte aligned. |
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| 303 | */ |
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| 304 | |
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| 305 | #define CPU_STACK_ALIGNMENT 64 |
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| 306 | |
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| 307 | #ifndef ASM |
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| 308 | |
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| 309 | /* macros */ |
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| 310 | |
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| 311 | /* |
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| 312 | * ISR handler macros |
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| 313 | * |
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| 314 | * These macros perform the following functions: |
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| 315 | * + disable all maskable CPU interrupts |
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| 316 | * + restore previous interrupt level (enable) |
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| 317 | * + temporarily restore interrupts (flash) |
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| 318 | * + set a particular level |
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| 319 | */ |
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| 320 | |
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| 321 | /* Disable interrupts; returning previous level in _level */ |
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| 322 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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| 323 | do { \ |
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| 324 | HPPA_ASM_RSM(HPPA_PSW_I, _isr_cookie); \ |
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| 325 | } while(0) |
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| 326 | |
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| 327 | /* Enable interrupts to previous level from _CPU_ISR_Disable |
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| 328 | * does not change 'level' */ |
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| 329 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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| 330 | { \ |
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| 331 | HPPA_ASM_MTSM( _isr_cookie ); \ |
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| 332 | } |
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| 333 | |
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| 334 | /* restore, then disable interrupts; does not change level */ |
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| 335 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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| 336 | { \ |
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| 337 | register int _ignore; \ |
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| 338 | _CPU_ISR_Enable( _isr_cookie ); \ |
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| 339 | _CPU_ISR_Disable( _ignore ); \ |
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| 340 | } |
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| 341 | |
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| 342 | /* |
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| 343 | * Interrupt task levels |
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| 344 | * |
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| 345 | * Future scheme proposal |
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| 346 | * level will be an index into a array. |
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| 347 | * Each entry of array will be the interrupt bits |
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| 348 | * enabled for that level. There will be 32 bits of external |
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| 349 | * interrupts (to be placed in EIEM) and some (optional) bsp |
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| 350 | * specific bits |
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| 351 | * |
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| 352 | * For pixel flow this *may* mean something like: |
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| 353 | * level 0: all interrupts enabled (external + rhino) |
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| 354 | * level 1: rhino disabled |
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| 355 | * level 2: all io interrupts disabled (timer still enabled) |
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| 356 | * level 7: *ALL* disabled (timer disabled) |
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| 357 | */ |
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| 358 | |
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| 359 | /* set interrupts on or off; does not return new level */ |
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| 360 | #define _CPU_ISR_Set_level( new_level ) \ |
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| 361 | { \ |
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| 362 | volatile int ignore; \ |
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| 363 | if ( new_level ) HPPA_ASM_RSM(HPPA_PSW_I, ignore); \ |
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| 364 | else HPPA_ASM_SSM(HPPA_PSW_I, ignore); \ |
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| 365 | } |
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| 366 | |
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[11290355] | 367 | /* return current level */ |
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| 368 | unsigned32 _CPU_ISR_Get_level( void ); |
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| 369 | |
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[ac7d5ef0] | 370 | /* end of ISR handler macros */ |
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| 371 | |
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| 372 | /* |
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| 373 | * Context handler macros |
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| 374 | * |
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| 375 | * These macros perform the following functions: |
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| 376 | * + initialize a context area |
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| 377 | * + restart the current thread |
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| 378 | * + calculate the initial pointer into a FP context area |
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| 379 | * + initialize an FP context area |
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| 380 | * |
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| 381 | * HPPA port adds two macros which hide the "indirectness" of the |
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| 382 | * pointer passed the save/restore FP context assembly routines. |
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| 383 | */ |
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| 384 | |
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| 385 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
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[9700578] | 386 | _new_level, _entry_point, _is_fp ) \ |
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[ac7d5ef0] | 387 | do { \ |
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| 388 | unsigned32 _stack; \ |
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| 389 | \ |
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| 390 | (_the_context)->flags = 0xfeedf00d; \ |
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| 391 | (_the_context)->pcoqfront = (unsigned32)(_entry_point); \ |
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| 392 | (_the_context)->pcoqback = (unsigned32)(_entry_point) + 4; \ |
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| 393 | (_the_context)->pcsqfront = 0; \ |
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| 394 | (_the_context)->pcsqback = 0; \ |
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| 395 | if ( (_new_level) ) \ |
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| 396 | (_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \ |
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| 397 | else \ |
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| 398 | (_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \ |
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| 399 | \ |
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| 400 | _stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \ |
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| 401 | _stack &= ~(CPU_STACK_ALIGNMENT - 1); \ |
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| 402 | if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \ |
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| 403 | _stack += CPU_FRAME_SIZE; \ |
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| 404 | \ |
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| 405 | (_the_context)->sp = (_stack); \ |
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| 406 | (_the_context)->gr27 = _CPU_Default_gr27; \ |
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| 407 | } while (0) |
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| 408 | |
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| 409 | #define _CPU_Context_Restart_self( _the_context ) \ |
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| 410 | do { \ |
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| 411 | _CPU_Context_restore( (_the_context) ); \ |
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| 412 | } while (0) |
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| 413 | |
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| 414 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
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| 415 | ( (void *) (_base) + (_offset) ) |
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| 416 | |
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| 417 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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| 418 | do { \ |
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| 419 | *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\ |
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| 420 | } while(0) |
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| 421 | |
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| 422 | #define _CPU_Context_save_fp( _fp_context ) \ |
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| 423 | _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context) ) |
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| 424 | |
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| 425 | #define _CPU_Context_restore_fp( _fp_context ) \ |
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| 426 | _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context) ) |
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| 427 | |
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| 428 | /* end of Context handler macros */ |
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| 429 | |
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| 430 | /* |
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| 431 | * Fatal Error manager macros |
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| 432 | * |
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| 433 | * These macros perform the following functions: |
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| 434 | * + disable interrupts and halt the CPU |
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| 435 | */ |
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| 436 | |
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[c64e4ed4] | 437 | void hppa_cpu_halt(unsigned32 the_error); |
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[ac7d5ef0] | 438 | #define _CPU_Fatal_halt( _error ) \ |
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[c64e4ed4] | 439 | hppa_cpu_halt(_error) |
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[ac7d5ef0] | 440 | |
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| 441 | /* end of Fatal Error manager macros */ |
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| 442 | |
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| 443 | /* |
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| 444 | * Bitfield handler macros |
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| 445 | * |
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| 446 | * These macros perform the following functions: |
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| 447 | * + scan for the highest numbered (MSB) set in a 16 bit bitfield |
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| 448 | * |
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| 449 | * NOTE: |
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| 450 | * |
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| 451 | * The HPPA does not have a scan instruction. This functionality |
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| 452 | * is implemented in software. |
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| 453 | */ |
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| 454 | |
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[9700578] | 455 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
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| 456 | #define CPU_USE_GENERIC_BITFIELD_DATA FALSE |
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| 457 | |
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[ac7d5ef0] | 458 | int hppa_rtems_ffs(unsigned int value); |
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| 459 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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| 460 | _output = hppa_rtems_ffs(_value) |
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| 461 | |
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| 462 | /* end of Bitfield handler macros */ |
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| 463 | |
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| 464 | /* |
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| 465 | * Priority handler macros |
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| 466 | * |
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| 467 | * These macros perform the following functions: |
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| 468 | * + return a mask with the bit for this major/minor portion of |
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| 469 | * of thread priority set. |
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| 470 | * + translate the bit number returned by "Bitfield_find_first_bit" |
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| 471 | * into an index into the thread ready chain bit maps |
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| 472 | * |
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| 473 | * Note: 255 is the lowest priority |
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| 474 | */ |
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| 475 | |
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| 476 | #define _CPU_Priority_Mask( _bit_number ) \ |
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| 477 | ( 1 << (_bit_number) ) |
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| 478 | |
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[9700578] | 479 | #define _CPU_Priority_bits_index( _priority ) \ |
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[ac7d5ef0] | 480 | (_priority) |
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| 481 | |
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| 482 | /* end of Priority handler macros */ |
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| 483 | |
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| 484 | /* functions */ |
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| 485 | |
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| 486 | /* |
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| 487 | * _CPU_Initialize |
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| 488 | * |
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| 489 | * This routine performs CPU dependent initialization. |
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| 490 | */ |
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| 491 | |
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| 492 | void _CPU_Initialize( |
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| 493 | rtems_cpu_table *cpu_table, |
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| 494 | void (*thread_dispatch) |
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| 495 | ); |
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| 496 | |
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[637df35] | 497 | /* |
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| 498 | * _CPU_ISR_install_raw_handler |
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| 499 | * |
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| 500 | * This routine installs a "raw" interrupt handler directly into the |
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| 501 | * processor's vector table. |
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| 502 | */ |
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| 503 | |
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| 504 | void _CPU_ISR_install_raw_handler( |
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| 505 | unsigned32 vector, |
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| 506 | proc_ptr new_handler, |
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| 507 | proc_ptr *old_handler |
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| 508 | ); |
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| 509 | |
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[ac7d5ef0] | 510 | /* |
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| 511 | * _CPU_ISR_install_vector |
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| 512 | * |
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| 513 | * This routine installs an interrupt vector. |
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| 514 | */ |
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| 515 | |
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| 516 | void _CPU_ISR_install_vector( |
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| 517 | unsigned32 vector, |
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| 518 | proc_ptr new_handler, |
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| 519 | proc_ptr *old_handler |
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| 520 | ); |
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| 521 | |
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| 522 | /* |
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| 523 | * _CPU_Context_switch |
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| 524 | * |
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| 525 | * This routine switches from the run context to the heir context. |
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| 526 | */ |
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| 527 | |
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| 528 | void _CPU_Context_switch( |
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| 529 | Context_Control *run, |
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| 530 | Context_Control *heir |
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| 531 | ); |
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| 532 | |
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| 533 | /* |
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| 534 | * _CPU_Context_restore |
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| 535 | * |
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| 536 | * This routine is generally used only to restart self in an |
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| 537 | * efficient manner and avoid stack conflicts. |
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| 538 | */ |
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| 539 | |
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| 540 | void _CPU_Context_restore( |
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| 541 | Context_Control *new_context |
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| 542 | ); |
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| 543 | |
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| 544 | /* |
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| 545 | * _CPU_Save_float_context |
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| 546 | * |
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| 547 | * This routine saves the floating point context passed to it. |
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| 548 | * |
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| 549 | * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA |
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| 550 | * which dereferences the pointer before calling this. |
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| 551 | */ |
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| 552 | |
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| 553 | void _CPU_Save_float_context( |
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| 554 | Context_Control_fp *fp_context |
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| 555 | ); |
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| 556 | |
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| 557 | /* |
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| 558 | * _CPU_Restore_float_context |
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| 559 | * |
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| 560 | * This routine restores the floating point context passed to it. |
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| 561 | * |
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| 562 | * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA |
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| 563 | * which dereferences the pointer before calling this. |
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| 564 | */ |
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| 565 | |
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| 566 | void _CPU_Restore_float_context( |
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| 567 | Context_Control_fp *fp_context |
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| 568 | ); |
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| 569 | |
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| 570 | |
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| 571 | /* The following routine swaps the endian format of an unsigned int. |
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| 572 | * It must be static so it can be referenced indirectly. |
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| 573 | */ |
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| 574 | |
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| 575 | static inline unsigned int |
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| 576 | CPU_swap_u32(unsigned32 value) |
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| 577 | { |
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| 578 | unsigned32 swapped; |
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| 579 | |
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| 580 | HPPA_ASM_SWAPBYTES(value, swapped); |
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| 581 | |
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| 582 | return( swapped ); |
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| 583 | } |
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| 584 | |
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| 585 | /* |
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| 586 | * Unused; I think it should go away |
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| 587 | */ |
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| 588 | |
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| 589 | #if 0 |
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| 590 | #define enable_tracing() |
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| 591 | #endif |
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| 592 | |
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| 593 | #endif /* ! ASM */ |
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| 594 | |
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| 595 | #ifdef __cplusplus |
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| 596 | } |
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| 597 | #endif |
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| 598 | |
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| 599 | #endif /* ! __CPU_h */ |
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