1 | /* |
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2 | * HP PA-RISC Dependent Source |
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3 | * |
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4 | * COPYRIGHT (c) 1994 by Division Incorporated |
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5 | * |
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6 | * To anyone who acknowledges that this file is provided "AS IS" |
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7 | * without any express or implied warranty: |
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8 | * permission to use, copy, modify, and distribute this file |
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9 | * for any purpose is hereby granted without fee, provided that |
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10 | * the above copyright notice and this notice appears in all |
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11 | * copies, and that the name of Division Incorporated not be |
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12 | * used in advertising or publicity pertaining to distribution |
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13 | * of the software without specific, written prior permission. |
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14 | * Division Incorporated makes no representations about the |
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15 | * suitability of this software for any purpose. |
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16 | * |
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17 | * $Id$ |
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18 | */ |
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19 | |
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20 | #include <rtems/system.h> |
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21 | #include <rtems/score/isr.h> |
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22 | |
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23 | void hppa_external_interrupt_initialize(void); |
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24 | void hppa_external_interrupt_enable(unsigned32); |
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25 | void hppa_external_interrupt_disable(unsigned32); |
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26 | void hppa_external_interrupt(unsigned32, CPU_Interrupt_frame *); |
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27 | void hppa_cpu_halt(unsigned32); |
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28 | |
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29 | /* |
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30 | * The first level interrupt handler for first 32 interrupts/traps. |
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31 | * Indexed by vector; generally each entry is _Generic_ISR_Handler. |
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32 | * Some TLB traps may have their own first level handler. |
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33 | */ |
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34 | |
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35 | extern void _Generic_ISR_Handler(void); |
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36 | unsigned32 HPPA_first_level_interrupt_handler[HPPA_INTERNAL_INTERRUPTS]; |
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37 | |
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38 | /* _CPU_Initialize |
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39 | * |
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40 | * This routine performs processor dependent initialization. |
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41 | * |
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42 | * INPUT PARAMETERS: |
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43 | * cpu_table - CPU table to initialize |
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44 | * thread_dispatch - address of disptaching routine |
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45 | * |
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46 | */ |
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47 | |
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48 | void _CPU_Initialize( |
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49 | rtems_cpu_table *cpu_table, |
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50 | void (*thread_dispatch) /* ignored on this CPU */ |
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51 | ) |
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52 | { |
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53 | register unsigned8 *fp_context; |
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54 | unsigned32 iva; |
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55 | unsigned32 iva_table; |
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56 | int i; |
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57 | |
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58 | extern void IVA_Table(void); |
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59 | |
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60 | /* |
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61 | * XXX; need to setup fpsr smarter perhaps |
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62 | */ |
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63 | |
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64 | fp_context = (unsigned8*) &_CPU_Null_fp_context; |
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65 | for (i=0 ; i<sizeof(Context_Control_fp); i++) |
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66 | *fp_context++ = 0; |
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67 | |
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68 | /* |
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69 | * Set _CPU_Default_gr27 here so it will hopefully be the correct |
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70 | * global data pointer for the entire system. |
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71 | */ |
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72 | |
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73 | asm volatile( "stw %%r27,%0" : "=m" (_CPU_Default_gr27): ); |
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74 | |
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75 | /* |
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76 | * Init the first level interrupt handlers |
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77 | */ |
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78 | |
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79 | for (i=0; i <= HPPA_INTERNAL_INTERRUPTS; i++) |
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80 | HPPA_first_level_interrupt_handler[i] = (unsigned32) _Generic_ISR_Handler; |
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81 | |
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82 | /* |
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83 | * Init the 2nd level interrupt handlers |
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84 | */ |
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85 | |
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86 | for (i=0; i <= CPU_INTERRUPT_NUMBER_OF_VECTORS; i++) |
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87 | _ISR_Vector_table[i] = (ISR_Handler_entry) hppa_cpu_halt; |
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88 | |
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89 | /* |
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90 | * Stabilize the interrupt stuff |
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91 | */ |
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92 | |
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93 | (void) hppa_external_interrupt_initialize(); |
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94 | |
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95 | /* |
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96 | * Set the IVA to point to physical address of the IVA_Table |
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97 | */ |
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98 | |
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99 | iva_table = (unsigned32) IVA_Table; |
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100 | #if defined(hppa1_1) |
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101 | /* |
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102 | * HACK: (from PA72000 TRM, page 4-19) |
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103 | * "The hardware TLB miss handler will never attempt to service |
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104 | * a non-access TLB miss or a TLB protection violation. It |
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105 | * will only attempt to service TLB accesses that would cause |
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106 | * Trap Numbers 6 (Instruction TLB miss) and 15 (Data TLB miss)." |
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107 | * |
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108 | * The LPA instruction is used to translate a virtual address to |
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109 | * a physical address, however, if the requested virtual address |
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110 | * is not currently resident in the TLB, the hardware TLB miss |
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111 | * handler will NOT insert it. In this situation Trap Number |
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112 | * #17 is invoked (Non-access Data TLB miss fault). |
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113 | * |
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114 | * To work around this, a dummy data access is first performed |
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115 | * to the virtual address prior to the LPA. The dummy access |
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116 | * causes the TLB entry to be inserted (if not already present) |
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117 | * and then the following LPA instruction will not generate |
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118 | * a non-access data TLB miss fault. |
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119 | * |
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120 | * It is unclear whether or not this behaves the same way for |
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121 | * the PA8000. |
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122 | * |
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123 | */ |
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124 | iva = *(volatile unsigned32 *)iva_table; /* dummy access */ |
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125 | #endif |
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126 | |
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127 | HPPA_ASM_LPA(0, iva_table, iva); |
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128 | set_iva(iva); |
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129 | |
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130 | _CPU_Table = *cpu_table; |
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131 | } |
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132 | |
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133 | /*PAGE |
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134 | * |
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135 | * _CPU_ISR_Get_level |
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136 | */ |
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137 | |
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138 | unsigned32 _CPU_ISR_Get_level(void) |
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139 | { |
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140 | int level; |
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141 | HPPA_ASM_SSM(0, level); /* change no bits; just get copy */ |
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142 | if (level & HPPA_PSW_I) |
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143 | return 0; |
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144 | return 1; |
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145 | } |
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146 | |
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147 | /*PAGE |
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148 | * |
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149 | * _CPU_ISR_install_raw_handler |
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150 | */ |
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151 | |
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152 | void _CPU_ISR_install_raw_handler( |
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153 | unsigned32 vector, |
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154 | proc_ptr new_handler, |
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155 | proc_ptr *old_handler |
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156 | ) |
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157 | { |
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158 | /* |
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159 | * This is unsupported. |
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160 | */ |
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161 | |
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162 | _CPU_Fatal_halt( 0xdeaddead ); |
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163 | } |
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164 | |
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165 | /*PAGE |
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166 | * |
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167 | * _CPU_ISR_install_vector |
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168 | * |
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169 | * This kernel routine installs the RTEMS handler for the |
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170 | * specified vector. |
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171 | * |
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172 | * Input parameters: |
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173 | * vector - interrupt vector number |
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174 | * old_handler - former ISR for this vector number |
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175 | * new_handler - replacement ISR for this vector number |
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176 | * |
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177 | * Output parameters: NONE |
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178 | * |
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179 | */ |
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180 | |
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181 | /* |
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182 | * HPPA has 8w for each vector instead of an address to jump to. |
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183 | * We put the actual ISR address in '_ISR_vector_table'. This will |
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184 | * be pulled by the code in the vector. |
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185 | */ |
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186 | |
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187 | void _CPU_ISR_install_vector( |
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188 | unsigned32 vector, |
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189 | proc_ptr new_handler, |
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190 | proc_ptr *old_handler |
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191 | ) |
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192 | { |
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193 | *old_handler = _ISR_Vector_table[vector]; |
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194 | |
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195 | _ISR_Vector_table[vector] = new_handler; |
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196 | |
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197 | if (vector >= HPPA_INTERRUPT_EXTERNAL_BASE) |
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198 | { |
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199 | unsigned32 external_vector; |
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200 | |
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201 | external_vector = vector - HPPA_INTERRUPT_EXTERNAL_BASE; |
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202 | if (new_handler) |
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203 | hppa_external_interrupt_enable(external_vector); |
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204 | else |
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205 | /* XXX this can never happen due to _ISR_Is_valid_user_handler */ |
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206 | hppa_external_interrupt_disable(external_vector); |
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207 | } |
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208 | } |
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209 | |
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210 | |
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211 | /* |
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212 | * Support for external and spurious interrupts on HPPA |
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213 | * |
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214 | * TODO: |
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215 | * Count interrupts |
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216 | * make sure interrupts disabled properly |
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217 | */ |
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218 | |
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219 | #define DISMISS(mask) set_eirr(mask) |
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220 | #define DISABLE(mask) set_eiem(get_eiem() & ~(mask)) |
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221 | #define ENABLE(mask) set_eiem(get_eiem() | (mask)) |
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222 | #define VECTOR_TO_MASK(v) (1 << (31 - (v))) |
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223 | |
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224 | /* |
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225 | * Init the external interrupt scheme |
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226 | * called by bsp_start() |
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227 | */ |
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228 | |
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229 | void |
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230 | hppa_external_interrupt_initialize(void) |
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231 | { |
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232 | proc_ptr ignore; |
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233 | |
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234 | /* mark them all unused */ |
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235 | DISABLE(~0); |
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236 | DISMISS(~0); |
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237 | |
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238 | /* install the external interrupt handler */ |
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239 | _CPU_ISR_install_vector( |
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240 | HPPA_INTERRUPT_EXTERNAL_INTERRUPT, |
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241 | (proc_ptr)hppa_external_interrupt, &ignore |
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242 | ); |
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243 | } |
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244 | |
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245 | /* |
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246 | * Enable a specific external interrupt |
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247 | */ |
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248 | |
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249 | void |
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250 | hppa_external_interrupt_enable(unsigned32 v) |
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251 | { |
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252 | unsigned32 isrlevel; |
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253 | |
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254 | _CPU_ISR_Disable(isrlevel); |
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255 | ENABLE(VECTOR_TO_MASK(v)); |
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256 | _CPU_ISR_Enable(isrlevel); |
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257 | } |
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258 | |
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259 | /* |
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260 | * Does not clear or otherwise affect any pending requests |
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261 | */ |
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262 | |
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263 | void |
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264 | hppa_external_interrupt_disable(unsigned32 v) |
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265 | { |
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266 | unsigned32 isrlevel; |
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267 | |
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268 | _CPU_ISR_Disable(isrlevel); |
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269 | DISABLE(VECTOR_TO_MASK(v)); |
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270 | _CPU_ISR_Enable(isrlevel); |
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271 | } |
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272 | |
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273 | void |
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274 | hppa_external_interrupt_spurious_handler(unsigned32 vector, |
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275 | CPU_Interrupt_frame *iframe) |
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276 | { |
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277 | /* XXX should not be printing :) |
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278 | printf("spurious external interrupt: %d at pc 0x%x; disabling\n", |
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279 | vector, iframe->Interrupt.pcoqfront); |
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280 | */ |
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281 | } |
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282 | |
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283 | void |
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284 | hppa_external_interrupt_report_spurious(unsigned32 spurious_mask, |
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285 | CPU_Interrupt_frame *iframe) |
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286 | { |
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287 | int v; |
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288 | for (v=0; v < HPPA_EXTERNAL_INTERRUPTS; v++) |
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289 | if (VECTOR_TO_MASK(v) & spurious_mask) |
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290 | { |
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291 | DISMISS(VECTOR_TO_MASK(v)); |
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292 | DISABLE(VECTOR_TO_MASK(v)); |
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293 | hppa_external_interrupt_spurious_handler(v, iframe); |
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294 | } |
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295 | DISMISS(spurious_mask); |
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296 | } |
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297 | |
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298 | |
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299 | /* |
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300 | * External interrupt handler. |
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301 | * This is installed as cpu interrupt handler for |
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302 | * HPPA_INTERRUPT_EXTERNAL_INTERRUPT. It vectors out to |
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303 | * specific external interrupt handlers. |
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304 | */ |
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305 | |
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306 | void |
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307 | hppa_external_interrupt(unsigned32 vector, |
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308 | CPU_Interrupt_frame *iframe) |
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309 | { |
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310 | unsigned32 mask; |
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311 | unsigned32 *vp, *max_vp; |
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312 | unsigned32 external_vector; |
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313 | unsigned32 global_vector; |
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314 | hppa_rtems_isr_entry handler; |
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315 | |
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316 | max_vp = &_CPU_Table.external_interrupt[_CPU_Table.external_interrupts]; |
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317 | while ( (mask = (get_eirr() & get_eiem())) ) |
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318 | { |
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319 | for (vp = _CPU_Table.external_interrupt; (vp < max_vp) && mask; vp++) |
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320 | { |
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321 | unsigned32 m; |
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322 | |
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323 | external_vector = *vp; |
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324 | global_vector = external_vector + HPPA_INTERRUPT_EXTERNAL_BASE; |
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325 | m = VECTOR_TO_MASK(external_vector); |
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326 | handler = (hppa_rtems_isr_entry) _ISR_Vector_table[global_vector]; |
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327 | if ((m & mask) && handler) |
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328 | { |
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329 | DISMISS(m); |
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330 | mask &= ~m; |
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331 | handler(global_vector, iframe); |
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332 | } |
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333 | } |
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334 | |
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335 | if (mask != 0) { |
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336 | if ( _CPU_Table.spurious_handler ) |
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337 | { |
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338 | handler = (hppa_rtems_isr_entry) _CPU_Table.spurious_handler; |
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339 | handler(mask, iframe); |
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340 | } |
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341 | else |
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342 | hppa_external_interrupt_report_spurious(mask, iframe); |
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343 | } |
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344 | } |
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345 | } |
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346 | |
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347 | /* |
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348 | * Halt the system. |
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349 | * Called by the _CPU_Fatal_halt macro |
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350 | * |
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351 | * XXX |
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352 | * Later on, this will allow us to return to the prom. |
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353 | * For now, we just ignore 'type_of_halt' |
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354 | */ |
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355 | |
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356 | void |
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357 | hppa_cpu_halt(unsigned32 the_error) |
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358 | { |
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359 | unsigned32 isrlevel; |
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360 | |
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361 | _CPU_ISR_Disable(isrlevel); |
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362 | |
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363 | HPPA_ASM_LABEL("_hppa_cpu_halt"); |
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364 | HPPA_ASM_BREAK(1, 0); |
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365 | } |
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