[ac7d5ef0] | 1 | /* |
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| 2 | * HP PA-RISC Dependent Source |
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| 3 | * |
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| 4 | * COPYRIGHT (c) 1994 by Division Incorporated |
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| 5 | * |
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| 6 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 7 | * without any express or implied warranty: |
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| 8 | * permission to use, copy, modify, and distribute this file |
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| 9 | * for any purpose is hereby granted without fee, provided that |
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| 10 | * the above copyright notice and this notice appears in all |
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| 11 | * copies, and that the name of Division Incorporated not be |
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| 12 | * used in advertising or publicity pertaining to distribution |
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| 13 | * of the software without specific, written prior permission. |
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| 14 | * Division Incorporated makes no representations about the |
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| 15 | * suitability of this software for any purpose. |
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| 16 | * |
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[eb5a7e07] | 17 | * $Id$ |
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[ac7d5ef0] | 18 | */ |
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| 19 | |
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| 20 | #include <rtems/system.h> |
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[11290355] | 21 | #include <rtems/fatal.h> |
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| 22 | #include <rtems/core/isr.h> |
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| 23 | #include <rtems/core/wkspace.h> |
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[ac7d5ef0] | 24 | |
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[3a4ae6c] | 25 | void hppa_external_interrupt_initialize(void); |
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[ac7d5ef0] | 26 | void hppa_external_interrupt_enable(unsigned32); |
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| 27 | void hppa_external_interrupt_disable(unsigned32); |
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| 28 | void hppa_external_interrupt(unsigned32, CPU_Interrupt_frame *); |
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| 29 | |
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| 30 | /* |
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| 31 | * Our interrupt handlers take a 2nd argument: |
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| 32 | * a pointer to a CPU_Interrupt_frame |
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| 33 | * So we use our own prototype instead of rtems_isr_entry |
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| 34 | */ |
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| 35 | |
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[b3ac6a8d] | 36 | typedef void ( *hppa_rtems_isr_entry )( |
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| 37 | ISR_Vector_number, |
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[ac7d5ef0] | 38 | CPU_Interrupt_frame * |
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| 39 | ); |
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| 40 | |
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| 41 | |
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| 42 | /* |
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| 43 | * who are we? cpu number |
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| 44 | * Not used by executive proper, just kept (or not) as a convenience |
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| 45 | * for libcpu and libbsp stuff that wants it. |
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| 46 | * |
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| 47 | * Defaults to 0. If the BSP doesn't like it, it can change it. |
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| 48 | */ |
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| 49 | |
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| 50 | int cpu_number; /* from 0; cpu number in a multi cpu system */ |
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| 51 | |
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| 52 | |
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| 53 | /* _CPU_Initialize |
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| 54 | * |
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| 55 | * This routine performs processor dependent initialization. |
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| 56 | * |
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| 57 | * INPUT PARAMETERS: |
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| 58 | * cpu_table - CPU table to initialize |
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| 59 | * thread_dispatch - address of disptaching routine |
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| 60 | * |
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| 61 | */ |
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| 62 | |
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| 63 | void _CPU_Initialize( |
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| 64 | rtems_cpu_table *cpu_table, |
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| 65 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 66 | ) |
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| 67 | { |
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| 68 | register unsigned8 *fp_context; |
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| 69 | unsigned32 iva; |
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| 70 | unsigned32 iva_table; |
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| 71 | int i; |
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| 72 | |
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| 73 | extern void IVA_Table(void); |
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| 74 | |
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| 75 | /* |
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| 76 | * XXX; need to setup fpsr smarter perhaps |
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| 77 | */ |
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| 78 | |
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| 79 | fp_context = (unsigned8*) &_CPU_Null_fp_context; |
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| 80 | for (i=0 ; i<sizeof(Context_Control_fp); i++) |
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| 81 | *fp_context++ = 0; |
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| 82 | |
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| 83 | /* |
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| 84 | * Set _CPU_Default_gr27 here so it will hopefully be the correct |
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| 85 | * global data pointer for the entire system. |
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| 86 | */ |
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| 87 | |
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| 88 | asm volatile( "stw %%r27,%0" : "=m" (_CPU_Default_gr27): ); |
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| 89 | |
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| 90 | /* |
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| 91 | * Stabilize the interrupt stuff |
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| 92 | */ |
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| 93 | |
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| 94 | (void) hppa_external_interrupt_initialize(); |
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| 95 | |
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| 96 | /* |
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| 97 | * Set the IVA to point to physical address of the IVA_Table |
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| 98 | */ |
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| 99 | |
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| 100 | iva_table = (unsigned32) IVA_Table; |
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| 101 | HPPA_ASM_LPA(0, iva_table, iva); |
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| 102 | set_iva(iva); |
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| 103 | |
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| 104 | _CPU_Table = *cpu_table; |
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| 105 | } |
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| 106 | |
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[11290355] | 107 | /*PAGE |
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| 108 | * |
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| 109 | * _CPU_ISR_Get_level |
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| 110 | */ |
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| 111 | |
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| 112 | unsigned32 _CPU_ISR_Get_level(void) |
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| 113 | { |
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| 114 | int level; |
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| 115 | HPPA_ASM_SSM(0, level); /* change no bits; just get copy */ |
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| 116 | if (level & HPPA_PSW_I) |
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| 117 | return 1; |
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| 118 | return 0; |
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| 119 | } |
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| 120 | |
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[637df35] | 121 | /*PAGE |
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| 122 | * |
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| 123 | * _CPU_ISR_install_raw_handler |
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| 124 | */ |
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| 125 | |
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| 126 | void _CPU_ISR_install_raw_handler( |
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| 127 | unsigned32 vector, |
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| 128 | proc_ptr new_handler, |
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| 129 | proc_ptr *old_handler |
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| 130 | ) |
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| 131 | { |
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| 132 | /* |
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| 133 | * This is unsupported. |
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| 134 | */ |
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| 135 | |
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| 136 | _CPU_Fatal_halt( 0xdeaddead ); |
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| 137 | } |
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| 138 | |
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| 139 | /*PAGE |
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| 140 | * |
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| 141 | * _CPU_ISR_install_vector |
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[ac7d5ef0] | 142 | * |
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| 143 | * This kernel routine installs the RTEMS handler for the |
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| 144 | * specified vector. |
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| 145 | * |
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| 146 | * Input parameters: |
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| 147 | * vector - interrupt vector number |
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| 148 | * old_handler - former ISR for this vector number |
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| 149 | * new_handler - replacement ISR for this vector number |
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| 150 | * |
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| 151 | * Output parameters: NONE |
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| 152 | * |
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| 153 | */ |
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| 154 | |
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| 155 | /* |
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| 156 | * HPPA has 8w for each vector instead of an address to jump to. |
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| 157 | * We put the actual ISR address in '_ISR_vector_table'. This will |
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| 158 | * be pulled by the code in the vector. |
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| 159 | */ |
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| 160 | |
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| 161 | void _CPU_ISR_install_vector( |
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| 162 | unsigned32 vector, |
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| 163 | proc_ptr new_handler, |
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| 164 | proc_ptr *old_handler |
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| 165 | ) |
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| 166 | { |
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| 167 | *old_handler = _ISR_Vector_table[vector]; |
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| 168 | |
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| 169 | _ISR_Vector_table[vector] = new_handler; |
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| 170 | |
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| 171 | if (vector >= HPPA_INTERRUPT_EXTERNAL_BASE) |
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| 172 | { |
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| 173 | unsigned32 external_vector; |
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| 174 | |
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| 175 | external_vector = vector - HPPA_INTERRUPT_EXTERNAL_BASE; |
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| 176 | if (new_handler) |
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| 177 | hppa_external_interrupt_enable(external_vector); |
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| 178 | else |
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| 179 | /* XXX this can never happen due to _ISR_Is_valid_user_handler */ |
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| 180 | hppa_external_interrupt_disable(external_vector); |
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| 181 | } |
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| 182 | } |
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| 183 | |
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| 184 | |
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| 185 | /* |
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| 186 | * Support for external and spurious interrupts on HPPA |
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| 187 | * |
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| 188 | * TODO: |
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| 189 | * delete interrupt.c etc. |
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| 190 | * Count interrupts |
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| 191 | * make sure interrupts disabled properly |
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| 192 | * should handler check again for more interrupts before exit? |
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| 193 | * How to enable interrupts from an interrupt handler? |
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| 194 | * Make sure there is an entry for everything in ISR_Vector_Table |
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| 195 | */ |
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| 196 | |
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| 197 | #define DISMISS(mask) set_eirr(mask) |
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| 198 | #define DISABLE(mask) set_eiem(get_eiem() & ~(mask)) |
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| 199 | #define ENABLE(mask) set_eiem(get_eiem() | (mask)) |
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| 200 | #define VECTOR_TO_MASK(v) (1 << (31 - (v))) |
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| 201 | |
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| 202 | /* |
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| 203 | * Init the external interrupt scheme |
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| 204 | * called by bsp_start() |
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| 205 | */ |
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| 206 | |
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[3a4ae6c] | 207 | void |
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[ac7d5ef0] | 208 | hppa_external_interrupt_initialize(void) |
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| 209 | { |
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[591d45e] | 210 | proc_ptr ignore; |
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[ac7d5ef0] | 211 | |
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| 212 | /* mark them all unused */ |
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| 213 | |
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| 214 | DISABLE(~0); |
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| 215 | DISMISS(~0); |
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| 216 | |
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| 217 | /* install the external interrupt handler */ |
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[3652ad35] | 218 | _CPU_ISR_install_vector( |
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| 219 | HPPA_INTERRUPT_EXTERNAL_INTERRUPT, |
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| 220 | (proc_ptr)hppa_external_interrupt, |
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[591d45e] | 221 | &ignore |
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[3652ad35] | 222 | ); |
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[ac7d5ef0] | 223 | } |
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| 224 | |
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| 225 | /* |
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| 226 | * Enable a specific external interrupt |
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| 227 | */ |
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| 228 | |
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| 229 | void |
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| 230 | hppa_external_interrupt_enable(unsigned32 v) |
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| 231 | { |
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| 232 | unsigned32 isrlevel; |
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| 233 | |
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| 234 | _CPU_ISR_Disable(isrlevel); |
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| 235 | ENABLE(VECTOR_TO_MASK(v)); |
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| 236 | _CPU_ISR_Enable(isrlevel); |
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| 237 | } |
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| 238 | |
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| 239 | /* |
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| 240 | * Does not clear or otherwise affect any pending requests |
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| 241 | */ |
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| 242 | |
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| 243 | void |
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| 244 | hppa_external_interrupt_disable(unsigned32 v) |
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| 245 | { |
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| 246 | unsigned32 isrlevel; |
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| 247 | |
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| 248 | _CPU_ISR_Disable(isrlevel); |
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| 249 | DISABLE(VECTOR_TO_MASK(v)); |
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| 250 | _CPU_ISR_Enable(isrlevel); |
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| 251 | } |
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| 252 | |
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| 253 | void |
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| 254 | hppa_external_interrupt_spurious_handler(unsigned32 vector, |
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| 255 | CPU_Interrupt_frame *iframe) |
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| 256 | { |
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| 257 | /* XXX should not be printing :) |
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| 258 | printf("spurious external interrupt: %d at pc 0x%x; disabling\n", |
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| 259 | vector, iframe->Interrupt.pcoqfront); |
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| 260 | */ |
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| 261 | DISMISS(VECTOR_TO_MASK(vector)); |
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| 262 | DISABLE(VECTOR_TO_MASK(vector)); |
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| 263 | } |
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| 264 | |
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| 265 | void |
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| 266 | hppa_external_interrupt_report_spurious(unsigned32 spurious, |
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| 267 | CPU_Interrupt_frame *iframe) |
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| 268 | { |
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| 269 | int v; |
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| 270 | for (v=0; v < HPPA_EXTERNAL_INTERRUPTS; v++) |
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| 271 | if (VECTOR_TO_MASK(v) & spurious) |
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| 272 | hppa_external_interrupt_spurious_handler(v, iframe); |
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| 273 | DISMISS(spurious); |
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| 274 | } |
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| 275 | |
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| 276 | |
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| 277 | /* |
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| 278 | * External interrupt handler. |
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| 279 | * This is installed as cpu interrupt handler for |
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| 280 | * HPPA_INTERRUPT_EXTERNAL_INTERRUPT. It vectors out to |
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| 281 | * specific external interrupt handlers. |
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| 282 | */ |
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| 283 | |
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| 284 | void |
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| 285 | hppa_external_interrupt(unsigned32 vector, |
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| 286 | CPU_Interrupt_frame *iframe) |
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| 287 | { |
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| 288 | unsigned32 mask; |
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| 289 | unsigned32 *vp, *max_vp; |
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| 290 | unsigned32 external_vector; |
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| 291 | unsigned32 global_vector; |
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| 292 | hppa_rtems_isr_entry handler; |
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| 293 | |
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| 294 | max_vp = &_CPU_Table.external_interrupt[_CPU_Table.external_interrupts]; |
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| 295 | while ( (mask = (get_eirr() & get_eiem())) ) |
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| 296 | { |
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| 297 | for (vp = _CPU_Table.external_interrupt; (vp < max_vp) && mask; vp++) |
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| 298 | { |
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| 299 | unsigned32 m; |
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| 300 | |
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| 301 | external_vector = *vp; |
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| 302 | global_vector = external_vector + HPPA_INTERRUPT_EXTERNAL_BASE; |
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| 303 | m = VECTOR_TO_MASK(external_vector); |
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| 304 | handler = (hppa_rtems_isr_entry) _ISR_Vector_table[global_vector]; |
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| 305 | if ((m & mask) && handler) |
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| 306 | { |
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| 307 | DISMISS(m); |
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| 308 | mask &= ~m; |
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| 309 | (*handler)(global_vector, iframe); |
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| 310 | } |
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| 311 | } |
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| 312 | |
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| 313 | if (mask != 0) { |
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| 314 | if ( _CPU_Table.spurious_handler ) |
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| 315 | (*((hppa_rtems_isr_entry) _CPU_Table.spurious_handler))( |
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| 316 | mask, |
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| 317 | iframe |
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| 318 | ); |
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| 319 | else |
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| 320 | hppa_external_interrupt_report_spurious(mask, iframe); |
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| 321 | } |
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| 322 | } |
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| 323 | } |
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| 324 | |
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| 325 | /* |
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| 326 | * Halt the system. |
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| 327 | * Called by the _CPU_Fatal_halt macro |
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| 328 | * |
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| 329 | * XXX |
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| 330 | * Later on, this will allow us to return to the prom. |
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| 331 | * For now, we just ignore 'type_of_halt' |
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| 332 | */ |
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| 333 | |
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| 334 | void |
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| 335 | hppa_cpu_halt(unsigned32 type_of_halt, |
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| 336 | unsigned32 the_error) |
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| 337 | { |
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| 338 | unsigned32 isrlevel; |
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| 339 | |
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| 340 | _CPU_ISR_Disable(isrlevel); |
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| 341 | |
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| 342 | asm volatile( "copy %0,%%r1" : : "r" (the_error) ); |
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| 343 | HPPA_ASM_BREAK(1, 0); |
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| 344 | } |
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