source: rtems/c/src/exec/score/cpu/h8300/rtems/score/cpu.h @ fb31e1a2

4.104.114.84.95
Last change on this file since fb31e1a2 was fb31e1a2, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 17, 2000 at 1:01:44 PM

Update from Philip Quaife <rtemsdev@…> that was hand-merged.
This update addresses the following:

+ the ISR enable/disable/flash macros now work with old gcc versions.
+ the UI CCR bits are now masked since other example code did so
+ _ISR_Dispatch disables interrupts during call setup

Together these removed the instabilities he was seeing.

  • Property mode set to 100644
File size: 33.2 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the XXX
4 *  processor.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __CPU_h
17#define __CPU_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#include <rtems/score/h8300.h>               /* pick up machine definitions */
24#ifndef ASM
25#include <rtems/score/h8300types.h>
26#endif
27
28/* conditional compilation parameters */
29
30/*
31 *  Should the calls to _Thread_Enable_dispatch be inlined?
32 *
33 *  If TRUE, then they are inlined.
34 *  If FALSE, then a subroutine call is made.
35 *
36 *  Basically this is an example of the classic trade-off of size
37 *  versus speed.  Inlining the call (TRUE) typically increases the
38 *  size of RTEMS while speeding up the enabling of dispatching.
39 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
40 *  only be 0 or 1 unless you are in an interrupt handler and that
41 *  interrupt handler invokes the executive.]  When not inlined
42 *  something calls _Thread_Enable_dispatch which in turns calls
43 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
44 *  one subroutine call is avoided entirely.]
45 *
46 *  H8300 Specific Information:
47 *
48 *  XXX
49 */
50
51#define CPU_INLINE_ENABLE_DISPATCH       FALSE
52
53/*
54 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
55 *  be unrolled one time?  In unrolled each iteration of the loop examines
56 *  two "nodes" on the chain being searched.  Otherwise, only one node
57 *  is examined per iteration.
58 *
59 *  If TRUE, then the loops are unrolled.
60 *  If FALSE, then the loops are not unrolled.
61 *
62 *  The primary factor in making this decision is the cost of disabling
63 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
64 *  body of the loop.  On some CPUs, the flash is more expensive than
65 *  one iteration of the loop body.  In this case, it might be desirable
66 *  to unroll the loop.  It is important to note that on some CPUs, this
67 *  code is the longest interrupt disable period in RTEMS.  So it is
68 *  necessary to strike a balance when setting this parameter.
69 *
70 *  H8300 Specific Information:
71 *
72 *  XXX
73 */
74
75#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
76
77/*
78 *  Does RTEMS manage a dedicated interrupt stack in software?
79 *
80 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
81 *  If FALSE, nothing is done.
82 *
83 *  If the CPU supports a dedicated interrupt stack in hardware,
84 *  then it is generally the responsibility of the BSP to allocate it
85 *  and set it up.
86 *
87 *  If the CPU does not support a dedicated interrupt stack, then
88 *  the porter has two options: (1) execute interrupts on the
89 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
90 *  interrupt stack.
91 *
92 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
93 *
94 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
95 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
96 *  possible that both are FALSE for a particular CPU.  Although it
97 *  is unclear what that would imply about the interrupt processing
98 *  procedure on that CPU.
99 *
100 *  H8300 Specific Information:
101 *
102 *  XXX
103 */
104
105#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
106
107/*
108 *  Does this CPU have hardware support for a dedicated interrupt stack?
109 *
110 *  If TRUE, then it must be installed during initialization.
111 *  If FALSE, then no installation is performed.
112 *
113 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
114 *
115 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
116 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
117 *  possible that both are FALSE for a particular CPU.  Although it
118 *  is unclear what that would imply about the interrupt processing
119 *  procedure on that CPU.
120 *
121 *  H8300 Specific Information:
122 *
123 *  XXX
124 */
125
126#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
127
128/*
129 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
130 *
131 *  If TRUE, then the memory is allocated during initialization.
132 *  If FALSE, then the memory is allocated during initialization.
133 *
134 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
135 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
136 *
137 *  H8300 Specific Information:
138 *
139 *  XXX
140 */
141
142#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
143
144/*
145 *  Does the CPU have hardware floating point?
146 *
147 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
148 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
149 *
150 *  If there is a FP coprocessor such as the i387 or mc68881, then
151 *  the answer is TRUE.
152 *
153 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
154 *  It indicates whether or not this CPU model has FP support.  For
155 *  example, it would be possible to have an i386_nofp CPU model
156 *  which set this to false to indicate that you have an i386 without
157 *  an i387 and wish to leave floating point support out of RTEMS.
158 *
159 *  H8300 Specific Information:
160 *
161 *  XXX
162 */
163
164#define CPU_HARDWARE_FP     FALSE
165
166/*
167 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
168 *
169 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
170 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
171 *
172 *  So far, the only CPU in which this option has been used is the
173 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
174 *  floating point registers to perform integer multiplies.  If
175 *  a function which you would not think utilize the FP unit DOES,
176 *  then one can not easily predict which tasks will use the FP hardware.
177 *  In this case, this option should be TRUE.
178 *
179 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
180 *
181 *  H8300 Specific Information:
182 *
183 *  XXX
184 */
185
186#define CPU_ALL_TASKS_ARE_FP     FALSE
187
188/*
189 *  Should the IDLE task have a floating point context?
190 *
191 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
192 *  and it has a floating point context which is switched in and out.
193 *  If FALSE, then the IDLE task does not have a floating point context.
194 *
195 *  Setting this to TRUE negatively impacts the time required to preempt
196 *  the IDLE task from an interrupt because the floating point context
197 *  must be saved as part of the preemption.
198 *
199 *  H8300 Specific Information:
200 *
201 *  XXX
202 */
203
204#define CPU_IDLE_TASK_IS_FP      FALSE
205
206/*
207 *  Should the saving of the floating point registers be deferred
208 *  until a context switch is made to another different floating point
209 *  task?
210 *
211 *  If TRUE, then the floating point context will not be stored until
212 *  necessary.  It will remain in the floating point registers and not
213 *  disturned until another floating point task is switched to.
214 *
215 *  If FALSE, then the floating point context is saved when a floating
216 *  point task is switched out and restored when the next floating point
217 *  task is restored.  The state of the floating point registers between
218 *  those two operations is not specified.
219 *
220 *  If the floating point context does NOT have to be saved as part of
221 *  interrupt dispatching, then it should be safe to set this to TRUE.
222 *
223 *  Setting this flag to TRUE results in using a different algorithm
224 *  for deciding when to save and restore the floating point context.
225 *  The deferred FP switch algorithm minimizes the number of times
226 *  the FP context is saved and restored.  The FP context is not saved
227 *  until a context switch is made to another, different FP task.
228 *  Thus in a system with only one FP task, the FP context will never
229 *  be saved or restored.
230 *
231 *  H8300 Specific Information:
232 *
233 *  XXX
234 */
235
236#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
237
238/*
239 *  Does this port provide a CPU dependent IDLE task implementation?
240 *
241 *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
242 *  must be provided and is the default IDLE thread body instead of
243 *  _Internal_threads_Idle_thread_body.
244 *
245 *  If FALSE, then use the generic IDLE thread body if the BSP does
246 *  not provide one.
247 *
248 *  This is intended to allow for supporting processors which have
249 *  a low power or idle mode.  When the IDLE thread is executed, then
250 *  the CPU can be powered down.
251 *
252 *  The order of precedence for selecting the IDLE thread body is:
253 *
254 *    1.  BSP provided
255 *    2.  CPU dependent (if provided)
256 *    3.  generic (if no BSP and no CPU dependent)
257 *
258 *  H8300 Specific Information:
259 *
260 *  XXX
261 *  The port initially called a BSP dependent routine called
262 *  IDLE_Monitor.  The idle task body can be overridden by
263 *  the BSP in newer versions of RTEMS.
264 */
265
266#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
267
268/*
269 *  Does the stack grow up (toward higher addresses) or down
270 *  (toward lower addresses)?
271 *
272 *  If TRUE, then the grows upward.
273 *  If FALSE, then the grows toward smaller addresses.
274 *
275 *  H8300 Specific Information:
276 *
277 *  XXX
278 */
279
280#define CPU_STACK_GROWS_UP               FALSE
281
282/*
283 *  The following is the variable attribute used to force alignment
284 *  of critical RTEMS structures.  On some processors it may make
285 *  sense to have these aligned on tighter boundaries than
286 *  the minimum requirements of the compiler in order to have as
287 *  much of the critical data area as possible in a cache line.
288 *
289 *  The placement of this macro in the declaration of the variables
290 *  is based on the syntactically requirements of the GNU C
291 *  "__attribute__" extension.  For example with GNU C, use
292 *  the following to force a structures to a 32 byte boundary.
293 *
294 *      __attribute__ ((aligned (32)))
295 *
296 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
297 *         To benefit from using this, the data must be heavily
298 *         used so it will stay in the cache and used frequently enough
299 *         in the executive to justify turning this on.
300 *
301 *  H8300 Specific Information:
302 *
303 *  XXX
304 */
305
306#define CPU_STRUCTURE_ALIGNMENT
307
308/*
309 *  Define what is required to specify how the network to host conversion
310 *  routines are handled.
311 */
312
313#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
314#define CPU_BIG_ENDIAN                           TRUE
315#define CPU_LITTLE_ENDIAN                        FALSE
316
317/*
318 *  The following defines the number of bits actually used in the
319 *  interrupt field of the task mode.  How those bits map to the
320 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
321 *
322 *  H8300 Specific Information:
323 *
324 *  XXX
325 */
326
327#define CPU_MODES_INTERRUPT_MASK   0x00000001
328
329/*
330 *  Processor defined structures
331 *
332 *  Examples structures include the descriptor tables from the i386
333 *  and the processor control structure on the i960ca.
334 *
335 *  H8300 Specific Information:
336 *
337 *  XXX
338 */
339
340/* may need to put some structures here.  */
341
342/*
343 * Contexts
344 *
345 *  Generally there are 2 types of context to save.
346 *     1. Interrupt registers to save
347 *     2. Task level registers to save
348 *
349 *  This means we have the following 3 context items:
350 *     1. task level context stuff::  Context_Control
351 *     2. floating point task stuff:: Context_Control_fp
352 *     3. special interrupt level context :: Context_Control_interrupt
353 *
354 *  On some processors, it is cost-effective to save only the callee
355 *  preserved registers during a task context switch.  This means
356 *  that the ISR code needs to save those registers which do not
357 *  persist across function calls.  It is not mandatory to make this
358 *  distinctions between the caller/callee saves registers for the
359 *  purpose of minimizing context saved during task switch and on interrupts.
360 *  If the cost of saving extra registers is minimal, simplicity is the
361 *  choice.  Save the same context on interrupt entry as for tasks in
362 *  this case.
363 *
364 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
365 *  care should be used in designing the context area.
366 *
367 *  On some CPUs with hardware floating point support, the Context_Control_fp
368 *  structure will not be used or it simply consist of an array of a
369 *  fixed number of bytes.   This is done when the floating point context
370 *  is dumped by a "FP save context" type instruction and the format
371 *  is not really defined by the CPU.  In this case, there is no need
372 *  to figure out the exact format -- only the size.  Of course, although
373 *  this is enough information for RTEMS, it is probably not enough for
374 *  a debugger such as gdb.  But that is another problem.
375 *
376 *  H8300 Specific Information:
377 *
378 *  XXX
379 */
380
381
382
383#define nogap __attribute__ ((packed))
384
385typedef struct {
386    unsigned16  ccr nogap;
387    void        *er7 nogap;
388    void        *er6 nogap;
389    unsigned32  er5 nogap;
390    unsigned32  er4 nogap;
391    unsigned32  er3 nogap;
392    unsigned32  er2 nogap;
393    unsigned32  er1 nogap;
394    unsigned32  er0 nogap;
395    unsigned32  xxx nogap;
396} Context_Control;
397
398typedef struct {
399    double      some_float_register[2];
400} Context_Control_fp;
401
402typedef struct {
403    unsigned32 special_interrupt_register;
404} CPU_Interrupt_frame;
405
406
407/*
408 *  The following table contains the information required to configure
409 *  the XXX processor specific parameters.
410 *
411 *  NOTE: The interrupt_stack_size field is required if
412 *        CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
413 *
414 *        The pretasking_hook, predriver_hook, and postdriver_hook,
415 *        and the do_zero_of_workspace fields are required on ALL CPUs.
416 *
417 *  H8300 Specific Information:
418 *
419 *  XXX
420 */
421
422typedef struct {
423  void       (*pretasking_hook)( void );
424  void       (*predriver_hook)( void );
425  void       (*postdriver_hook)( void );
426  void       (*idle_task)( void );
427  boolean      do_zero_of_workspace;
428  unsigned32   idle_task_stack_size;
429  unsigned32   interrupt_stack_size;
430  unsigned32   extra_mpci_receive_server_stack;
431  void *     (*stack_allocate_hook)( unsigned32 );
432  void       (*stack_free_hook)( void* );
433}   rtems_cpu_table;
434
435/*
436 *  This variable is optional.  It is used on CPUs on which it is difficult
437 *  to generate an "uninitialized" FP context.  It is filled in by
438 *  _CPU_Initialize and copied into the task's FP context area during
439 *  _CPU_Context_Initialize.
440 *
441 *  H8300 Specific Information:
442 *
443 *  XXX
444 */
445
446SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
447
448/*
449 *  On some CPUs, RTEMS supports a software managed interrupt stack.
450 *  This stack is allocated by the Interrupt Manager and the switch
451 *  is performed in _ISR_Handler.  These variables contain pointers
452 *  to the lowest and highest addresses in the chunk of memory allocated
453 *  for the interrupt stack.  Since it is unknown whether the stack
454 *  grows up or down (in general), this give the CPU dependent
455 *  code the option of picking the version it wants to use.
456 *
457 *  NOTE: These two variables are required if the macro
458 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
459 *
460 *  H8300 Specific Information:
461 *
462 *  XXX
463 */
464
465SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
466SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
467
468/*
469 *  With some compilation systems, it is difficult if not impossible to
470 *  call a high-level language routine from assembly language.  This
471 *  is especially true of commercial Ada compilers and name mangling
472 *  C++ ones.  This variable can be optionally defined by the CPU porter
473 *  and contains the address of the routine _Thread_Dispatch.  This
474 *  can make it easier to invoke that routine at the end of the interrupt
475 *  sequence (if a dispatch is necessary).
476 *
477 *  H8300 Specific Information:
478 *
479 *  XXX
480 */
481
482SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
483
484/*
485 *  Nothing prevents the porter from declaring more CPU specific variables.
486 *
487 *  H8300 Specific Information:
488 *
489 *  XXX
490 */
491
492/* XXX: if needed, put more variables here */
493
494/*
495 *  The size of the floating point context area.  On some CPUs this
496 *  will not be a "sizeof" because the format of the floating point
497 *  area is not defined -- only the size is.  This is usually on
498 *  CPUs with a "floating point save context" instruction.
499 *
500 *  H8300 Specific Information:
501 *
502 *  XXX
503 */
504
505#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
506
507/*
508 *  Amount of extra stack (above minimum stack size) required by
509 *  system initialization thread.  Remember that in a multiprocessor
510 *  system the system intialization thread becomes the MP server thread.
511 *
512 *  H8300 Specific Information:
513 *
514 *  XXX
515 */
516
517#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
518
519/*
520 *  This defines the number of entries in the ISR_Vector_table managed
521 *  by RTEMS.
522 *
523 *  H8300 Specific Information:
524 *
525 *  XXX
526 */
527
528#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
529#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
530
531/*
532 *  Should be large enough to run all RTEMS tests.  This insures
533 *  that a "reasonable" small application should not have any problems.
534 *
535 *  H8300 Specific Information:
536 *
537 *  XXX
538 */
539
540#define CPU_STACK_MINIMUM_SIZE          (1536)
541
542/*
543 *  CPU's worst alignment requirement for data types on a byte boundary.  This
544 *  alignment does not take into account the requirements for the stack.
545 *
546 *  H8300 Specific Information:
547 *
548 *  XXX
549 */
550
551#define CPU_ALIGNMENT              8
552
553/*
554 *  This number corresponds to the byte alignment requirement for the
555 *  heap handler.  This alignment requirement may be stricter than that
556 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
557 *  common for the heap to follow the same alignment requirement as
558 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
559 *  then this should be set to CPU_ALIGNMENT.
560 *
561 *  NOTE:  This does not have to be a power of 2.  It does have to
562 *         be greater or equal to than CPU_ALIGNMENT.
563 *
564 *  H8300 Specific Information:
565 *
566 *  XXX
567 */
568
569#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
570
571/*
572 *  This number corresponds to the byte alignment requirement for memory
573 *  buffers allocated by the partition manager.  This alignment requirement
574 *  may be stricter than that for the data types alignment specified by
575 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
576 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
577 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
578 *
579 *  NOTE:  This does not have to be a power of 2.  It does have to
580 *         be greater or equal to than CPU_ALIGNMENT.
581 *
582 *  H8300 Specific Information:
583 *
584 *  XXX
585 */
586
587#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
588
589/*
590 *  This number corresponds to the byte alignment requirement for the
591 *  stack.  This alignment requirement may be stricter than that for the
592 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
593 *  is strict enough for the stack, then this should be set to 0.
594 *
595 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
596 *
597 *  H8300 Specific Information:
598 *
599 *  XXX
600 */
601
602#define CPU_STACK_ALIGNMENT        2
603
604/* ISR handler macros */
605
606/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
607   Note requires ISR_Level be unsigned16 or assembler croaks.
608*/
609
610#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 )
611
612
613/*
614 *  Disable all interrupts for an RTEMS critical section.  The previous
615 *  level is returned in _level.
616 */
617
618#define _CPU_ISR_Disable( _isr_cookie ) \
619  do { \
620    asm volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" :  : "r" (_isr_cookie) ); \
621  } while (0)
622
623
624/*
625 *  Enable interrupts to the previois level (returned by _CPU_ISR_Disable).
626 *  This indicates the end of an RTEMS critical section.  The parameter
627 *  _level is not modified.
628 */
629
630
631#define _CPU_ISR_Enable( _isr_cookie )  \
632  do { \
633    asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" :  : "r" (_isr_cookie) ); \
634  } while (0)
635
636
637/*
638 *  This temporarily restores the interrupt to _level before immediately
639 *  disabling them again.  This is used to divide long RTEMS critical
640 *  sections into two or more parts.  The parameter _level is not
641 * modified.
642 */
643
644
645#define _CPU_ISR_Flash( _isr_cookie ) \
646  do { \
647    asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" :  : "r" (_isr_cookie) ); \
648  } while (0)
649
650/* end of ISR handler macros */
651
652#else
653
654/*
655 *  Disable all interrupts for an RTEMS critical section.  The previous
656 *  level is returned in _level.
657 *
658 *  H8300 Specific Information:
659 *
660 *  XXX 
661 */
662
663#if defined(__H8300__)
664#define _CPU_ISR_Disable( _isr_cookie )
665    asm volatile( "orc #0x80,ccr " );
666#else
667#define _CPU_ISR_Disable( _isr_cookie ) \
668  do { \
669    unsigned char __ccr; \
670    asm volatile( "stc ccr, %0 ; orc #0x80,ccr " \
671             : "=m" (__ccr) : "0" (__ccr) ); \
672    (_isr_cookie) = __ccr; \
673  } while (0)
674#endif
675
676
677/*
678 *  Enable interrupts to the previois level (returned by _CPU_ISR_Disable).
679 *  This indicates the end of an RTEMS critical section.  The parameter
680 *  _level is not modified.
681 *
682 *  H8300 Specific Information:
683 *
684 *  XXX
685 */
686
687#if defined(__H8300__)
688#define _CPU_ISR_Enable( _isr_cookie )  \
689   asm(" andc #0x7f,ccr \n")
690#else
691#define _CPU_ISR_Enable( _isr_cookie )  \
692  do { \
693    unsigned char __ccr = (unsigned char) (_isr_cookie); \
694    asm volatile( "ldc %0, ccr" :  : "m" (__ccr) ); \
695  } while (0)
696#endif
697
698/*
699 *  This temporarily restores the interrupt to _level before immediately
700 *  disabling them again.  This is used to divide long RTEMS critical
701 *  sections into two or more parts.  The parameter _level is not
702 *  modified.
703 *
704 *  H8300 Specific Information:
705 *
706 *  XXX
707 */
708
709#if defined(__H8300__)
710#define _CPU_ISR_Enable( _isr_cookie )  \
711   asm( "andc #0x7f,ccr \n orc #0x80,ccr\n" )
712#else
713#define _CPU_ISR_Flash( _isr_cookie ) \
714  do { \
715    unsigned char __ccr = (unsigned char) (_isr_cookie); \
716    asm volatile( "ldc %0, ccr ; orc #0x80,ccr " :  : "m" (__ccr) ); \
717  } while (0)
718#endif
719
720#endif /* end of old gcc */
721
722
723/*
724 *  Map interrupt level in task mode onto the hardware that the CPU
725 *  actually provides.  Currently, interrupt levels which do not
726 *  map onto the CPU in a generic fashion are undefined.  Someday,
727 *  it would be nice if these were "mapped" by the application
728 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
729 *  8 - 255 would be available for bsp/application specific meaning.
730 *  This could be used to manage a programmable interrupt controller
731 *  via the rtems_task_mode directive.
732 *
733 *  H8300 Specific Information:
734 *
735 *  XXX
736 */
737
738#define _CPU_ISR_Set_level( _new_level ) \
739  { \
740    if ( _new_level ) asm volatile ( "orc #0x80,ccr\n" ); \
741    else              asm volatile ( "andc #0x7f,ccr\n" ); \
742  }
743
744unsigned32 _CPU_ISR_Get_level( void );
745
746/* end of ISR handler macros */
747
748/* Context handler macros */
749
750/*
751 *  Initialize the context to a state suitable for starting a
752 *  task after a context restore operation.  Generally, this
753 *  involves:
754 *
755 *     - setting a starting address
756 *     - preparing the stack
757 *     - preparing the stack and frame pointers
758 *     - setting the proper interrupt level in the context
759 *     - initializing the floating point context
760 *
761 *  This routine generally does not set any unnecessary register
762 *  in the context.  The state of the "general data" registers is
763 *  undefined at task start time.
764 *
765 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
766 *        point thread.  This is typically only used on CPUs where the
767 *        FPU may be easily disabled by software such as on the SPARC
768 *        where the PSR contains an enable FPU bit.
769 *
770 *  H8300 Specific Information:
771 *
772 *  XXX
773 */
774
775
776#define CPU_CCR_INTERRUPTS_ON  0x80
777#define CPU_CCR_INTERRUPTS_OFF 0x00
778
779#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
780                                   _isr, _entry_point, _is_fp ) \
781  /* Locate Me */ \
782  do { \
783    unsigned32 _stack; \
784    \
785    if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \
786    else          (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \
787    \
788    _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \
789    *((proc_ptr *)(_stack)) = (_entry_point); \
790     (_the_context)->er7     = (void *) _stack; \
791     (_the_context)->er6     = (void *) _stack; \
792     (_the_context)->er5     = 0; \
793     (_the_context)->er4     = 1; \
794     (_the_context)->er3     = 2; \
795  } while (0)
796
797
798/*
799 *  This routine is responsible for somehow restarting the currently
800 *  executing task.  If you are lucky, then all that is necessary
801 *  is restoring the context.  Otherwise, there will need to be
802 *  a special assembly routine which does something special in this
803 *  case.  Context_Restore should work most of the time.  It will
804 *  not work if restarting self conflicts with the stack frame
805 *  assumptions of restoring a context.
806 *
807 *  H8300 Specific Information:
808 *
809 *  XXX
810 */
811
812#define _CPU_Context_Restart_self( _the_context ) \
813   _CPU_Context_restore( (_the_context) );
814
815/*
816 *  The purpose of this macro is to allow the initial pointer into
817 *  a floating point context area (used to save the floating point
818 *  context) to be at an arbitrary place in the floating point
819 *  context area.
820 *
821 *  This is necessary because some FP units are designed to have
822 *  their context saved as a stack which grows into lower addresses.
823 *  Other FP units can be saved by simply moving registers into offsets
824 *  from the base of the context area.  Finally some FP units provide
825 *  a "dump context" instruction which could fill in from high to low
826 *  or low to high based on the whim of the CPU designers.
827 *
828 *  H8300 Specific Information:
829 *
830 *  XXX
831 */
832
833#define _CPU_Context_Fp_start( _base, _offset ) \
834   ( (void *) (_base) + (_offset) )
835
836/*
837 *  This routine initializes the FP context area passed to it to.
838 *  There are a few standard ways in which to initialize the
839 *  floating point context.  The code included for this macro assumes
840 *  that this is a CPU in which a "initial" FP context was saved into
841 *  _CPU_Null_fp_context and it simply copies it to the destination
842 *  context passed to it.
843 *
844 *  Other models include (1) not doing anything, and (2) putting
845 *  a "null FP status word" in the correct place in the FP context.
846 *
847 *  H8300 Specific Information:
848 *
849 *  XXX
850 */
851
852#define _CPU_Context_Initialize_fp( _destination ) \
853  { \
854   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
855  }
856
857/* end of Context handler macros */
858
859/* Fatal Error manager macros */
860
861/*
862 *  This routine copies _error into a known place -- typically a stack
863 *  location or a register, optionally disables interrupts, and
864 *  halts/stops the CPU.
865 *
866 *  H8300 Specific Information:
867 *
868 *  XXX
869 */
870
871#define _CPU_Fatal_halt( _error ) \
872        printk("Fatal Error %d Halted\n",_error); \
873        for(;;)
874 
875
876/* end of Fatal Error manager macros */
877
878/* Bitfield handler macros */
879
880/*
881 *  This routine sets _output to the bit number of the first bit
882 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
883 *  This type may be either 16 or 32 bits wide although only the 16
884 *  least significant bits will be used.
885 *
886 *  There are a number of variables in using a "find first bit" type
887 *  instruction.
888 *
889 *    (1) What happens when run on a value of zero?
890 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
891 *    (3) The numbering may be zero or one based.
892 *    (4) The "find first bit" instruction may search from MSB or LSB.
893 *
894 *  RTEMS guarantees that (1) will never happen so it is not a concern.
895 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
896 *  _CPU_Priority_bits_index().  These three form a set of routines
897 *  which must logically operate together.  Bits in the _value are
898 *  set and cleared based on masks built by _CPU_Priority_mask().
899 *  The basic major and minor values calculated by _Priority_Major()
900 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
901 *  to properly range between the values returned by the "find first bit"
902 *  instruction.  This makes it possible for _Priority_Get_highest() to
903 *  calculate the major and directly index into the minor table.
904 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
905 *  is the first bit found.
906 *
907 *  This entire "find first bit" and mapping process depends heavily
908 *  on the manner in which a priority is broken into a major and minor
909 *  components with the major being the 4 MSB of a priority and minor
910 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
911 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
912 *  to the lowest priority.
913 *
914 *  If your CPU does not have a "find first bit" instruction, then
915 *  there are ways to make do without it.  Here are a handful of ways
916 *  to implement this in software:
917 *
918 *    - a series of 16 bit test instructions
919 *    - a "binary search using if's"
920 *    - _number = 0
921 *      if _value > 0x00ff
922 *        _value >>=8
923 *        _number = 8;
924 *
925 *      if _value > 0x0000f
926 *        _value >=8
927 *        _number += 4
928 *
929 *      _number += bit_set_table[ _value ]
930 *
931 *    where bit_set_table[ 16 ] has values which indicate the first
932 *      bit set
933 *
934 *  H8300 Specific Information:
935 *
936 *  XXX
937 */
938
939#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
940#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
941
942#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
943
944#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
945  { \
946    (_output) = 0;   /* do something to prevent warnings */ \
947  }
948
949#endif
950
951/* end of Bitfield handler macros */
952
953/*
954 *  This routine builds the mask which corresponds to the bit fields
955 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
956 *  for that routine.
957 *
958 *  H8300 Specific Information:
959 *
960 *  XXX
961 */
962
963#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
964
965#define _CPU_Priority_Mask( _bit_number ) \
966  ( 1 << (_bit_number) )
967
968#endif
969
970/*
971 *  This routine translates the bit numbers returned by
972 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
973 *  a major or minor component of a priority.  See the discussion
974 *  for that routine.
975 *
976 *  H8300 Specific Information:
977 *
978 *  XXX
979 */
980
981#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
982
983#define _CPU_Priority_bits_index( _priority ) \
984  (_priority)
985
986#endif
987
988/* end of Priority handler macros */
989
990/* functions */
991
992/*
993 *  _CPU_Initialize
994 *
995 *  This routine performs CPU dependent initialization.
996 *
997 *  H8300 Specific Information:
998 *
999 *  XXX
1000 */
1001
1002void _CPU_Initialize(
1003  rtems_cpu_table  *cpu_table,
1004  void      (*thread_dispatch)
1005);
1006
1007/*
1008 *  _CPU_ISR_install_raw_handler
1009 *
1010 *  This routine installs a "raw" interrupt handler directly into the
1011 *  processor's vector table.
1012 *
1013 *  H8300 Specific Information:
1014 *
1015 *  XXX
1016 */
1017 
1018void _CPU_ISR_install_raw_handler(
1019  unsigned32  vector,
1020  proc_ptr    new_handler,
1021  proc_ptr   *old_handler
1022);
1023
1024/*
1025 *  _CPU_ISR_install_vector
1026 *
1027 *  This routine installs an interrupt vector.
1028 *
1029 *  H8300 Specific Information:
1030 *
1031 *  XXX
1032 */
1033
1034void _CPU_ISR_install_vector(
1035  unsigned32  vector,
1036  proc_ptr    new_handler,
1037  proc_ptr   *old_handler
1038);
1039
1040/*
1041 *  _CPU_Install_interrupt_stack
1042 *
1043 *  This routine installs the hardware interrupt stack pointer.
1044 *
1045 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1046 *         is TRUE.
1047 *
1048 *  H8300 Specific Information:
1049 *
1050 *  XXX
1051 */
1052
1053void _CPU_Install_interrupt_stack( void );
1054
1055/*
1056 *  _CPU_Internal_threads_Idle_thread_body
1057 *
1058 *  This routine is the CPU dependent IDLE thread body.
1059 *
1060 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1061 *         is TRUE.
1062 *
1063 *  H8300 Specific Information:
1064 *
1065 *  XXX
1066 */
1067
1068void _CPU_Thread_Idle_body( void );
1069
1070/*
1071 *  _CPU_Context_switch
1072 *
1073 *  This routine switches from the run context to the heir context.
1074 *
1075 *  H8300 Specific Information:
1076 *
1077 *  XXX
1078 */
1079
1080void _CPU_Context_switch(
1081  Context_Control  *run,
1082  Context_Control  *heir
1083);
1084
1085/*
1086 *  _CPU_Context_restore
1087 *
1088 *  This routine is generallu used only to restart self in an
1089 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1090 *
1091 *  NOTE: May be unnecessary to reload some registers.
1092 *
1093 *  H8300 Specific Information:
1094 *
1095 *  XXX
1096 */
1097
1098void _CPU_Context_restore(
1099  Context_Control *new_context
1100);
1101
1102/*
1103 *  _CPU_Context_save_fp
1104 *
1105 *  This routine saves the floating point context passed to it.
1106 *
1107 *  H8300 Specific Information:
1108 *
1109 *  XXX
1110 */
1111
1112void _CPU_Context_save_fp(
1113  void **fp_context_ptr
1114);
1115
1116/*
1117 *  _CPU_Context_restore_fp
1118 *
1119 *  This routine restores the floating point context passed to it.
1120 *
1121 *  H8300 Specific Information:
1122 *
1123 *  XXX
1124 */
1125
1126void _CPU_Context_restore_fp(
1127  void **fp_context_ptr
1128);
1129
1130/*  The following routine swaps the endian format of an unsigned int.
1131 *  It must be static because it is referenced indirectly.
1132 *
1133 *  This version will work on any processor, but if there is a better
1134 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1135 *
1136 *     swap least significant two bytes with 16-bit rotate
1137 *     swap upper and lower 16-bits
1138 *     swap most significant two bytes with 16-bit rotate
1139 *
1140 *  Some CPUs have special instructions which swap a 32-bit quantity in
1141 *  a single instruction (e.g. i486).  It is probably best to avoid
1142 *  an "endian swapping control bit" in the CPU.  One good reason is
1143 *  that interrupts would probably have to be disabled to insure that
1144 *  an interrupt does not try to access the same "chunk" with the wrong
1145 *  endian.  Another good reason is that on some CPUs, the endian bit
1146 *  endianness for ALL fetches -- both code and data -- so the code
1147 *  will be fetched incorrectly.
1148 *
1149 *  H8300 Specific Information:
1150 *
1151 *  XXX
1152 */
1153 
1154static inline unsigned int CPU_swap_u32(
1155  unsigned int value
1156)
1157{
1158  unsigned32 byte1, byte2, byte3, byte4, swapped;
1159 
1160  byte4 = (value >> 24) & 0xff;
1161  byte3 = (value >> 16) & 0xff;
1162  byte2 = (value >> 8)  & 0xff;
1163  byte1 =  value        & 0xff;
1164 
1165  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1166  return( swapped );
1167}
1168
1169#ifdef __cplusplus
1170}
1171#endif
1172
1173#endif
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