1 | /* |
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2 | * Hitachi H8 Score CPU functions |
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3 | * Copyright Comnet Technologies Ltd 1999 |
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4 | * |
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5 | * Based on example code and other ports with this copyright: |
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6 | * |
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7 | * COPYRIGHT (c) 1989-1999. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.OARcorp.com/rtems/license.html. |
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13 | * |
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14 | * $Id$ |
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15 | */ |
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16 | |
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17 | |
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18 | ;.equ RUNCONTEXT_ARG, er0 |
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19 | ;.equ HEIRCONTEXT_ARG, er1 |
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20 | |
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21 | /* |
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22 | * Make sure we tell the assembler what type of CPU model we are |
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23 | * being compiled for. |
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24 | */ |
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25 | |
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26 | #if defined(__H8300H__) |
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27 | .h8300h |
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28 | #endif |
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29 | #if defined(__H8300S__) |
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30 | .h8300s |
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31 | #endif |
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32 | .text |
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33 | |
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34 | .text |
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35 | /* |
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36 | GCC Compiled with optimisations and Wimplicit decs to ensure |
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37 | that stack from doesn't change |
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38 | |
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39 | Supposedly R2 and R3 do not need to be saved but who knows |
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40 | |
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41 | Arg1 = er0 (not on stack) |
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42 | Arg2 = er1 (not on stack) |
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43 | */ |
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44 | |
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45 | .align 2 |
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46 | |
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47 | .global __CPU_Context_switch |
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48 | |
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49 | __CPU_Context_switch: |
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50 | /* Save Context */ |
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51 | stc.w ccr,@(0:16,er0) |
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52 | mov.l er7,@(2:16,er0) |
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53 | mov.l er6,@(6:16,er0) |
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54 | mov.l er5,@(10:16,er0) |
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55 | mov.l er4,@(14:16,er0) |
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56 | mov.l er3,@(18:16,er0) |
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57 | mov.l er2,@(22:16,er0) |
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58 | |
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59 | /* Install New context */ |
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60 | |
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61 | restore: |
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62 | mov.l @(22:16,er1),er2 |
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63 | mov.l @(18:16,er1),er3 |
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64 | mov.l @(14:16,er1),er4 |
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65 | mov.l @(10:16,er1),er5 |
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66 | mov.l @(6:16,er1),er6 |
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67 | mov.l @(2:16,er1),er7 |
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68 | ldc.w @(0:16,er1),ccr |
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69 | |
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70 | rts |
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71 | |
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72 | .align 2 |
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73 | |
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74 | .global __CPU_Context_restore |
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75 | |
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76 | __CPU_Context_restore: |
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77 | |
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78 | Mov.l er0,er1 |
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79 | jmp @restore:24 |
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80 | |
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81 | |
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82 | |
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83 | /* |
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84 | VHandler for Vectored Interrupts |
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85 | |
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86 | All IRQ's are vectored to routine _ISR_#vector_number |
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87 | This routine stacks er0 and loads er0 with vector number |
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88 | before transferring to here |
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89 | |
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90 | */ |
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91 | .align 2 |
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92 | .global __ISR_Handler |
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93 | .extern __ISR_Nest_level |
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94 | .extern __Vector_table |
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95 | .extern __Context_switch_necessary |
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96 | |
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97 | |
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98 | __ISR_Handler: |
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99 | mov.l er1,@-er7 |
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100 | mov.l er2,@-er7 |
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101 | mov.l er3,@-er7 |
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102 | mov.l er4,@-er7 |
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103 | mov.l er5,@-er7 |
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104 | mov.l er6,@-er7 |
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105 | |
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106 | /* Set IRQ Stack */ |
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107 | orc #0xc0,ccr |
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108 | mov.l er7,er6 ; save stack pointer |
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109 | mov.l @__ISR_Nest_level,er1 |
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110 | bne nested |
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111 | mov.l @__CPU_Interrupt_stack_high,er7 |
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112 | |
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113 | nested: |
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114 | mov.l er6,@-er7 ; save sp so pop regardless of nest level |
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115 | |
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116 | ;; Inc system counters |
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117 | mov.l @__ISR_Nest_level,er1 |
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118 | inc.l #1,er1 |
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119 | mov.l er1,@__ISR_Nest_level |
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120 | mov.l @__Thread_Dispatch_disable_level,er1 |
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121 | inc.l #1,er1 |
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122 | mov.l er1,@__Thread_Dispatch_disable_level |
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123 | |
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124 | /* Vector to ISR */ |
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125 | |
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126 | mov.l #__ISR_Vector_table,er1 |
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127 | mov er0,er2 ; copy vector |
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128 | shll.l er2 |
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129 | shll.l er2 ; vector = vector * 4 (sizeof(int)) |
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130 | add.l er2,er1 |
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131 | mov.l @er1,er1 |
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132 | jsr @er1 ; er0 = arg1 =vector |
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133 | |
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134 | orc #0xc0,ccr |
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135 | mov.l @__ISR_Nest_level,er1 |
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136 | dec.l #1,er1 |
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137 | mov.l er1,@__ISR_Nest_level |
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138 | mov.l @__Thread_Dispatch_disable_level,er1 |
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139 | dec.l #1,er1 |
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140 | mov.l er1,@__Thread_Dispatch_disable_level |
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141 | bne exit |
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142 | |
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143 | mov.l @__Context_Switch_necessary,er1 |
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144 | bne bframe ; If yes then dispatch next task |
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145 | |
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146 | mov.l @__ISR_Signals_to_thread_executing,er1 |
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147 | beq exit ; If no signals waiting |
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148 | |
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149 | /* Context switch here through ISR_Dispatch */ |
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150 | |
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151 | bframe: |
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152 | orc #0xc0,ccr |
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153 | /* Pop Stack */ |
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154 | mov @er7+,er6 |
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155 | mov er6,er7 |
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156 | mov.l #0,er2 |
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157 | mov.l er2,@__ISR_Signals_to_thread_executing |
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158 | |
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159 | /* Set up IRQ stack frame and dispatch to _ISR_Dispatch */ |
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160 | |
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161 | mov.l #0xc0000000,er2 /* Disable IRQ */ |
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162 | or.l #_ISR_Dispatch,er2 |
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163 | mov.l er2,@-er7 |
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164 | rte |
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165 | |
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166 | /* Inner IRQ Return, pop flags and return */ |
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167 | exit: |
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168 | /* Pop Stack */ |
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169 | orc #0x80,ccr |
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170 | mov @er7+,er6 |
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171 | mov er6,er7 |
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172 | mov @er7+,er6 |
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173 | mov @er7+,er5 |
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174 | mov @er7+,er4 |
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175 | mov @er7+,er3 |
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176 | mov @er7+,er2 |
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177 | mov @er7+,er1 |
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178 | mov @er7+,er0 |
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179 | rte |
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180 | |
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181 | /* |
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182 | Called from ISR_Handler as a way of ending IRQ |
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183 | but allowing dispatch to another task. |
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184 | Must use RTE as CCR is still on stack but IRQ has been serviced. |
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185 | CCR and PC occupy same word so rte can be used. |
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186 | now using task stack |
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187 | */ |
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188 | |
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189 | .align 2 |
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190 | .global _ISR_Dispatch |
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191 | |
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192 | _ISR_Dispatch: |
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193 | |
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194 | Jsr @__Thread_Dispatch |
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195 | mov @er7+,er6 |
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196 | mov @er7+,er5 |
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197 | mov @er7+,er4 |
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198 | mov @er7+,er3 |
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199 | mov @er7+,er2 |
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200 | mov @er7+,er1 |
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201 | mov @er7+,er0 |
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202 | rte |
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203 | |
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204 | |
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205 | .align 2 |
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206 | .global __CPU_Context_save_fp |
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207 | |
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208 | __CPU_Context_save_fp: |
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209 | rts |
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210 | |
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211 | |
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212 | .align 2 |
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213 | .global __CPU_Context_restore_fp |
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214 | |
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215 | __CPU_Context_restore_fp: |
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216 | rts |
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217 | |
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