source: rtems/c/src/exec/score/cpu/h8300/cpu_asm.S @ fb31e1a2

4.104.114.84.95
Last change on this file since fb31e1a2 was fb31e1a2, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 17, 2000 at 1:01:44 PM

Update from Philip Quaife <rtemsdev@…> that was hand-merged.
This update addresses the following:

+ the ISR enable/disable/flash macros now work with old gcc versions.
+ the UI CCR bits are now masked since other example code did so
+ _ISR_Dispatch disables interrupts during call setup

Together these removed the instabilities he was seeing.

  • Property mode set to 100644
File size: 4.0 KB
Line 
1/*
2 * Hitachi H8 Score CPU functions
3 *   Copyright Comnet Technologies Ltd 1999
4 *
5 *  Based on example code and other ports with this copyright:
6 * 
7 *  COPYRIGHT (c) 1989-1999.
8 *  On-Line Applications Research Corporation (OAR).
9 * 
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 * 
14 *  $Id$
15 */
16
17
18;.equ   RUNCONTEXT_ARG,  er0
19;.equ   HEIRCONTEXT_ARG, er1
20       
21/*     
22 *  Make sure we tell the assembler what type of CPU model we are
23 *  being compiled for.
24 */
25
26#if defined(__H8300H__)
27        .h8300h
28#endif
29#if defined(__H8300S__)
30        .h8300s
31#endif
32        .text
33
34        .text
35/*
36        GCC Compiled with optimisations and Wimplicit decs to ensure
37    that stack from doesn't change
38       
39        Supposedly R2 and R3 do not need to be saved but who knows
40       
41        Arg1 = er0      (not on stack)
42        Arg2 = er1      (not on stack)
43*/
44
45        .align 2
46
47        .global __CPU_Context_switch
48
49__CPU_Context_switch:
50        /* Save Context */
51        stc.w   ccr,@(0:16,er0)
52        mov.l   er7,@(2:16,er0)
53        mov.l   er6,@(6:16,er0)
54        mov.l   er5,@(10:16,er0)
55        mov.l   er4,@(14:16,er0)
56        mov.l   er3,@(18:16,er0)
57        mov.l   er2,@(22:16,er0)
58
59        /* Install New context */
60
61restore:
62        mov.l   @(22:16,er1),er2
63        mov.l   @(18:16,er1),er3
64        mov.l   @(14:16,er1),er4
65        mov.l   @(10:16,er1),er5
66        mov.l   @(6:16,er1),er6
67        mov.l   @(2:16,er1),er7
68        ldc.w   @(0:16,er1),ccr
69
70        rts
71
72        .align 2
73
74        .global __CPU_Context_restore
75
76__CPU_Context_restore:
77       
78        Mov.l   er0,er1
79        jmp             @restore:24
80
81
82
83/*
84        VHandler for Vectored Interrupts
85       
86        All IRQ's are vectored to routine _ISR_#vector_number
87        This routine stacks er0 and loads er0 with vector number
88        before transferring to here
89       
90*/
91        .align 2
92        .global __ISR_Handler
93        .extern __ISR_Nest_level
94        .extern __Vector_table
95        .extern __Context_switch_necessary
96
97       
98__ISR_Handler:
99        mov.l   er1,@-er7
100        mov.l   er2,@-er7
101        mov.l   er3,@-er7
102        mov.l   er4,@-er7
103        mov.l   er5,@-er7
104        mov.l   er6,@-er7
105       
106/*  Set IRQ Stack */
107        orc             #0xc0,ccr
108        mov.l   er7,er6         ; save stack pointer
109        mov.l   @__ISR_Nest_level,er1
110        bne             nested
111        mov.l   @__CPU_Interrupt_stack_high,er7
112       
113nested:
114        mov.l   er6,@-er7       ; save sp so pop regardless of nest level
115       
116;; Inc  system counters
117        mov.l   @__ISR_Nest_level,er1
118        inc.l   #1,er1
119        mov.l   er1,@__ISR_Nest_level
120        mov.l   @__Thread_Dispatch_disable_level,er1
121        inc.l   #1,er1
122        mov.l   er1,@__Thread_Dispatch_disable_level
123       
124/* Vector to ISR */
125
126        mov.l   #__ISR_Vector_table,er1
127        mov             er0,er2 ; copy vector
128        shll.l  er2
129        shll.l  er2             ; vector = vector * 4 (sizeof(int))
130        add.l   er2,er1
131    mov.l       @er1,er1
132        jsr             @er1    ; er0 = arg1 =vector
133       
134        orc             #0xc0,ccr
135        mov.l   @__ISR_Nest_level,er1
136        dec.l   #1,er1
137        mov.l   er1,@__ISR_Nest_level
138        mov.l   @__Thread_Dispatch_disable_level,er1
139        dec.l   #1,er1
140        mov.l   er1,@__Thread_Dispatch_disable_level
141        bne             exit
142       
143        mov.l   @__Context_Switch_necessary,er1
144        bne             bframe          ; If yes then dispatch next task
145       
146        mov.l   @__ISR_Signals_to_thread_executing,er1
147        beq             exit            ; If no signals waiting
148
149        /* Context switch here through ISR_Dispatch */
150       
151bframe:
152        orc             #0xc0,ccr
153/*      Pop Stack       */
154        mov             @er7+,er6
155        mov             er6,er7
156        mov.l   #0,er2
157        mov.l   er2,@__ISR_Signals_to_thread_executing
158
159        /* Set up IRQ stack frame and dispatch to _ISR_Dispatch */
160       
161        mov.l   #0xc0000000,er2         /* Disable IRQ */
162        or.l    #_ISR_Dispatch,er2
163        mov.l   er2,@-er7
164        rte
165
166/*      Inner IRQ Return, pop flags and return */
167exit:
168/*      Pop Stack       */
169        orc             #0x80,ccr
170        mov             @er7+,er6
171        mov             er6,er7
172        mov             @er7+,er6
173        mov             @er7+,er5
174        mov             @er7+,er4
175        mov             @er7+,er3
176        mov             @er7+,er2
177        mov             @er7+,er1
178        mov             @er7+,er0
179        rte
180       
181/*
182        Called from ISR_Handler as a way of ending IRQ
183        but allowing dispatch to another task.
184        Must use RTE as CCR is still on stack but IRQ has been serviced.       
185        CCR and PC occupy same word so rte can be used.
186        now using task stack
187*/
188
189        .align 2
190        .global _ISR_Dispatch
191
192_ISR_Dispatch:
193       
194        Jsr             @__Thread_Dispatch
195        mov             @er7+,er6
196        mov             @er7+,er5
197        mov             @er7+,er4
198        mov             @er7+,er3
199        mov             @er7+,er2
200        mov             @er7+,er1
201        mov             @er7+,er0
202        rte
203       
204
205        .align 2
206        .global __CPU_Context_save_fp
207
208__CPU_Context_save_fp:
209        rts
210
211
212        .align 2
213        .global __CPU_Context_restore_fp
214
215__CPU_Context_restore_fp:
216        rts
217
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