source: rtems/c/src/exec/score/cpu/h8300/cpu_asm.S @ 5532553

4.104.114.84.95
Last change on this file since 5532553 was 5532553, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 29, 2000 at 11:00:48 PM

This is the initial addition of the port of RTEMS to the
Hitachi H8 family. This port was done by Philip Quaife
<philip@…> of Q Solutions and sponsored by
Comnet Technologies Ltd. The port was done based on RTEMS 3.5.1
to a Hitach H8300H. The port was updated to RTEMS 4.5 style
Makefiles/configure by Joel Sherrill <joel@…>.
While doing this Joel added support for the h8300-rtems to
binutils, gcc, newlib, and gdb.

NOTE: Philip submitted a BSP for a Hitachi evaluation board
which is being merged as a separate entity.

  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*
2 * Hitachi H8 Score CPU functions
3 *   Copyright Comnet Technologies Ltd 1999
4 *
5 *  Based on example code and other ports with this copyright:
6 * 
7 *  COPYRIGHT (c) 1989-1999.
8 *  On-Line Applications Research Corporation (OAR).
9 * 
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 * 
14 *  $Id$
15 */
16
17
18;.equ   RUNCONTEXT_ARG,  er0
19;.equ   HEIRCONTEXT_ARG, er1
20       
21
22/*
23 *  Make sure we tell the assembler what type of CPU model we are
24 *  being compiled for.
25 */
26
27#if defined(__H8300H__)
28        .h8300h
29#endif
30#if defined(__H8300S__)
31        .h8300s
32#endif
33        .text
34
35/*
36        GCC Compiled with optimisations and Wimplicit decs to ensure
37    that stack from doesn't change
38       
39        Supposedly R2 and R3 do not need to be saved but who knows
40       
41        Arg1 = er0      (not on stack)
42        Arg2 = er1      (not on stack)
43*/
44
45        .align 2
46        .global __CPU_Context_switch
47__CPU_Context_switch:
48#if defined(__H8300H__) || defined(__H8300S__)
49        /* Save Context */
50        stc     ccr,@(0:16,er0)
51        mov.l   er7,@(2:16,er0)
52        mov.l   er6,@(6:16,er0)
53        mov.l   er5,@(10:16,er0)
54        mov.l   er4,@(14:16,er0)
55        mov.l   er3,@(18:16,er0)
56        mov.l   er2,@(22:16,er0)
57
58        /* Install New context */
59
60restore:
61        mov.l   @(22:16,er1),er2
62        mov.l   @(18:16,er1),er3
63        mov.l   @(14:16,er1),er4
64        mov.l   @(10:16,er1),er5
65        mov.l   @(6:16,er1),er6
66        mov.l   @(2:16,er1),er7
67        ldc     @(0:16,er1),ccr
68#endif
69        rts
70
71        .align 2
72        .global __CPU_Context_restore
73__CPU_Context_restore:
74#if defined(__H8300H__) || defined(__H8300S__)
75        mov.l   er0,er1
76        jmp     @restore:24
77#else
78        rts
79#endif
80
81
82
83/*
84        VHandler for Vectored Interrupts
85       
86        All IRQ's are vectored to routine _ISR_#vector_number
87        This routine stacks er0 and loads er0 with vector number
88        before transferring to here
89       
90*/
91        .align 2
92        .global __ISR_Handler
93        .extern __ISR_Nest_level
94        .extern __Vector_table
95        .extern __Context_switch_necessary
96
97       
98__ISR_Handler:
99#if defined(__H8300H__) || defined(__H8300S__)
100        mov.l   er1,@-er7
101        mov.l   er2,@-er7
102        mov.l   er3,@-er7
103        mov.l   er4,@-er7
104        mov.l   er5,@-er7
105        mov.l   er6,@-er7
106       
107/*  Set IRQ Stack */
108        orc             #0x80,ccr
109        mov.l   er7,er6         ; save stack pointer
110        mov.l   @__ISR_Nest_level,er1
111        bne             nested
112        mov.l   @__CPU_Interrupt_stack_high,er7
113       
114nested:
115        mov.l   er6,@-er7       ; save sp so pop regardless of nest level
116       
117;; Inc  system counters
118        mov.l   @__ISR_Nest_level,er1
119        inc.l   #1,er1
120        mov.l   er1,@__ISR_Nest_level
121        mov.l   @__Thread_Dispatch_disable_level,er1
122        inc.l   #1,er1
123        mov.l   er1,@__Thread_Dispatch_disable_level
124       
125/* Vector to ISR */
126
127        mov.l   #__ISR_Vector_table,er1
128        mov             er0,er2 ; copy vector
129        shll.l  er2
130        shll.l  er2             ; vector = vector * 4 (sizeof(int))
131        add.l   er2,er1
132    mov.l       @er1,er1
133        jsr             @er1    ; er0 = arg1 =vector
134       
135        orc             #0x80,ccr
136        mov.l   @__ISR_Nest_level,er1
137        dec.l   #1,er1
138        mov.l   er1,@__ISR_Nest_level
139        mov.l   @__Thread_Dispatch_disable_level,er1
140        dec.l   #1,er1
141        mov.l   er1,@__Thread_Dispatch_disable_level
142        bne             exit
143       
144        mov.l   @__Context_Switch_necessary,er1
145        bne             bframe          ; If yes then dispatch next task
146       
147        mov.l   @__ISR_Signals_to_thread_executing,er1
148        beq             exit            ; If no signals waiting
149
150        /* Context switch here through ISR_Dispatch */
151       
152bframe:
153        orc             #0x80,ccr
154/*      Pop Stack       */
155        mov             @er7+,er6
156        mov             er6,er7
157        mov.l   #0,er2
158        mov.l   er2,@__ISR_Signals_to_thread_executing
159
160        /* Set up IRQ stack frame and dispatch to _ISR_Dispatch */
161       
162        stc             ccr,@er2
163        and.l   #0xff,er2       
164        rotr.l  er2
165        rotr.l  er2
166        rotr.l  er2
167        rotr.l  er2
168        or.l    #_ISR_Dispatch,er2
169        mov.l   er2,@-er7
170        rte
171
172/*      Inner IRQ Return, pop flags and return */
173exit:
174/*      Pop Stack       */
175        orc             #0x80,ccr
176        mov             @er7+,er6
177        mov             er6,er7
178        andc    #0x7f,ccr
179        mov             @er7+,er6
180        mov             @er7+,er5
181        mov             @er7+,er4
182        mov             @er7+,er3
183        mov             @er7+,er2
184        mov             @er7+,er1
185        mov             @er7+,er0
186        andc    #0x7f,ccr
187        rte
188#endif
189       
190/*
191        Called from ISR_Handler as a way of ending IRQ
192        but allowing dispatch to another task.
193        Must use RTE as CCR is still on stack but IRQ has been serviced.       
194        CCR and PC occupy same word so rte can be used.
195*/
196
197        .align 2
198        .global _ISR_Dispatch
199
200_ISR_Dispatch:
201#if defined(__H8300H__) || defined(__H8300S__)
202        jsr             @__Thread_Dispatch
203        mov             @er7+,er6
204        mov             @er7+,er5
205        mov             @er7+,er4
206        mov             @er7+,er3
207        mov             @er7+,er2
208        mov             @er7+,er1
209        mov             @er7+,er0
210        rte
211#endif
212       
213
214        .align 2
215        .global __CPU_Context_save_fp
216
217__CPU_Context_save_fp:
218        rts
219
220
221        .align 2
222        .global __CPU_Context_restore_fp
223
224__CPU_Context_restore_fp:
225        rts
226
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