source: rtems/c/src/exec/score/cpu/c4x/rtems/score/c4x.h @ 8eacefcc

4.104.114.84.95
Last change on this file since 8eacefcc was 8eacefcc, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 29, 2000 at 4:35:45 PM

BSP now compiles and links with CAVSL board information. This includes
linkcmds updated, simio references removed, and switch to libchip for
serial ports from simio.

Added a MEMORY_MAP file to capture information about the various
addresses on this board.

In addition, many of the beta patches are now included.

  • Property mode set to 100644
File size: 8.3 KB
Line 
1/*  c4x.h
2 *
3 *  This file is an example (i.e. "no CPU") of the file which is
4 *  created for each CPU family port of RTEMS.
5 *
6 *
7 *  COPYRIGHT (c) 1989-1999.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id$
15 *
16 */
17
18#ifndef _INCLUDE_C4X_h
19#define _INCLUDE_C4X_h
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25/*
26 *  This file contains the information required to build
27 *  RTEMS for a particular member of the "no cpu"
28 *  family when executing in protected mode.  It does
29 *  this by setting variables to indicate which implementation
30 *  dependent features are present in a particular member
31 *  of the family.
32 */
33 
34#if defined(c30)
35#define CPU_MODEL_NAME  "C30"
36
37#elif defined(c31)
38#define CPU_MODEL_NAME  "C31"
39 
40#elif defined(c32)
41#define CPU_MODEL_NAME  "C32"
42 
43#elif defined(c40)
44#define CPU_MODEL_NAME  "C40"
45 
46#elif defined(c44)
47#define CPU_MODEL_NAME  "C44"
48 
49#else
50 
51#error "Unsupported CPU Model"
52 
53#endif
54
55/*
56 *  Define the name of the CPU family.
57 */
58
59#define CPU_NAME "Texas Instruments C3x/C4x"
60
61/*
62 *  This port is a little unusual in that even though there are "floating
63 *  point registers", the notion of floating point is very inherent to
64 *  applications.  In addition, the calling conventions require that
65 *  only a few extended registers be preserved across subroutine calls.
66 *  The overhead of including these few registers in the basic
67 *  context is small compared to the overhead of managing the notion
68 *  of separate floating point contexts.  So we decided to pretend that
69 *  there is no FPU on the C3x or C4x.
70 */
71
72#define C4X_HAS_FPU  0
73
74/*
75 *  Routines to manipulate the bits in the Status Word (ST).
76 */
77
78#define C4X_ST_C      0x0001
79#define C4X_ST_V      0x0002
80#define C4X_ST_Z      0x0004
81#define C4X_ST_N      0x0008
82#define C4X_ST_UF     0x0010
83#define C4X_ST_LV     0x0020
84#define C4X_ST_LUF    0x0040
85#define C4X_ST_OVM    0x0080
86#define C4X_ST_RM     0x0100
87#define C4X_ST_CF     0x0400
88#define C4X_ST_CE     0x0800
89#define C4X_ST_CC     0x1000
90#define C4X_ST_GIE    0x2000
91
92#ifndef _TMS320C40
93#define C3X_IE_INTERRUPT_MASK_BITS     0xffff
94#define C3x_IE_INTERRUPTS_ALL_ENABLED  0x0000
95#define C3x_IE_INTERRUPTS_ALL_DISABLED 0xffff
96#endif
97
98#ifndef ASM
99
100/*
101 *  A nop macro.
102 */
103
104#define c4x_nop() \
105  __asm__("nop");
106
107/*
108 *  Routines to set and clear individual bits in the ST (status word).
109 *
110 *  cpu_st_bit_clear  - clear bit in ST
111 *  cpu_st_bit_set    - set bit in ST
112 *  cpu_st_get        - obtain entire ST
113 */
114
115#ifdef _TMS320C40
116#define c4x_gie_nop()
117#else
118#define c4x_gie_nop() { c4x_nop(); c4x_nop(); }
119#endif
120
121#define cpu_st_bit_clear(_st_bit) \
122  do { \
123    __asm__("andn %0,st" : : "g" (_st_bit) : "cc"); \
124    c4x_gie_nop(); \
125  } while (0)
126
127#define cpu_st_bit_set(_st_bit) \
128  do { \
129    __asm__("or %0,st" : : "g" (_st_bit) : "cc"); \
130    c4x_gie_nop(); \
131  } while (0)
132
133static inline unsigned int cpu_st_get(void)
134{
135  register unsigned int st_value;
136  __asm__("ldi st, %0" : "=r" (st_value));
137  return st_value;
138}
139
140/*
141 *  Routines to manipulate the Global Interrupt Enable (GIE) bit in
142 *  the Status Word (ST).
143 *
144 *  c4x_global_interrupts_get      - returns current GIE setting
145 *  c4x_global_interrupts_disable  - disables global interrupts
146 *  c4x_global_interrupts_enable   - enables global interrupts
147 *  c4x_global_interrupts_restore  - restores GIE to pre-disable state
148 *  c4x_global_interrupts_flash    - temporarily enable global interrupts
149 */
150
151#define c4x_global_interrupts_get() \
152  (cpu_st_get() & C4X_ST_GIE)
153 
154#define c4x_global_interrupts_disable() \
155  cpu_st_bit_clear(C4X_ST_GIE)
156
157#define c4x_global_interrupts_enable() \
158  cpu_st_bit_set(C4X_ST_GIE)
159
160#define c4x_global_interrupts_restore(_old_level) \
161  cpu_st_bit_set(_old_level)
162
163#define c4x_global_interrupts_flash(_old_level) \
164  do { \
165    cpu_st_bit_set(_old_level); \
166    cpu_st_bit_clear(C4X_ST_GIE); \
167  } while (0)
168
169#ifndef _TMS320C40
170
171/*
172 *  Routines to set and get the IF register
173 *
174 *  c3x_get_if     - obtains IF register
175 *  c3x_set_if     - sets IF register
176 */
177
178static inline unsigned int c3x_get_if(void)
179{
180  register unsigned int _if_value;
181
182  __asm__( "ldi if, %0" : "=r" (_if_value) );
183  return _if_value;
184}
185
186static inline void c3x_set_if(unsigned int _if_value)
187{
188  __asm__( "ldi %0, if" : : "g" (_if_value) : "if", "cc"); 
189}
190
191/*
192 *  Routines to set and get the IE register
193 *
194 *  c3x_get_ie     - obtains IE register
195 *  c3x_set_ie     - sets IE register
196 */
197
198static inline unsigned int c3x_get_ie(void)
199{
200  register unsigned int _ie_value;
201
202  __asm__ volatile ( "ldi ie, %0" : "=r" (_ie_value) );
203  return _ie_value;
204}
205
206static inline void c3x_set_ie(unsigned int _ie_value)
207{
208  __asm__ volatile ( "ldi %0, ie" : : "g" (_ie_value) : "ie", "cc"); 
209}
210
211/*
212 *  Routines to manipulates the mask portion of the IE register.
213 *
214 *  c3x_ie_mask_all     - returns previous IE mask
215 *  c3x_ie_mask_restore - restores previous IE mask
216 *  c3x_ie_mask_flash   - temporarily restores previous IE mask
217 *  c3x_ie_mask_set     - sets a specific set of the IE mask
218 */
219 
220#define c3x_ie_mask_all( _isr_cookie ) \
221  do { \
222    __asm__("ldi  ie,%0\n" \
223            "\tandn 0ffffh, ie" \
224          : "=r" (_isr_cookie): : "ie", "cc" ); \
225  } while (0)
226
227#define c3x_ie_mask_restore( _isr_cookie )  \
228  do { \
229    __asm__("or %0, ie" \
230          : : "g" (_isr_cookie) : "ie", "cc" ); \
231  } while (0)
232
233#define c3x_ie_mask_flash( _isr_cookie ) \
234  do { \
235    __asm__("or %0, ie\n" \
236           "\tandn 0ffffh, ie" \
237          : : "g" (_isr_cookie) : "ie", "cc" ); \
238  } while (0)
239
240#define c3x_ie_mask_set( _new_mask ) \
241  do { unsigned int _ie_mask; \
242    unsigned int _ie_value; \
243    \
244    if ( _new_mask == 0 ) _ie_mask = 0; \
245    else                  _ie_mask = 0xffff; \
246    _ie_value = c3x_get_ie(); \
247    _ie_value &= C4X_IE_INTERRUPT_MASK_BITS; \
248    _ie_value |= _ie_mask; \
249    c3x_set_ie(_ie_value); \
250  } while (0)
251#endif
252/* end of C3x specific interrupt flag routines */
253
254/*
255 *  This is a section of C4x specific interrupt flag management routines.
256 */
257
258#ifdef _TMS320C40
259
260/*
261 *  Routines to set and get the IIF register
262 *
263 *  c4x_get_iif     - obtains IIF register
264 *  c4x_set_iif     - sets IIF register
265 */
266
267static inline unsigned int c4x_get_iif(void)
268{
269  register unsigned int _iif_value;
270
271  __asm__( "ldi iif, %0" : "=r" (_iif_value) );
272  return _iif_value;
273}
274
275static inline void c4x_set_iif(unsigned int _iif_value)
276{
277  __asm__( "ldi %0, iif" : : "g" (_iif_value) : "iif", "cc"); 
278}
279
280/*
281 *  Routines to set and get the IIE register
282 *
283 *  c4x_get_iie     - obtains IIE register
284 *  c4x_set_iie     - sets IIE register
285 */
286
287static inline unsigned int c4x_get_iie(void)
288{
289  register unsigned int _iie_value;
290
291  __asm__( "ldi iie, %0" : "=r" (_iie_value) );
292  return _iie_value;
293}
294
295static inline void c4x_set_iie(unsigned int _iie_value)
296{
297  __asm__( "ldi %0, iie" : : "g" (_iie_value) : "iie", "cc"); 
298}
299
300/*
301 *  Routines to manipulates the mask portion of the IIE register.
302 *
303 *  c4x_ie_mask_all     - returns previous IIE mask
304 *  c4x_ie_mask_restore - restores previous IIE mask
305 *  c4x_ie_mask_flash   - temporarily restores previous IIE mask
306 *  c4x_ie_mask_set     - sets a specific set of the IIE mask
307 */
308
309#if 0
310#warning "C4x IIE masking routines not implemented."
311#define c4x_iie_mask_all( _isr_cookie )
312#define c4x_iie_mask_restore( _isr_cookie )
313#define c4x_iie_mask_flash( _isr_cookie )
314#define c4x_iie_mask_set( _new_mask )
315#endif
316
317#endif
318/* end of C4x specific interrupt flag routines */
319
320/*
321 *  Routines to access the Interrupt Trap Table Pointer
322 *
323 *  c4x_get_ittp    - get ITTP
324 *  c4x_set_ittp    - set ITTP
325 */
326
327static inline void * c4x_get_ittp(void)
328{ 
329  register unsigned int _if_value;
330 
331  __asm__( "ldi if, %0" : "=r" (_if_value) );
332  return (void *)((_if_value & 0xffff0000) >> 8); 
333} 
334
335static inline void c4x_set_ittp(void *_ittp_value)
336{ 
337  unsigned int _if_value;
338  unsigned int _ittp_field;
339
340#ifdef _TMS320C40
341  _if_value = c4x_get_iif();
342#else
343  _if_value = c3x_get_if();
344#endif
345  _if_value &= 0xffff;
346  _ittp_field = (((unsigned int) _ittp_value) >> 8);
347  _if_value |= _ittp_field << 16 ;
348#ifdef _TMS320C40
349  c4x_set_iif( _if_value );
350#else
351  c3x_set_if( _if_value );
352#endif
353} 
354
355#endif /* ifndef ASM */
356
357#ifdef __cplusplus
358}
359#endif
360
361#endif /* ! _INCLUDE_C4X_h */
362/* end of include file */
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