[61ba9763] | 1 | /* c4x.h |
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| 2 | * |
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| 3 | * This file is an example (i.e. "no CPU") of the file which is |
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| 4 | * created for each CPU family port of RTEMS. |
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| 5 | * |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1989-1999. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.OARcorp.com/rtems/license.html. |
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| 13 | * |
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| 14 | * $Id$ |
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| 15 | * |
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| 16 | */ |
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| 17 | |
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| 18 | #ifndef _INCLUDE_C4X_h |
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| 19 | #define _INCLUDE_C4X_h |
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| 20 | |
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| 21 | #ifdef __cplusplus |
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| 22 | extern "C" { |
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| 23 | #endif |
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| 24 | |
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| 25 | /* |
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| 26 | * This file contains the information required to build |
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| 27 | * RTEMS for a particular member of the "no cpu" |
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| 28 | * family when executing in protected mode. It does |
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| 29 | * this by setting variables to indicate which implementation |
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| 30 | * dependent features are present in a particular member |
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| 31 | * of the family. |
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| 32 | */ |
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| 33 | |
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[38e5a9f] | 34 | #if defined(_C30) |
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[61ba9763] | 35 | #define CPU_MODEL_NAME "C30" |
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| 36 | |
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[38e5a9f] | 37 | #elif defined(_C31) |
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[61ba9763] | 38 | #define CPU_MODEL_NAME "C31" |
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| 39 | |
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[38e5a9f] | 40 | #elif defined(_C32) |
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[61ba9763] | 41 | #define CPU_MODEL_NAME "C32" |
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| 42 | |
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[38e5a9f] | 43 | #elif defined(_C33) |
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| 44 | #define CPU_MODEL_NAME "C33" |
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| 45 | |
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| 46 | #elif defined(_C40) |
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[61ba9763] | 47 | #define CPU_MODEL_NAME "C40" |
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| 48 | |
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[38e5a9f] | 49 | #elif defined(_C44) |
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[61ba9763] | 50 | #define CPU_MODEL_NAME "C44" |
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| 51 | |
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| 52 | #else |
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| 53 | |
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| 54 | #error "Unsupported CPU Model" |
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| 55 | |
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| 56 | #endif |
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| 57 | |
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| 58 | /* |
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| 59 | * Define the name of the CPU family. |
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| 60 | */ |
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| 61 | |
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| 62 | #define CPU_NAME "Texas Instruments C3x/C4x" |
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| 63 | |
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| 64 | /* |
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| 65 | * This port is a little unusual in that even though there are "floating |
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| 66 | * point registers", the notion of floating point is very inherent to |
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| 67 | * applications. In addition, the calling conventions require that |
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| 68 | * only a few extended registers be preserved across subroutine calls. |
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| 69 | * The overhead of including these few registers in the basic |
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| 70 | * context is small compared to the overhead of managing the notion |
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| 71 | * of separate floating point contexts. So we decided to pretend that |
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| 72 | * there is no FPU on the C3x or C4x. |
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| 73 | */ |
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| 74 | |
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| 75 | #define C4X_HAS_FPU 0 |
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| 76 | |
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| 77 | /* |
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| 78 | * Routines to manipulate the bits in the Status Word (ST). |
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| 79 | */ |
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| 80 | |
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| 81 | #define C4X_ST_C 0x0001 |
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| 82 | #define C4X_ST_V 0x0002 |
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| 83 | #define C4X_ST_Z 0x0004 |
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| 84 | #define C4X_ST_N 0x0008 |
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| 85 | #define C4X_ST_UF 0x0010 |
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| 86 | #define C4X_ST_LV 0x0020 |
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| 87 | #define C4X_ST_LUF 0x0040 |
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| 88 | #define C4X_ST_OVM 0x0080 |
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| 89 | #define C4X_ST_RM 0x0100 |
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| 90 | #define C4X_ST_CF 0x0400 |
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| 91 | #define C4X_ST_CE 0x0800 |
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| 92 | #define C4X_ST_CC 0x1000 |
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| 93 | #define C4X_ST_GIE 0x2000 |
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| 94 | |
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| 95 | #ifndef _TMS320C40 |
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| 96 | #define C3X_IE_INTERRUPT_MASK_BITS 0xffff |
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| 97 | #define C3x_IE_INTERRUPTS_ALL_ENABLED 0x0000 |
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| 98 | #define C3x_IE_INTERRUPTS_ALL_DISABLED 0xffff |
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| 99 | #endif |
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| 100 | |
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| 101 | #ifndef ASM |
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| 102 | |
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| 103 | /* |
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| 104 | * A nop macro. |
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| 105 | */ |
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| 106 | |
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| 107 | #define c4x_nop() \ |
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| 108 | __asm__("nop"); |
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| 109 | |
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| 110 | /* |
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| 111 | * Routines to set and clear individual bits in the ST (status word). |
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| 112 | * |
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| 113 | * cpu_st_bit_clear - clear bit in ST |
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| 114 | * cpu_st_bit_set - set bit in ST |
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| 115 | * cpu_st_get - obtain entire ST |
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| 116 | */ |
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| 117 | |
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| 118 | #ifdef _TMS320C40 |
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| 119 | #define c4x_gie_nop() |
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| 120 | #else |
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| 121 | #define c4x_gie_nop() { c4x_nop(); c4x_nop(); } |
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| 122 | #endif |
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| 123 | |
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| 124 | #define cpu_st_bit_clear(_st_bit) \ |
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| 125 | do { \ |
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| 126 | __asm__("andn %0,st" : : "g" (_st_bit) : "cc"); \ |
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| 127 | c4x_gie_nop(); \ |
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| 128 | } while (0) |
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| 129 | |
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| 130 | #define cpu_st_bit_set(_st_bit) \ |
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| 131 | do { \ |
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| 132 | __asm__("or %0,st" : : "g" (_st_bit) : "cc"); \ |
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| 133 | c4x_gie_nop(); \ |
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| 134 | } while (0) |
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| 135 | |
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| 136 | static inline unsigned int cpu_st_get(void) |
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| 137 | { |
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| 138 | register unsigned int st_value; |
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| 139 | __asm__("ldi st, %0" : "=r" (st_value)); |
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| 140 | return st_value; |
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| 141 | } |
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| 142 | |
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| 143 | /* |
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| 144 | * Routines to manipulate the Global Interrupt Enable (GIE) bit in |
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| 145 | * the Status Word (ST). |
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| 146 | * |
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| 147 | * c4x_global_interrupts_get - returns current GIE setting |
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| 148 | * c4x_global_interrupts_disable - disables global interrupts |
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| 149 | * c4x_global_interrupts_enable - enables global interrupts |
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| 150 | * c4x_global_interrupts_restore - restores GIE to pre-disable state |
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| 151 | * c4x_global_interrupts_flash - temporarily enable global interrupts |
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| 152 | */ |
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| 153 | |
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| 154 | #define c4x_global_interrupts_get() \ |
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| 155 | (cpu_st_get() & C4X_ST_GIE) |
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| 156 | |
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| 157 | #define c4x_global_interrupts_disable() \ |
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| 158 | cpu_st_bit_clear(C4X_ST_GIE) |
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| 159 | |
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| 160 | #define c4x_global_interrupts_enable() \ |
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| 161 | cpu_st_bit_set(C4X_ST_GIE) |
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| 162 | |
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| 163 | #define c4x_global_interrupts_restore(_old_level) \ |
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| 164 | cpu_st_bit_set(_old_level) |
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| 165 | |
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| 166 | #define c4x_global_interrupts_flash(_old_level) \ |
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| 167 | do { \ |
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| 168 | cpu_st_bit_set(_old_level); \ |
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| 169 | cpu_st_bit_clear(C4X_ST_GIE); \ |
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| 170 | } while (0) |
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| 171 | |
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| 172 | #ifndef _TMS320C40 |
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| 173 | |
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| 174 | /* |
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| 175 | * Routines to set and get the IF register |
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| 176 | * |
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| 177 | * c3x_get_if - obtains IF register |
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| 178 | * c3x_set_if - sets IF register |
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| 179 | */ |
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| 180 | |
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| 181 | static inline unsigned int c3x_get_if(void) |
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| 182 | { |
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| 183 | register unsigned int _if_value; |
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| 184 | |
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| 185 | __asm__( "ldi if, %0" : "=r" (_if_value) ); |
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| 186 | return _if_value; |
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| 187 | } |
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| 188 | |
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| 189 | static inline void c3x_set_if(unsigned int _if_value) |
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| 190 | { |
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| 191 | __asm__( "ldi %0, if" : : "g" (_if_value) : "if", "cc"); |
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| 192 | } |
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| 193 | |
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| 194 | /* |
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| 195 | * Routines to set and get the IE register |
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| 196 | * |
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| 197 | * c3x_get_ie - obtains IE register |
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| 198 | * c3x_set_ie - sets IE register |
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| 199 | */ |
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| 200 | |
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| 201 | static inline unsigned int c3x_get_ie(void) |
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| 202 | { |
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| 203 | register unsigned int _ie_value; |
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| 204 | |
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| 205 | __asm__ volatile ( "ldi ie, %0" : "=r" (_ie_value) ); |
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| 206 | return _ie_value; |
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| 207 | } |
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| 208 | |
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| 209 | static inline void c3x_set_ie(unsigned int _ie_value) |
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| 210 | { |
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| 211 | __asm__ volatile ( "ldi %0, ie" : : "g" (_ie_value) : "ie", "cc"); |
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| 212 | } |
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| 213 | |
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| 214 | /* |
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| 215 | * Routines to manipulates the mask portion of the IE register. |
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| 216 | * |
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| 217 | * c3x_ie_mask_all - returns previous IE mask |
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| 218 | * c3x_ie_mask_restore - restores previous IE mask |
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| 219 | * c3x_ie_mask_flash - temporarily restores previous IE mask |
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| 220 | * c3x_ie_mask_set - sets a specific set of the IE mask |
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| 221 | */ |
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| 222 | |
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| 223 | #define c3x_ie_mask_all( _isr_cookie ) \ |
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| 224 | do { \ |
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| 225 | __asm__("ldi ie,%0\n" \ |
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| 226 | "\tandn 0ffffh, ie" \ |
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| 227 | : "=r" (_isr_cookie): : "ie", "cc" ); \ |
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| 228 | } while (0) |
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| 229 | |
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| 230 | #define c3x_ie_mask_restore( _isr_cookie ) \ |
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| 231 | do { \ |
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| 232 | __asm__("or %0, ie" \ |
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| 233 | : : "g" (_isr_cookie) : "ie", "cc" ); \ |
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| 234 | } while (0) |
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| 235 | |
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| 236 | #define c3x_ie_mask_flash( _isr_cookie ) \ |
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| 237 | do { \ |
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| 238 | __asm__("or %0, ie\n" \ |
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| 239 | "\tandn 0ffffh, ie" \ |
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| 240 | : : "g" (_isr_cookie) : "ie", "cc" ); \ |
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| 241 | } while (0) |
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| 242 | |
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| 243 | #define c3x_ie_mask_set( _new_mask ) \ |
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| 244 | do { unsigned int _ie_mask; \ |
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| 245 | unsigned int _ie_value; \ |
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| 246 | \ |
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| 247 | if ( _new_mask == 0 ) _ie_mask = 0; \ |
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| 248 | else _ie_mask = 0xffff; \ |
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| 249 | _ie_value = c3x_get_ie(); \ |
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| 250 | _ie_value &= C4X_IE_INTERRUPT_MASK_BITS; \ |
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| 251 | _ie_value |= _ie_mask; \ |
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| 252 | c3x_set_ie(_ie_value); \ |
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| 253 | } while (0) |
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| 254 | #endif |
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| 255 | /* end of C3x specific interrupt flag routines */ |
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| 256 | |
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| 257 | /* |
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| 258 | * This is a section of C4x specific interrupt flag management routines. |
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| 259 | */ |
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| 260 | |
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| 261 | #ifdef _TMS320C40 |
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| 262 | |
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| 263 | /* |
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| 264 | * Routines to set and get the IIF register |
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| 265 | * |
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| 266 | * c4x_get_iif - obtains IIF register |
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| 267 | * c4x_set_iif - sets IIF register |
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| 268 | */ |
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| 269 | |
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| 270 | static inline unsigned int c4x_get_iif(void) |
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| 271 | { |
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| 272 | register unsigned int _iif_value; |
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| 273 | |
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| 274 | __asm__( "ldi iif, %0" : "=r" (_iif_value) ); |
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| 275 | return _iif_value; |
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| 276 | } |
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| 277 | |
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| 278 | static inline void c4x_set_iif(unsigned int _iif_value) |
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| 279 | { |
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| 280 | __asm__( "ldi %0, iif" : : "g" (_iif_value) : "iif", "cc"); |
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| 281 | } |
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| 282 | |
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| 283 | /* |
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| 284 | * Routines to set and get the IIE register |
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| 285 | * |
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| 286 | * c4x_get_iie - obtains IIE register |
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| 287 | * c4x_set_iie - sets IIE register |
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| 288 | */ |
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| 289 | |
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| 290 | static inline unsigned int c4x_get_iie(void) |
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| 291 | { |
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| 292 | register unsigned int _iie_value; |
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| 293 | |
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| 294 | __asm__( "ldi iie, %0" : "=r" (_iie_value) ); |
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| 295 | return _iie_value; |
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| 296 | } |
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| 297 | |
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| 298 | static inline void c4x_set_iie(unsigned int _iie_value) |
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| 299 | { |
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| 300 | __asm__( "ldi %0, iie" : : "g" (_iie_value) : "iie", "cc"); |
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| 301 | } |
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| 302 | |
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| 303 | /* |
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| 304 | * Routines to manipulates the mask portion of the IIE register. |
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| 305 | * |
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| 306 | * c4x_ie_mask_all - returns previous IIE mask |
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| 307 | * c4x_ie_mask_restore - restores previous IIE mask |
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| 308 | * c4x_ie_mask_flash - temporarily restores previous IIE mask |
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| 309 | * c4x_ie_mask_set - sets a specific set of the IIE mask |
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| 310 | */ |
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| 311 | |
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| 312 | #if 0 |
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| 313 | #warning "C4x IIE masking routines not implemented." |
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| 314 | #define c4x_iie_mask_all( _isr_cookie ) |
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| 315 | #define c4x_iie_mask_restore( _isr_cookie ) |
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| 316 | #define c4x_iie_mask_flash( _isr_cookie ) |
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| 317 | #define c4x_iie_mask_set( _new_mask ) |
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| 318 | #endif |
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| 319 | |
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| 320 | #endif |
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| 321 | /* end of C4x specific interrupt flag routines */ |
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| 322 | |
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| 323 | /* |
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| 324 | * Routines to access the Interrupt Trap Table Pointer |
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| 325 | * |
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| 326 | * c4x_get_ittp - get ITTP |
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| 327 | * c4x_set_ittp - set ITTP |
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| 328 | */ |
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| 329 | |
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| 330 | static inline void * c4x_get_ittp(void) |
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| 331 | { |
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| 332 | register unsigned int _if_value; |
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| 333 | |
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| 334 | __asm__( "ldi if, %0" : "=r" (_if_value) ); |
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[8eacefcc] | 335 | return (void *)((_if_value & 0xffff0000) >> 8); |
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[61ba9763] | 336 | } |
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| 337 | |
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| 338 | static inline void c4x_set_ittp(void *_ittp_value) |
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| 339 | { |
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| 340 | unsigned int _if_value; |
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| 341 | unsigned int _ittp_field; |
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| 342 | |
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| 343 | #ifdef _TMS320C40 |
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| 344 | _if_value = c4x_get_iif(); |
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| 345 | #else |
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| 346 | _if_value = c3x_get_if(); |
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| 347 | #endif |
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| 348 | _if_value &= 0xffff; |
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[8eacefcc] | 349 | _ittp_field = (((unsigned int) _ittp_value) >> 8); |
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| 350 | _if_value |= _ittp_field << 16 ; |
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[61ba9763] | 351 | #ifdef _TMS320C40 |
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| 352 | c4x_set_iif( _if_value ); |
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| 353 | #else |
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| 354 | c3x_set_if( _if_value ); |
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| 355 | #endif |
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| 356 | } |
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| 357 | |
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| 358 | #endif /* ifndef ASM */ |
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| 359 | |
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| 360 | #ifdef __cplusplus |
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| 361 | } |
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| 362 | #endif |
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| 363 | |
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| 364 | #endif /* ! _INCLUDE_C4X_h */ |
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| 365 | /* end of include file */ |
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