source: rtems/c/src/exec/score/cpu/arm/rtems/score/cpu.h @ 4f0b287

4.104.114.84.95
Last change on this file since 4f0b287 was 4f0b287, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 17, 2002 at 5:14:31 PM

2002-07-17 Jay Monkman <jtm@…>

  • rtems/score/cpu_asm.h: Enhanced to include register offsets.
  • Makefile.am: Install rtems/score/cpu_asm.h.
  • cpu.c: Significantly enhanced including the implementation of _CPU_ISR_Get_level.
  • cpu_asm.S: Improved behavior of context switch and interrupt dispatching.
  • rtems/score/arm.h: Improved the CPU model name determination.
  • rtems/score/cpu.h: Improved interrupt disable/enable functions.
  • Property mode set to 100644
File size: 31.3 KB
Line 
1/*
2 *  This include file contains information pertaining to the ARM
3 *  processor.
4 *
5 *  COPYRIGHT (c) 2002 Advent Networks, Inc.
6 *        Jay Monkman <jmonkman@adventnetworks.com>
7 *
8 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
9 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.OARcorp.com/rtems/license.html.
14 *
15 *  $Id$
16 */
17
18/* FIXME: finish commenting/cleaning up this file */
19#ifndef __CPU_h
20#define __CPU_h
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/arm.h>            /* pick up machine definitions */
27#ifndef ASM
28#include <rtems/score/types.h>
29#endif
30
31/* conditional compilation parameters */
32
33/*
34 *  Should the calls to _Thread_Enable_dispatch be inlined?
35 *
36 *  If TRUE, then they are inlined.
37 *  If FALSE, then a subroutine call is made.
38 *
39 *  Basically this is an example of the classic trade-off of size
40 *  versus speed.  Inlining the call (TRUE) typically increases the
41 *  size of RTEMS while speeding up the enabling of dispatching.
42 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
43 *  only be 0 or 1 unless you are in an interrupt handler and that
44 *  interrupt handler invokes the executive.]  When not inlined
45 *  something calls _Thread_Enable_dispatch which in turns calls
46 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
47 *  one subroutine call is avoided entirely.]
48 */
49
50#define CPU_INLINE_ENABLE_DISPATCH       TRUE
51
52/*
53 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
54 *  be unrolled one time?  In unrolled each iteration of the loop examines
55 *  two "nodes" on the chain being searched.  Otherwise, only one node
56 *  is examined per iteration.
57 *
58 *  If TRUE, then the loops are unrolled.
59 *  If FALSE, then the loops are not unrolled.
60 *
61 *  The primary factor in making this decision is the cost of disabling
62 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
63 *  body of the loop.  On some CPUs, the flash is more expensive than
64 *  one iteration of the loop body.  In this case, it might be desirable
65 *  to unroll the loop.  It is important to note that on some CPUs, this
66 *  code is the longest interrupt disable period in RTEMS.  So it is
67 *  necessary to strike a balance when setting this parameter.
68 */
69
70#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
71
72/*
73 *  Does RTEMS manage a dedicated interrupt stack in software?
74 *
75 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
76 *  If FALSE, nothing is done.
77 *
78 *  If the CPU supports a dedicated interrupt stack in hardware,
79 *  then it is generally the responsibility of the BSP to allocate it
80 *  and set it up.
81 *
82 *  If the CPU does not support a dedicated interrupt stack, then
83 *  the porter has two options: (1) execute interrupts on the
84 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
85 *  interrupt stack.
86 *
87 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
88 *
89 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
90 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
91 *  possible that both are FALSE for a particular CPU.  Although it
92 *  is unclear what that would imply about the interrupt processing
93 *  procedure on that CPU.
94 */
95
96#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
97
98/*
99 *  Does this CPU have hardware support for a dedicated interrupt stack?
100 *
101 *  If TRUE, then it must be installed during initialization.
102 *  If FALSE, then no installation is performed.
103 *
104 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
105 *
106 *  Only one of CPU_HAS_SOFTWARE_INTERRU
107 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
108 *  possible that both are FALSE for a particular CPU.  Although it
109 *  is unclear what that would imply about the interrupt processing
110 *  procedure on that CPU.
111 */
112
113#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
114
115/*
116 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
117 *
118 *  If TRUE, then the memory is allocated during initialization.
119 *  If FALSE, then the memory is allocated during initialization.
120 *
121 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
122 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
123 */
124
125#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
126
127/*
128 *  Does the RTEMS invoke the user's ISR with the vector number and
129 *  a pointer to the saved interrupt frame (1) or just the vector
130 *  number (0)?
131 */
132
133#define CPU_ISR_PASSES_FRAME_POINTER 0
134
135/*
136 *  Does the CPU have hardware floating point?
137 *
138 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
139 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
140 *
141 *  If there is a FP coprocessor such as the i387 or mc68881, then
142 *  the answer is TRUE.
143 *
144 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
145 *  It indicates whether or not this CPU model has FP support.  For
146 *  example, it would be possible to have an i386_nofp CPU model
147 *  which set this to false to indicate that you have an i386 without
148 *  an i387 and wish to leave floating point support out of RTEMS.
149 */
150
151#if ( ARM_HAS_FPU == 1 )
152#define CPU_HARDWARE_FP     TRUE
153#else
154#define CPU_HARDWARE_FP     FALSE
155#endif
156
157#define CPU_SOFTWARE_FP     FALSE
158
159/*
160 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
161 *
162 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
163 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
164 *
165 *  So far, the only CPU in which this option has been used is the
166 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
167 *  floating point registers to perform integer multiplies.  If
168 *  a function which you would not think utilize the FP unit DOES,
169 *  then one can not easily predict which tasks will use the FP hardware.
170 *  In this case, this option should be TRUE.
171 *
172 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
173 */
174
175#define CPU_ALL_TASKS_ARE_FP     FALSE
176
177/*
178 *  Should the IDLE task have a floating point context?
179 *
180 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
181 *  and it has a floating point context which is switched in and out.
182 *  If FALSE, then the IDLE task does not have a floating point context.
183 *
184 *  Setting this to TRUE negatively impacts the time required to preempt
185 *  the IDLE task from an interrupt because the floating point context
186 *  must be saved as part of the preemption.
187 */
188
189#define CPU_IDLE_TASK_IS_FP      FALSE
190
191/*
192 *  Should the saving of the floating point registers be deferred
193 *  until a context switch is made to another different floating point
194 *  task?
195 *
196 *  If TRUE, then the floating point context will not be stored until
197 *  necessary.  It will remain in the floating point registers and not
198 *  disturned until another floating point task is switched to.
199 *
200 *  If FALSE, then the floating point context is saved when a floating
201 *  point task is switched out and restored when the next floating point
202 *  task is restored.  The state of the floating point registers between
203 *  those two operations is not specified.
204 *
205 *  If the floating point context does NOT have to be saved as part of
206 *  interrupt dispatching, then it should be safe to set this to TRUE.
207 *
208 *  Setting this flag to TRUE results in using a different algorithm
209 *  for deciding when to save and restore the floating point context.
210 *  The deferred FP switch algorithm minimizes the number of times
211 *  the FP context is saved and restored.  The FP context is not saved
212 *  until a context switch is made to another, different FP task.
213 *  Thus in a system with only one FP task, the FP context will never
214 *  be saved or restored.
215 */
216
217#define CPU_USE_DEFERRED_FP_SWITCH   FALSE
218
219/*
220 *  Does this port provide a CPU dependent IDLE task implementation?
221 *
222 *  If TRUE, then the routine _CPU_Thread_Idle_body
223 *  must be provided and is the default IDLE thread body instead of
224 *  _CPU_Thread_Idle_body.
225 *
226 *  If FALSE, then use the generic IDLE thread body if the BSP does
227 *  not provide one.
228 *
229 *  This is intended to allow for supporting processors which have
230 *  a low power or idle mode.  When the IDLE thread is executed, then
231 *  the CPU can be powered down.
232 *
233 *  The order of precedence for selecting the IDLE thread body is:
234 *
235 *    1.  BSP provided
236 *    2.  CPU dependent (if provided)
237 *    3.  generic (if no BSP and no CPU dependent)
238 */
239
240#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
241
242/*
243 *  Does the stack grow up (toward higher addresses) or down
244 *  (toward lower addresses)?
245 *
246 *  If TRUE, then the grows upward.
247 *  If FALSE, then the grows toward smaller addresses.
248 */
249
250#define CPU_STACK_GROWS_UP               FALSE
251
252/*
253 *  The following is the variable attribute used to force alignment
254 *  of critical RTEMS structures.  On some processors it may make
255 *  sense to have these aligned on tighter boundaries than
256 *  the minimum requirements of the compiler in order to have as
257 *  much of the critical data area as possible in a cache line.
258 *
259 *  The placement of this macro in the declaration of the variables
260 *  is based on the syntactically requirements of the GNU C
261 *  "__attribute__" extension.  For example with GNU C, use
262 *  the following to force a structures to a 32 byte boundary.
263 *
264 *      __attribute__ ((aligned (32)))
265 *
266 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
267 *         To benefit from using this, the data must be heavily
268 *         used so it will stay in the cache and used frequently enough
269 *         in the executive to justify turning this on.
270 */
271
272#define CPU_STRUCTURE_ALIGNMENT  __attribute__ ((aligned (32)))
273
274/*
275 *  Define what is required to specify how the network to host conversion
276 *  routines are handled.
277 */
278
279#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
280#define CPU_BIG_ENDIAN                           FALSE
281#define CPU_LITTLE_ENDIAN                        TRUE
282
283/*
284 *  The following defines the number of bits actually used in the
285 *  interrupt field of the task mode.  How those bits map to the
286 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
287 */
288
289#define CPU_MODES_INTERRUPT_MASK   0x000000c0
290
291/*
292 *  Processor defined structures
293 *
294 *  Examples structures include the descriptor tables from the i386
295 *  and the processor control structure on the i960ca.
296 */
297
298/* may need to put some structures here.  */
299
300/*
301 * Contexts
302 *
303 *  Generally there are 2 types of context to save.
304 *     1. Interrupt registers to save
305 *     2. Task level registers to save
306 *
307 *  This means we have the following 3 context items:
308 *     1. task level context stuff::  Context_Control
309 *     2. floating point task stuff:: Context_Control_fp
310 *     3. special interrupt level context :: Context_Control_interrupt
311 *
312 *  On some processors, it is cost-effective to save only the callee
313 *  preserved registers during a task context switch.  This means
314 *  that the ISR code needs to save those registers which do not
315 *  persist across function calls.  It is not mandatory to make this
316 *  distinctions between the caller/callee saves registers for the
317 *  purpose of minimizing context saved during task switch and on interrupts.
318 *  If the cost of saving extra registers is minimal, simplicity is the
319 *  choice.  Save the same context on interrupt entry as for tasks in
320 *  this case.
321 *
322 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
323 *  care should be used in designing the context area.
324 *
325 *  On some CPUs with hardware floating point support, the Context_Control_fp
326 *  structure will not be used or it simply consist of an array of a
327 *  fixed number of bytes.   This is done when the floating point context
328 *  is dumped by a "FP save context" type instruction and the format
329 *  is not really defined by the CPU.  In this case, there is no need
330 *  to figure out the exact format -- only the size.  Of course, although
331 *  this is enough information for RTEMS, it is probably not enough for
332 *  a debugger such as gdb.  But that is another problem.
333 */
334
335typedef struct {
336    unsigned32 register_r0;
337    unsigned32 register_r1;
338    unsigned32 register_r2;
339    unsigned32 register_r3;
340    unsigned32 register_r4;
341    unsigned32 register_r5;
342    unsigned32 register_r6;
343    unsigned32 register_r7;
344    unsigned32 register_r8;
345    unsigned32 register_r9;
346    unsigned32 register_r10;
347    unsigned32 register_fp;
348    unsigned32 register_ip;
349    unsigned32 register_sp;
350    unsigned32 register_lr;
351    unsigned32 register_pc;
352    unsigned32 register_cpsr;
353} Context_Control;
354
355typedef struct {
356    double      some_float_register;
357} Context_Control_fp;
358
359typedef Context_Control CPU_Exception_frame;
360
361typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
362extern cpuExcHandlerType _currentExcHandler;
363extern void rtems_exception_init_mngt();
364 
365/*
366 *  The following structure defines the set of information saved
367 *  on the current stack by RTEMS upon receipt of each interrupt
368 *  that will lead to re-enter the kernel to signal the thread.
369 */
370
371typedef CPU_Exception_frame CPU_Interrupt_frame;
372
373/*
374 *  The following table contains the information required to configure
375 *  the ARM processor specific parameters.
376 */
377
378typedef struct {
379  void       (*pretasking_hook)( void );
380  void       (*predriver_hook)( void );
381  void       (*postdriver_hook)( void );
382  void       (*idle_task)( void );
383  boolean      do_zero_of_workspace;
384  unsigned32   idle_task_stack_size;
385  unsigned32   interrupt_stack_size;
386  unsigned32   extra_mpci_receive_server_stack;
387  void *     (*stack_allocate_hook)( unsigned32 );
388  void       (*stack_free_hook)( void* );
389  /* end of fields required on all CPUs */
390
391}   rtems_cpu_table;
392
393/*
394 *  Macros to access required entires in the CPU Table are in
395 *  the file rtems/system.h.
396 */
397
398/*
399 *  Macros to access NO_CPU specific additions to the CPU Table
400 */
401
402/* There are no CPU specific additions to the CPU Table for this port. */
403
404/*
405 *  This variable is optional.  It is used on CPUs on which it is difficult
406 *  to generate an "uninitialized" FP context.  It is filled in by
407 *  _CPU_Initialize and copied into the task's FP context area during
408 *  _CPU_Context_Initialize.
409 */
410
411SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
412
413/*
414 *  On some CPUs, RTEMS supports a software managed interrupt stack.
415 *  This stack is allocated by the Interrupt Manager and the switch
416 *  is performed in _ISR_Handler.  These variables contain pointers
417 *  to the lowest and highest addresses in the chunk of memory allocated
418 *  for the interrupt stack.  Since it is unknown whether the stack
419 *  grows up or down (in general), this give the CPU dependent
420 *  code the option of picking the version it wants to use.
421 *
422 *  NOTE: These two variables are required if the macro
423 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
424 */
425
426SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
427SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
428
429/*
430 *  With some compilation systems, it is difficult if not impossible to
431 *  call a high-level language routine from assembly language.  This
432 *  is especially true of commercial Ada compilers and name mangling
433 *  C++ ones.  This variable can be optionally defined by the CPU porter
434 *  and contains the address of the routine _Thread_Dispatch.  This
435 *  can make it easier to invoke that routine at the end of the interrupt
436 *  sequence (if a dispatch is necessary).
437 */
438
439SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
440
441/*
442 *  Nothing prevents the porter from declaring more CPU specific variables.
443 */
444
445/* XXX: if needed, put more variables here */
446
447/*
448 *  The size of the floating point context area.  On some CPUs this
449 *  will not be a "sizeof" because the format of the floating point
450 *  area is not defined -- only the size is.  This is usually on
451 *  CPUs with a "floating point save context" instruction.
452 */
453
454#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
455
456/*
457 *  Amount of extra stack (above minimum stack size) required by
458 *  MPCI receive server thread.  Remember that in a multiprocessor
459 *  system this thread must exist and be able to process all directives.
460 */
461
462#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
463
464/*
465 *  This defines the number of entries in the ISR_Vector_table managed
466 *  by RTEMS.
467 */
468
469#define CPU_INTERRUPT_NUMBER_OF_VECTORS      8
470#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
471
472/*
473 *  This is defined if the port has a special way to report the ISR nesting
474 *  level.  Most ports maintain the variable _ISR_Nest_level.
475 */
476
477#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
478
479/*
480 *  Should be large enough to run all RTEMS tests.  This insures
481 *  that a "reasonable" small application should not have any problems.
482 */
483
484#define CPU_STACK_MINIMUM_SIZE          (1024*16)
485
486/*
487 *  CPU's worst alignment requirement for data types on a byte boundary.  This
488 *  alignment does not take into account the requirements for the stack.
489 */
490
491#define CPU_ALIGNMENT              4
492
493/*
494 *  This number corresponds to the byte alignment requirement for the
495 *  heap handler.  This alignment requirement may be stricter than that
496 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
497 *  common for the heap to follow the same alignment requirement as
498 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
499 *  then this should be set to CPU_ALIGNMENT.
500 *
501 *  NOTE:  This does not have to be a power of 2.  It does have to
502 *         be greater or equal to than CPU_ALIGNMENT.
503 */
504
505#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
506
507/*
508 *  This number corresponds to the byte alignment requirement for memory
509 *  buffers allocated by the partition manager.  This alignment requirement
510 *  may be stricter than that for the data types alignment specified by
511 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
512 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
513 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
514 *
515 *  NOTE:  This does not have to be a power of 2.  It does have to
516 *         be greater or equal to than CPU_ALIGNMENT.
517 */
518
519#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
520
521/*
522 *  This number corresponds to the byte alignment requirement for the
523 *  stack.  This alignment requirement may be stricter than that for the
524 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
525 *  is strict enough for the stack, then this should be set to 0.
526 *
527 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
528 */
529
530#define CPU_STACK_ALIGNMENT        4
531
532/* ISR handler macros */
533
534/*
535 *  Support routine to initialize the RTEMS vector table after it is allocated.
536 */
537
538#define _CPU_Initialize_vectors()
539
540/*
541 *  Disable all interrupts for an RTEMS critical section.  The previous
542 *  level is returned in _level.
543 */
544
545#define _CPU_ISR_Disable( _level )                \
546  do {                                            \
547    int reg;                                      \
548    asm volatile ("MRS        %0, cpsr \n"        \
549                  "ORR  %1, %0, #0xc0 \n"         \
550                  "MSR  cpsr, %1 \n"              \
551                  "AND  %0, %0, #0xc0 \n"         \
552                   : "=r" (_level), "=r" (reg)    \
553                   : "0" (_level), "1" (reg));    \
554  } while (0)
555
556/*
557 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
558 *  This indicates the end of an RTEMS critical section.  The parameter
559 *  _level is not modified.
560 */
561
562#define _CPU_ISR_Enable( _level )               \
563  do {                                          \
564    int reg;                                    \
565    asm volatile ("MRS        %0, cpsr \n"      \
566                  "BIC  %0, %0, #0xc0 \n"       \
567                  "ORR  %0, %0, %2 \n"          \
568                  "MSR  cpsr, %0 \n"            \
569                  : "=r" (reg)                  \
570                  : "0" (reg), "r" (_level));   \
571  } while (0)
572
573/*
574 *  This temporarily restores the interrupt to _level before immediately
575 *  disabling them again.  This is used to divide long RTEMS critical
576 *  sections into two or more parts.  The parameter _level is not
577 * modified.
578 */
579
580#define _CPU_ISR_Flash( _level ) \
581  { \
582    int reg1;                                   \
583    int reg2;                                   \
584    asm volatile ("MRS  %0, cpsr \n"            \
585                  "BIC  %1, %0, #0xc0 \n"       \
586                  "ORR  %1, %1, %4 \n"          \
587                  "MSR  cpsr, %1 \n"            \
588                  "MSR  cpsr, %0 \n"            \
589                  : "=r" (reg1), "=r" (reg2)    \
590                  : "0" (reg1), "1" (reg2),  "r" (_level));       \
591  }
592
593/*
594 *  Map interrupt level in task mode onto the hardware that the CPU
595 *  actually provides.  Currently, interrupt levels which do not
596 *  map onto the CPU in a generic fashion are undefined.  Someday,
597 *  it would be nice if these were "mapped" by the application
598 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
599 *  8 - 255 would be available for bsp/application specific meaning.
600 *  This could be used to manage a programmable interrupt controller
601 *  via the rtems_task_mode directive.
602 *
603 *  The get routine usually must be implemented as a subroutine.
604 */
605
606#define _CPU_ISR_Set_level( new_level ) \
607  { \
608    int reg;                                    \
609    asm volatile ("MRS  %0, cpsr \n"            \
610                  "BIC  %0, %0, #0xc0 \n"            \
611                  "ORR  %0, %0, %2 \n"          \
612                  "MSR  cpsr_c, %0 \n"            \
613                  : "=r" (reg)                 \
614                  : "0" (reg), "r" (new_level)); \
615  }
616
617
618unsigned32 _CPU_ISR_Get_level( void );
619
620/* end of ISR handler macros */
621
622/* Context handler macros */
623
624/*
625 *  Initialize the context to a state suitable for starting a
626 *  task after a context restore operation.  Generally, this
627 *  involves:
628 *
629 *     - setting a starting address
630 *     - preparing the stack
631 *     - preparing the stack and frame pointers
632 *     - setting the proper interrupt level in the context
633 *     - initializing the floating point context
634 *
635 *  This routine generally does not set any unnecessary register
636 *  in the context.  The state of the "general data" registers is
637 *  undefined at task start time.
638 *
639 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
640 *        point thread.  This is typically only used on CPUs where the
641 *        FPU may be easily disabled by software such as on the SPARC
642 *        where the PSR contains an enable FPU bit.
643 */
644
645void _CPU_Context_Initialize(
646  Context_Control  *the_context,
647  unsigned32       *stack_base,
648  unsigned32        size,
649  unsigned32        new_level,
650  void             *entry_point,
651  boolean           is_fp
652);
653
654/*
655 *  This routine is responsible for somehow restarting the currently
656 *  executing task.  If you are lucky, then all that is necessary
657 *  is restoring the context.  Otherwise, there will need to be
658 *  a special assembly routine which does something special in this
659 *  case.  Context_Restore should work most of the time.  It will
660 *  not work if restarting self conflicts with the stack frame
661 *  assumptions of restoring a context.
662 */
663
664#define _CPU_Context_Restart_self( _the_context ) \
665   _CPU_Context_restore( (_the_context) );
666
667/*
668 *  The purpose of this macro is to allow the initial pointer into
669 *  a floating point context area (used to save the floating point
670 *  context) to be at an arbitrary place in the floating point
671 *  context area.
672 *
673 *  This is necessary because some FP units are designed to have
674 *  their context saved as a stack which grows into lower addresses.
675 *  Other FP units can be saved by simply moving registers into offsets
676 *  from the base of the context area.  Finally some FP units provide
677 *  a "dump context" instruction which could fill in from high to low
678 *  or low to high based on the whim of the CPU designers.
679 */
680
681#define _CPU_Context_Fp_start( _base, _offset ) \
682   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
683
684/*
685 *  This routine initializes the FP context area passed to it to.
686 *  There are a few standard ways in which to initialize the
687 *  floating point context.  The code included for this macro assumes
688 *  that this is a CPU in which a "initial" FP context was saved into
689 *  _CPU_Null_fp_context and it simply copies it to the destination
690 *  context passed to it.
691 *
692 *  Other models include (1) not doing anything, and (2) putting
693 *  a "null FP status word" in the correct place in the FP context.
694 */
695
696#define _CPU_Context_Initialize_fp( _destination ) \
697  { \
698   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
699  }
700
701/* end of Context handler macros */
702
703/* Fatal Error manager macros */
704
705/*
706 *  This routine copies _error into a known place -- typically a stack
707 *  location or a register, optionally disables interrupts, and
708 *  halts/stops the CPU.
709 */
710
711#define _CPU_Fatal_halt( _error ) \
712  { \
713  }
714
715/* end of Fatal Error manager macros */
716
717/* Bitfield handler macros */
718
719/*
720 *  This routine sets _output to the bit number of the first bit
721 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
722 *  This type may be either 16 or 32 bits wide although only the 16
723 *  least significant bits will be used.
724 *
725 *  There are a number of variables in using a "find first bit" type
726 *  instruction.
727 *
728 *    (1) What happens when run on a value of zero?
729 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
730 *    (3) The numbering may be zero or one based.
731 *    (4) The "find first bit" instruction may search from MSB or LSB.
732 *
733 *  RTEMS guarantees that (1) will never happen so it is not a concern.
734 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
735 *  _CPU_Priority_bits_index().  These three form a set of routines
736 *  which must logically operate together.  Bits in the _value are
737 *  set and cleared based on masks built by _CPU_Priority_mask().
738 *  The basic major and minor values calculated by _Priority_Major()
739 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
740 *  to properly range between the values returned by the "find first bit"
741 *  instruction.  This makes it possible for _Priority_Get_highest() to
742 *  calculate the major and directly index into the minor table.
743 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
744 *  is the first bit found.
745 *
746 *  This entire "find first bit" and mapping process depends heavily
747 *  on the manner in which a priority is broken into a major and minor
748 *  components with the major being the 4 MSB of a priority and minor
749 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
750 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
751 *  to the lowest priority.
752 *
753 *  If your CPU does not have a "find first bit" instruction, then
754 *  there are ways to make do without it.  Here are a handful of ways
755 *  to implement this in software:
756 *
757 *    - a series of 16 bit test instructions
758 *    - a "binary search using if's"
759 *    - _number = 0
760 *      if _value > 0x00ff
761 *        _value >>=8
762 *        _number = 8;
763 *
764 *      if _value > 0x0000f
765 *        _value >=8
766 *        _number += 4
767 *
768 *      _number += bit_set_table[ _value ]
769 *
770 *    where bit_set_table[ 16 ] has values which indicate the first
771 *      bit set
772 */
773
774#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
775#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
776
777#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
778
779#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
780  { \
781    (_output) = 0;   /* do something to prevent warnings */ \
782  }
783
784#endif
785
786/* end of Bitfield handler macros */
787
788/*
789 *  This routine builds the mask which corresponds to the bit fields
790 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
791 *  for that routine.
792 */
793
794#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
795
796#define _CPU_Priority_Mask( _bit_number ) \
797  ( 1 << (_bit_number) )
798
799#endif
800
801/*
802 *  This routine translates the bit numbers returned by
803 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
804 *  a major or minor component of a priority.  See the discussion
805 *  for that routine.
806 */
807
808#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
809
810#define _CPU_Priority_bits_index( _priority ) \
811  (_priority)
812
813#endif
814
815/* end of Priority handler macros */
816
817/* functions */
818
819/*
820 *  _CPU_Initialize
821 *
822 *  This routine performs CPU dependent initialization.
823 */
824
825void _CPU_Initialize(
826  rtems_cpu_table  *cpu_table,
827  void      (*thread_dispatch)
828);
829
830typedef enum {
831  ARM_EXCEPTION_RESET      = 0,
832  ARM_EXCEPTION_UNDEF      = 1,
833  ARM_EXCEPTION_SWI        = 2,
834  ARM_EXCEPTION_PREF_ABORT = 3,
835  ARM_EXCEPTION_DATA_ABORT = 4,
836  ARM_EXCEPTION_RESERVED   = 5,
837  ARM_EXCEPTION_IRQ        = 6,
838  ARM_EXCEPTION_FIQ        = 7,
839  MAX_EXCEPTIONS           = 8
840} Arm_symbolic_exception_name;
841
842/*
843 *  _CPU_ISR_install_vector
844 *
845 *  This routine installs an interrupt vector.
846 */
847
848void _CPU_ISR_install_vector(
849  unsigned32  vector,
850  proc_ptr    new_handler,
851  proc_ptr   *old_handler
852);
853
854/*
855 *  _CPU_Install_interrupt_stack
856 *
857 *  This routine installs the hardware interrupt stack pointer.
858 *
859 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
860 *         is TRUE.
861 */
862
863void _CPU_Install_interrupt_stack( void );
864
865/*
866 *  _CPU_Thread_Idle_body
867 *
868 *  This routine is the CPU dependent IDLE thread body.
869 *
870 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
871 *         is TRUE.
872 */
873
874void _CPU_Thread_Idle_body( void );
875
876/*
877 *  _CPU_Context_switch
878 *
879 *  This routine switches from the run context to the heir context.
880 */
881
882void _CPU_Context_switch(
883  Context_Control  *run,
884  Context_Control  *heir
885);
886
887/*
888 *  _CPU_Context_restore
889 *
890 *  This routine is generally used only to restart self in an
891 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
892 *
893 *  NOTE: May be unnecessary to reload some registers.
894 */
895
896void _CPU_Context_restore(
897  Context_Control *new_context
898);
899
900/*
901 *  _CPU_Context_save_fp
902 *
903 *  This routine saves the floating point context passed to it.
904 */
905
906void _CPU_Context_save_fp(
907  void **fp_context_ptr
908);
909
910/*
911 *  _CPU_Context_restore_fp
912 *
913 *  This routine restores the floating point context passed to it.
914 */
915
916void _CPU_Context_restore_fp(
917  void **fp_context_ptr
918);
919
920/*  The following routine swaps the endian format of an unsigned int.
921 *  It must be static because it is referenced indirectly.
922 *
923 *  This version will work on any processor, but if there is a better
924 *  way for your CPU PLEASE use it.  The most common way to do this is to:
925 *
926 *     swap least significant two bytes with 16-bit rotate
927 *     swap upper and lower 16-bits
928 *     swap most significant two bytes with 16-bit rotate
929 *
930 *  Some CPUs have special instructions which swap a 32-bit quantity in
931 *  a single instruction (e.g. i486).  It is probably best to avoid
932 *  an "endian swapping control bit" in the CPU.  One good reason is
933 *  that interrupts would probably have to be disabled to insure that
934 *  an interrupt does not try to access the same "chunk" with the wrong
935 *  endian.  Another good reason is that on some CPUs, the endian bit
936 *  endianness for ALL fetches -- both code and data -- so the code
937 *  will be fetched incorrectly.
938 */
939 
940static inline unsigned int CPU_swap_u32(
941  unsigned int value
942)
943{
944  unsigned32 byte1, byte2, byte3, byte4, swapped;
945 
946  byte4 = (value >> 24) & 0xff;
947  byte3 = (value >> 16) & 0xff;
948  byte2 = (value >> 8)  & 0xff;
949  byte1 =  value        & 0xff;
950 
951  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
952  return( swapped );
953}
954
955#define CPU_swap_u16( value ) \
956  (((value&0xff) << 8) | ((value >> 8)&0xff))
957
958#ifdef __cplusplus
959}
960#endif
961
962#endif
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