source: rtems/c/src/exec/score/cpu/arm/rtems/score/cpu.h @ 2540208

4.104.114.84.95
Last change on this file since 2540208 was 2540208, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 5, 2002 at 6:09:59 PM

2002-07-05 Joel Sherrill <joel@…>

  • rtems/score/cpu.h: Filled in something that was marked XXX.
  • Property mode set to 100644
File size: 29.9 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the arm
4 *  processor.
5 *
6 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
7 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 */
14
15#ifndef __CPU_h
16#define __CPU_h
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#include <rtems/score/arm.h>            /* pick up machine definitions */
23#ifndef ASM
24#include <rtems/score/types.h>
25#endif
26
27/* conditional compilation parameters */
28
29/*
30 *  Should the calls to _Thread_Enable_dispatch be inlined?
31 *
32 *  If TRUE, then they are inlined.
33 *  If FALSE, then a subroutine call is made.
34 *
35 *  Basically this is an example of the classic trade-off of size
36 *  versus speed.  Inlining the call (TRUE) typically increases the
37 *  size of RTEMS while speeding up the enabling of dispatching.
38 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
39 *  only be 0 or 1 unless you are in an interrupt handler and that
40 *  interrupt handler invokes the executive.]  When not inlined
41 *  something calls _Thread_Enable_dispatch which in turns calls
42 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
43 *  one subroutine call is avoided entirely.]
44 */
45
46#define CPU_INLINE_ENABLE_DISPATCH       FALSE
47
48/*
49 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
50 *  be unrolled one time?  In unrolled each iteration of the loop examines
51 *  two "nodes" on the chain being searched.  Otherwise, only one node
52 *  is examined per iteration.
53 *
54 *  If TRUE, then the loops are unrolled.
55 *  If FALSE, then the loops are not unrolled.
56 *
57 *  The primary factor in making this decision is the cost of disabling
58 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
59 *  body of the loop.  On some CPUs, the flash is more expensive than
60 *  one iteration of the loop body.  In this case, it might be desirable
61 *  to unroll the loop.  It is important to note that on some CPUs, this
62 *  code is the longest interrupt disable period in RTEMS.  So it is
63 *  necessary to strike a balance when setting this parameter.
64 */
65
66#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
67
68/*
69 *  Does RTEMS manage a dedicated interrupt stack in software?
70 *
71 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
72 *  If FALSE, nothing is done.
73 *
74 *  If the CPU supports a dedicated interrupt stack in hardware,
75 *  then it is generally the responsibility of the BSP to allocate it
76 *  and set it up.
77 *
78 *  If the CPU does not support a dedicated interrupt stack, then
79 *  the porter has two options: (1) execute interrupts on the
80 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
81 *  interrupt stack.
82 *
83 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
84 *
85 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
86 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
87 *  possible that both are FALSE for a particular CPU.  Although it
88 *  is unclear what that would imply about the interrupt processing
89 *  procedure on that CPU.
90 */
91
92#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
93
94/*
95 *  Does this CPU have hardware support for a dedicated interrupt stack?
96 *
97 *  If TRUE, then it must be installed during initialization.
98 *  If FALSE, then no installation is performed.
99 *
100 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
101 *
102 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
103 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
104 *  possible that both are FALSE for a particular CPU.  Although it
105 *  is unclear what that would imply about the interrupt processing
106 *  procedure on that CPU.
107 */
108
109#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
110
111/*
112 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
113 *
114 *  If TRUE, then the memory is allocated during initialization.
115 *  If FALSE, then the memory is allocated during initialization.
116 *
117 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
118 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
119 */
120
121#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
122
123/*
124 *  Does the RTEMS invoke the user's ISR with the vector number and
125 *  a pointer to the saved interrupt frame (1) or just the vector
126 *  number (0)?
127 */
128
129#define CPU_ISR_PASSES_FRAME_POINTER 0
130
131/*
132 *  Does the CPU have hardware floating point?
133 *
134 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
135 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
136 *
137 *  If there is a FP coprocessor such as the i387 or mc68881, then
138 *  the answer is TRUE.
139 *
140 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
141 *  It indicates whether or not this CPU model has FP support.  For
142 *  example, it would be possible to have an i386_nofp CPU model
143 *  which set this to false to indicate that you have an i386 without
144 *  an i387 and wish to leave floating point support out of RTEMS.
145 */
146
147#if ( ARM_HAS_FPU == 1 )
148#define CPU_HARDWARE_FP     TRUE
149#else
150#define CPU_HARDWARE_FP     FALSE
151#endif
152
153#define CPU_SOFTWARE_FP     FALSE
154
155/*
156 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
157 *
158 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
159 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
160 *
161 *  So far, the only CPU in which this option has been used is the
162 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
163 *  floating point registers to perform integer multiplies.  If
164 *  a function which you would not think utilize the FP unit DOES,
165 *  then one can not easily predict which tasks will use the FP hardware.
166 *  In this case, this option should be TRUE.
167 *
168 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
169 */
170
171#define CPU_ALL_TASKS_ARE_FP     FALSE
172
173/*
174 *  Should the IDLE task have a floating point context?
175 *
176 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
177 *  and it has a floating point context which is switched in and out.
178 *  If FALSE, then the IDLE task does not have a floating point context.
179 *
180 *  Setting this to TRUE negatively impacts the time required to preempt
181 *  the IDLE task from an interrupt because the floating point context
182 *  must be saved as part of the preemption.
183 */
184
185#define CPU_IDLE_TASK_IS_FP      FALSE
186
187/*
188 *  Should the saving of the floating point registers be deferred
189 *  until a context switch is made to another different floating point
190 *  task?
191 *
192 *  If TRUE, then the floating point context will not be stored until
193 *  necessary.  It will remain in the floating point registers and not
194 *  disturned until another floating point task is switched to.
195 *
196 *  If FALSE, then the floating point context is saved when a floating
197 *  point task is switched out and restored when the next floating point
198 *  task is restored.  The state of the floating point registers between
199 *  those two operations is not specified.
200 *
201 *  If the floating point context does NOT have to be saved as part of
202 *  interrupt dispatching, then it should be safe to set this to TRUE.
203 *
204 *  Setting this flag to TRUE results in using a different algorithm
205 *  for deciding when to save and restore the floating point context.
206 *  The deferred FP switch algorithm minimizes the number of times
207 *  the FP context is saved and restored.  The FP context is not saved
208 *  until a context switch is made to another, different FP task.
209 *  Thus in a system with only one FP task, the FP context will never
210 *  be saved or restored.
211 */
212
213#define CPU_USE_DEFERRED_FP_SWITCH   FALSE
214
215/*
216 *  Does this port provide a CPU dependent IDLE task implementation?
217 *
218 *  If TRUE, then the routine _CPU_Thread_Idle_body
219 *  must be provided and is the default IDLE thread body instead of
220 *  _CPU_Thread_Idle_body.
221 *
222 *  If FALSE, then use the generic IDLE thread body if the BSP does
223 *  not provide one.
224 *
225 *  This is intended to allow for supporting processors which have
226 *  a low power or idle mode.  When the IDLE thread is executed, then
227 *  the CPU can be powered down.
228 *
229 *  The order of precedence for selecting the IDLE thread body is:
230 *
231 *    1.  BSP provided
232 *    2.  CPU dependent (if provided)
233 *    3.  generic (if no BSP and no CPU dependent)
234 */
235
236#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
237
238/*
239 *  Does the stack grow up (toward higher addresses) or down
240 *  (toward lower addresses)?
241 *
242 *  If TRUE, then the grows upward.
243 *  If FALSE, then the grows toward smaller addresses.
244 */
245
246#define CPU_STACK_GROWS_UP               FALSE
247
248/*
249 *  The following is the variable attribute used to force alignment
250 *  of critical RTEMS structures.  On some processors it may make
251 *  sense to have these aligned on tighter boundaries than
252 *  the minimum requirements of the compiler in order to have as
253 *  much of the critical data area as possible in a cache line.
254 *
255 *  The placement of this macro in the declaration of the variables
256 *  is based on the syntactically requirements of the GNU C
257 *  "__attribute__" extension.  For example with GNU C, use
258 *  the following to force a structures to a 32 byte boundary.
259 *
260 *      __attribute__ ((aligned (32)))
261 *
262 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
263 *         To benefit from using this, the data must be heavily
264 *         used so it will stay in the cache and used frequently enough
265 *         in the executive to justify turning this on.
266 */
267
268#define CPU_STRUCTURE_ALIGNMENT  __attribute__ ((aligned (32)))
269
270/*
271 *  Define what is required to specify how the network to host conversion
272 *  routines are handled.
273 */
274
275#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
276#define CPU_BIG_ENDIAN                           TRUE
277#define CPU_LITTLE_ENDIAN                        FALSE
278
279/*
280 *  The following defines the number of bits actually used in the
281 *  interrupt field of the task mode.  How those bits map to the
282 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
283 */
284
285#define CPU_MODES_INTERRUPT_MASK   0x00000001
286
287/*
288 *  Processor defined structures
289 *
290 *  Examples structures include the descriptor tables from the i386
291 *  and the processor control structure on the i960ca.
292 */
293
294/* may need to put some structures here.  */
295
296/*
297 * Contexts
298 *
299 *  Generally there are 2 types of context to save.
300 *     1. Interrupt registers to save
301 *     2. Task level registers to save
302 *
303 *  This means we have the following 3 context items:
304 *     1. task level context stuff::  Context_Control
305 *     2. floating point task stuff:: Context_Control_fp
306 *     3. special interrupt level context :: Context_Control_interrupt
307 *
308 *  On some processors, it is cost-effective to save only the callee
309 *  preserved registers during a task context switch.  This means
310 *  that the ISR code needs to save those registers which do not
311 *  persist across function calls.  It is not mandatory to make this
312 *  distinctions between the caller/callee saves registers for the
313 *  purpose of minimizing context saved during task switch and on interrupts.
314 *  If the cost of saving extra registers is minimal, simplicity is the
315 *  choice.  Save the same context on interrupt entry as for tasks in
316 *  this case.
317 *
318 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
319 *  care should be used in designing the context area.
320 *
321 *  On some CPUs with hardware floating point support, the Context_Control_fp
322 *  structure will not be used or it simply consist of an array of a
323 *  fixed number of bytes.   This is done when the floating point context
324 *  is dumped by a "FP save context" type instruction and the format
325 *  is not really defined by the CPU.  In this case, there is no need
326 *  to figure out the exact format -- only the size.  Of course, although
327 *  this is enough information for RTEMS, it is probably not enough for
328 *  a debugger such as gdb.  But that is another problem.
329 */
330
331typedef struct {
332    unsigned32 register_r0;
333    unsigned32 register_r1;
334    unsigned32 register_r2;
335    unsigned32 register_r3;
336    unsigned32 register_r4;
337    unsigned32 register_r5;
338    unsigned32 register_r6;
339    unsigned32 register_r7;
340    unsigned32 register_r8;
341    unsigned32 register_r9;
342    unsigned32 register_r10;
343    unsigned32 register_fp;
344    unsigned32 register_ip;
345    unsigned32 register_sp;
346    unsigned32 register_lr;
347    unsigned32 register_pc;
348} Context_Control;
349
350typedef struct {
351    double      some_float_register;
352} Context_Control_fp;
353
354typedef Context_Control CPU_Exception_frame;
355
356typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
357extern cpuExcHandlerType _currentExcHandler;
358extern void rtems_exception_init_mngt();
359 
360/*
361 *  The following structure defines the set of information saved
362 *  on the current stack by RTEMS upon receipt of each interrupt
363 *  that will lead to re-enter the kernel to signal the thread.
364 */
365
366typedef CPU_Exception_frame CPU_Interrupt_frame;
367
368/*
369 *  The following table contains the information required to configure
370 *  the ARM processor specific parameters.
371 */
372
373typedef struct {
374  void       (*pretasking_hook)( void );
375  void       (*predriver_hook)( void );
376  void       (*postdriver_hook)( void );
377  void       (*idle_task)( void );
378  boolean      do_zero_of_workspace;
379  unsigned32   idle_task_stack_size;
380  unsigned32   interrupt_stack_size;
381  unsigned32   extra_mpci_receive_server_stack;
382  void *     (*stack_allocate_hook)( unsigned32 );
383  void       (*stack_free_hook)( void* );
384  /* end of fields required on all CPUs */
385
386}   rtems_cpu_table;
387
388/*
389 *  Macros to access required entires in the CPU Table are in
390 *  the file rtems/system.h.
391 */
392
393/*
394 *  Macros to access NO_CPU specific additions to the CPU Table
395 */
396
397/* There are no CPU specific additions to the CPU Table for this port. */
398
399/*
400 *  This variable is optional.  It is used on CPUs on which it is difficult
401 *  to generate an "uninitialized" FP context.  It is filled in by
402 *  _CPU_Initialize and copied into the task's FP context area during
403 *  _CPU_Context_Initialize.
404 */
405
406SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
407
408/*
409 *  On some CPUs, RTEMS supports a software managed interrupt stack.
410 *  This stack is allocated by the Interrupt Manager and the switch
411 *  is performed in _ISR_Handler.  These variables contain pointers
412 *  to the lowest and highest addresses in the chunk of memory allocated
413 *  for the interrupt stack.  Since it is unknown whether the stack
414 *  grows up or down (in general), this give the CPU dependent
415 *  code the option of picking the version it wants to use.
416 *
417 *  NOTE: These two variables are required if the macro
418 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
419 */
420
421SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
422SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
423
424/*
425 *  With some compilation systems, it is difficult if not impossible to
426 *  call a high-level language routine from assembly language.  This
427 *  is especially true of commercial Ada compilers and name mangling
428 *  C++ ones.  This variable can be optionally defined by the CPU porter
429 *  and contains the address of the routine _Thread_Dispatch.  This
430 *  can make it easier to invoke that routine at the end of the interrupt
431 *  sequence (if a dispatch is necessary).
432 */
433
434SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
435
436/*
437 *  Nothing prevents the porter from declaring more CPU specific variables.
438 */
439
440/* XXX: if needed, put more variables here */
441
442/*
443 *  The size of the floating point context area.  On some CPUs this
444 *  will not be a "sizeof" because the format of the floating point
445 *  area is not defined -- only the size is.  This is usually on
446 *  CPUs with a "floating point save context" instruction.
447 */
448
449#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
450
451/*
452 *  Amount of extra stack (above minimum stack size) required by
453 *  MPCI receive server thread.  Remember that in a multiprocessor
454 *  system this thread must exist and be able to process all directives.
455 */
456
457#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
458
459/*
460 *  This defines the number of entries in the ISR_Vector_table managed
461 *  by RTEMS.
462 */
463
464#define CPU_INTERRUPT_NUMBER_OF_VECTORS      8
465#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
466
467/*
468 *  This is defined if the port has a special way to report the ISR nesting
469 *  level.  Most ports maintain the variable _ISR_Nest_level.
470 */
471
472#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
473
474/*
475 *  Should be large enough to run all RTEMS tests.  This insures
476 *  that a "reasonable" small application should not have any problems.
477 */
478
479#define CPU_STACK_MINIMUM_SIZE          (1024*4)
480
481/*
482 *  CPU's worst alignment requirement for data types on a byte boundary.  This
483 *  alignment does not take into account the requirements for the stack.
484 */
485
486#define CPU_ALIGNMENT              8
487
488/*
489 *  This number corresponds to the byte alignment requirement for the
490 *  heap handler.  This alignment requirement may be stricter than that
491 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
492 *  common for the heap to follow the same alignment requirement as
493 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
494 *  then this should be set to CPU_ALIGNMENT.
495 *
496 *  NOTE:  This does not have to be a power of 2.  It does have to
497 *         be greater or equal to than CPU_ALIGNMENT.
498 */
499
500#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
501
502/*
503 *  This number corresponds to the byte alignment requirement for memory
504 *  buffers allocated by the partition manager.  This alignment requirement
505 *  may be stricter than that for the data types alignment specified by
506 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
507 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
508 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
509 *
510 *  NOTE:  This does not have to be a power of 2.  It does have to
511 *         be greater or equal to than CPU_ALIGNMENT.
512 */
513
514#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
515
516/*
517 *  This number corresponds to the byte alignment requirement for the
518 *  stack.  This alignment requirement may be stricter than that for the
519 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
520 *  is strict enough for the stack, then this should be set to 0.
521 *
522 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
523 */
524
525#define CPU_STACK_ALIGNMENT        32
526
527/* ISR handler macros */
528
529/*
530 *  Support routine to initialize the RTEMS vector table after it is allocated.
531 */
532
533#define _CPU_Initialize_vectors()
534
535/*
536 *  Disable all interrupts for an RTEMS critical section.  The previous
537 *  level is returned in _level.
538 */
539
540#define _CPU_ISR_Disable( _level ) \
541  { \
542    (_level) = 0; \
543   asm volatile ("MRS r0, cpsr          \n"  \
544                 "ORR  r0, r0, #0xc0    \n" \
545                 "MSR  cpsr, r0         \n" \
546                   : : : "r0"); \
547  }
548
549/*
550 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
551 *  This indicates the end of an RTEMS critical section.  The parameter
552 *  _level is not modified.
553 */
554
555#define _CPU_ISR_Enable( _level )  \
556  { \
557   asm volatile ("MRS r0, cpsr                  \n"  \
558                 "AND  r0, r0, #0xFFFFFF3F      \n" \
559                 "MSR  cpsr, r0                 \n" \
560                 : : : "r0" ); \
561  }
562 
563/*
564 *  This temporarily restores the interrupt to _level before immediately
565 *  disabling them again.  This is used to divide long RTEMS critical
566 *  sections into two or more parts.  The parameter _level is not
567 * modified.
568 */
569
570#define _CPU_ISR_Flash( _isr_cookie ) \
571  { \
572  }
573
574/*
575 *  Map interrupt level in task mode onto the hardware that the CPU
576 *  actually provides.  Currently, interrupt levels which do not
577 *  map onto the CPU in a generic fashion are undefined.  Someday,
578 *  it would be nice if these were "mapped" by the application
579 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
580 *  8 - 255 would be available for bsp/application specific meaning.
581 *  This could be used to manage a programmable interrupt controller
582 *  via the rtems_task_mode directive.
583 *
584 *  The get routine usually must be implemented as a subroutine.
585 */
586
587#define _CPU_ISR_Set_level( new_level ) \
588  { \
589  }
590
591unsigned32 _CPU_ISR_Get_level( void );
592
593/* end of ISR handler macros */
594
595/* Context handler macros */
596
597/*
598 *  Initialize the context to a state suitable for starting a
599 *  task after a context restore operation.  Generally, this
600 *  involves:
601 *
602 *     - setting a starting address
603 *     - preparing the stack
604 *     - preparing the stack and frame pointers
605 *     - setting the proper interrupt level in the context
606 *     - initializing the floating point context
607 *
608 *  This routine generally does not set any unnecessary register
609 *  in the context.  The state of the "general data" registers is
610 *  undefined at task start time.
611 *
612 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
613 *        point thread.  This is typically only used on CPUs where the
614 *        FPU may be easily disabled by software such as on the SPARC
615 *        where the PSR contains an enable FPU bit.
616 */
617
618#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
619                                 _isr, _entry_point, _is_fp ) \
620  { \
621   (_the_context)->register_sp = ((unsigned32)(_stack_base)) + (_size) ; \
622   (_the_context)->register_pc = (_entry_point); \
623  }
624
625/*
626 *  This routine is responsible for somehow restarting the currently
627 *  executing task.  If you are lucky, then all that is necessary
628 *  is restoring the context.  Otherwise, there will need to be
629 *  a special assembly routine which does something special in this
630 *  case.  Context_Restore should work most of the time.  It will
631 *  not work if restarting self conflicts with the stack frame
632 *  assumptions of restoring a context.
633 */
634
635#define _CPU_Context_Restart_self( _the_context ) \
636   _CPU_Context_restore( (_the_context) );
637
638/*
639 *  The purpose of this macro is to allow the initial pointer into
640 *  a floating point context area (used to save the floating point
641 *  context) to be at an arbitrary place in the floating point
642 *  context area.
643 *
644 *  This is necessary because some FP units are designed to have
645 *  their context saved as a stack which grows into lower addresses.
646 *  Other FP units can be saved by simply moving registers into offsets
647 *  from the base of the context area.  Finally some FP units provide
648 *  a "dump context" instruction which could fill in from high to low
649 *  or low to high based on the whim of the CPU designers.
650 */
651
652#define _CPU_Context_Fp_start( _base, _offset ) \
653   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
654
655/*
656 *  This routine initializes the FP context area passed to it to.
657 *  There are a few standard ways in which to initialize the
658 *  floating point context.  The code included for this macro assumes
659 *  that this is a CPU in which a "initial" FP context was saved into
660 *  _CPU_Null_fp_context and it simply copies it to the destination
661 *  context passed to it.
662 *
663 *  Other models include (1) not doing anything, and (2) putting
664 *  a "null FP status word" in the correct place in the FP context.
665 */
666
667#define _CPU_Context_Initialize_fp( _destination ) \
668  { \
669   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
670  }
671
672/* end of Context handler macros */
673
674/* Fatal Error manager macros */
675
676/*
677 *  This routine copies _error into a known place -- typically a stack
678 *  location or a register, optionally disables interrupts, and
679 *  halts/stops the CPU.
680 */
681
682#define _CPU_Fatal_halt( _error ) \
683  { \
684  }
685
686/* end of Fatal Error manager macros */
687
688/* Bitfield handler macros */
689
690/*
691 *  This routine sets _output to the bit number of the first bit
692 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
693 *  This type may be either 16 or 32 bits wide although only the 16
694 *  least significant bits will be used.
695 *
696 *  There are a number of variables in using a "find first bit" type
697 *  instruction.
698 *
699 *    (1) What happens when run on a value of zero?
700 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
701 *    (3) The numbering may be zero or one based.
702 *    (4) The "find first bit" instruction may search from MSB or LSB.
703 *
704 *  RTEMS guarantees that (1) will never happen so it is not a concern.
705 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
706 *  _CPU_Priority_bits_index().  These three form a set of routines
707 *  which must logically operate together.  Bits in the _value are
708 *  set and cleared based on masks built by _CPU_Priority_mask().
709 *  The basic major and minor values calculated by _Priority_Major()
710 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
711 *  to properly range between the values returned by the "find first bit"
712 *  instruction.  This makes it possible for _Priority_Get_highest() to
713 *  calculate the major and directly index into the minor table.
714 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
715 *  is the first bit found.
716 *
717 *  This entire "find first bit" and mapping process depends heavily
718 *  on the manner in which a priority is broken into a major and minor
719 *  components with the major being the 4 MSB of a priority and minor
720 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
721 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
722 *  to the lowest priority.
723 *
724 *  If your CPU does not have a "find first bit" instruction, then
725 *  there are ways to make do without it.  Here are a handful of ways
726 *  to implement this in software:
727 *
728 *    - a series of 16 bit test instructions
729 *    - a "binary search using if's"
730 *    - _number = 0
731 *      if _value > 0x00ff
732 *        _value >>=8
733 *        _number = 8;
734 *
735 *      if _value > 0x0000f
736 *        _value >=8
737 *        _number += 4
738 *
739 *      _number += bit_set_table[ _value ]
740 *
741 *    where bit_set_table[ 16 ] has values which indicate the first
742 *      bit set
743 */
744
745#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
746#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
747
748#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
749
750#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
751  { \
752    (_output) = 0;   /* do something to prevent warnings */ \
753  }
754
755#endif
756
757/* end of Bitfield handler macros */
758
759/*
760 *  This routine builds the mask which corresponds to the bit fields
761 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
762 *  for that routine.
763 */
764
765#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
766
767#define _CPU_Priority_Mask( _bit_number ) \
768  ( 1 << (_bit_number) )
769
770#endif
771
772/*
773 *  This routine translates the bit numbers returned by
774 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
775 *  a major or minor component of a priority.  See the discussion
776 *  for that routine.
777 */
778
779#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
780
781#define _CPU_Priority_bits_index( _priority ) \
782  (_priority)
783
784#endif
785
786/* end of Priority handler macros */
787
788/* functions */
789
790/*
791 *  _CPU_Initialize
792 *
793 *  This routine performs CPU dependent initialization.
794 */
795
796void _CPU_Initialize(
797  rtems_cpu_table  *cpu_table,
798  void      (*thread_dispatch)
799);
800
801typedef enum {
802  ARM_EXCEPTION_RESET      = 0,
803  ARM_EXCEPTION_UNDEF      = 1,
804  ARM_EXCEPTION_SWI        = 2,
805  ARM_EXCEPTION_PREF_ABORT = 3,
806  ARM_EXCEPTION_DATA_ABORT = 4,
807  ARM_EXCEPTION_RESERVED   = 5,
808  ARM_EXCEPTION_IRQ        = 6,
809  ARM_EXCEPTION_FIQ        = 7,
810  MAX_EXCEPTIONS           = 8
811} Arm_symbolic_exception_name;
812
813/*
814 *  _CPU_ISR_install_vector
815 *
816 *  This routine installs an interrupt vector.
817 */
818
819void _CPU_ISR_install_vector(
820  unsigned32  vector,
821  proc_ptr    new_handler,
822  proc_ptr   *old_handler
823);
824
825/*
826 *  _CPU_Install_interrupt_stack
827 *
828 *  This routine installs the hardware interrupt stack pointer.
829 *
830 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
831 *         is TRUE.
832 */
833
834void _CPU_Install_interrupt_stack( void );
835
836/*
837 *  _CPU_Thread_Idle_body
838 *
839 *  This routine is the CPU dependent IDLE thread body.
840 *
841 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
842 *         is TRUE.
843 */
844
845void _CPU_Thread_Idle_body( void );
846
847/*
848 *  _CPU_Context_switch
849 *
850 *  This routine switches from the run context to the heir context.
851 */
852
853void _CPU_Context_switch(
854  Context_Control  *run,
855  Context_Control  *heir
856);
857
858/*
859 *  _CPU_Context_restore
860 *
861 *  This routine is generally used only to restart self in an
862 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
863 *
864 *  NOTE: May be unnecessary to reload some registers.
865 */
866
867void _CPU_Context_restore(
868  Context_Control *new_context
869);
870
871/*
872 *  _CPU_Context_save_fp
873 *
874 *  This routine saves the floating point context passed to it.
875 */
876
877void _CPU_Context_save_fp(
878  void **fp_context_ptr
879);
880
881/*
882 *  _CPU_Context_restore_fp
883 *
884 *  This routine restores the floating point context passed to it.
885 */
886
887void _CPU_Context_restore_fp(
888  void **fp_context_ptr
889);
890
891/*  The following routine swaps the endian format of an unsigned int.
892 *  It must be static because it is referenced indirectly.
893 *
894 *  This version will work on any processor, but if there is a better
895 *  way for your CPU PLEASE use it.  The most common way to do this is to:
896 *
897 *     swap least significant two bytes with 16-bit rotate
898 *     swap upper and lower 16-bits
899 *     swap most significant two bytes with 16-bit rotate
900 *
901 *  Some CPUs have special instructions which swap a 32-bit quantity in
902 *  a single instruction (e.g. i486).  It is probably best to avoid
903 *  an "endian swapping control bit" in the CPU.  One good reason is
904 *  that interrupts would probably have to be disabled to insure that
905 *  an interrupt does not try to access the same "chunk" with the wrong
906 *  endian.  Another good reason is that on some CPUs, the endian bit
907 *  endianness for ALL fetches -- both code and data -- so the code
908 *  will be fetched incorrectly.
909 */
910 
911static inline unsigned int CPU_swap_u32(
912  unsigned int value
913)
914{
915  unsigned32 byte1, byte2, byte3, byte4, swapped;
916 
917  byte4 = (value >> 24) & 0xff;
918  byte3 = (value >> 16) & 0xff;
919  byte2 = (value >> 8)  & 0xff;
920  byte1 =  value        & 0xff;
921 
922  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
923  return( swapped );
924}
925
926#define CPU_swap_u16( value ) \
927  (((value&0xff) << 8) | ((value >> 8)&0xff))
928
929#ifdef __cplusplus
930}
931#endif
932
933#endif
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