[7908ba5b] | 1 | /* cpu.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the AMD 29K |
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| 4 | * processor. |
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| 5 | * |
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| 6 | * Author: Craig Lebakken <craigl@transition.com> |
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| 7 | * |
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| 8 | * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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| 9 | * |
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| 10 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 11 | * without any express or implied warranty: |
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| 12 | * permission to use, copy, modify, and distribute this file |
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| 13 | * for any purpose is hereby granted without fee, provided that |
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| 14 | * the above copyright notice and this notice appears in all |
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| 15 | * copies, and that the name of Transition Networks not be used in |
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| 16 | * advertising or publicity pertaining to distribution of the |
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| 17 | * software without specific, written prior permission. |
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| 18 | * Transition Networks makes no representations about the suitability |
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| 19 | * of this software for any purpose. |
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| 20 | * |
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| 21 | * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.c: |
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| 22 | * |
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[08311cc3] | 23 | * COPYRIGHT (c) 1989-1999. |
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[7908ba5b] | 24 | * On-Line Applications Research Corporation (OAR). |
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| 25 | * |
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| 26 | * The license and distribution terms for this file may be |
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| 27 | * found in the file LICENSE in this distribution or at |
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| 28 | * http://www.OARcorp.com/rtems/license.html. |
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| 29 | * |
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| 30 | * $Id$ |
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| 31 | */ |
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| 32 | /* @(#)cpu.h 10/21/96 1.11 */ |
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| 33 | |
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| 34 | #ifndef __CPU_h |
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| 35 | #define __CPU_h |
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| 36 | |
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| 37 | #ifdef __cplusplus |
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| 38 | extern "C" { |
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| 39 | #endif |
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| 40 | |
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| 41 | #include <rtems/score/a29k.h> /* pick up machine definitions */ |
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| 42 | #ifndef ASM |
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| 43 | #include <rtems/score/a29ktypes.h> |
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| 44 | #endif |
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| 45 | |
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| 46 | extern unsigned int a29k_disable( void ); |
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| 47 | extern void a29k_enable( unsigned int cookie ); |
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| 48 | extern unsigned int a29k_getops( void ); |
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| 49 | extern void a29k_getops_sup( void ); |
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| 50 | extern void a29k_disable_sup( void ); |
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| 51 | extern void a29k_enable_sup( void ); |
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| 52 | extern void a29k_disable_all( void ); |
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| 53 | extern void a29k_disable_all_sup( void ); |
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| 54 | extern void a29k_enable_all( void ); |
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| 55 | extern void a29k_enable_all_sup( void ); |
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| 56 | extern void a29k_halt( void ); |
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| 57 | extern void a29k_fatal_error( unsigned32 error ); |
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| 58 | extern void a29k_as70( void ); |
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| 59 | extern void a29k_super_mode( void ); |
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| 60 | extern void a29k_context_switch_sup(void); |
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| 61 | extern void a29k_context_restore_sup(void); |
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| 62 | extern void a29k_context_save_sup(void); |
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| 63 | extern void a29k_sigdfl_sup(void); |
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| 64 | |
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| 65 | /* conditional compilation parameters */ |
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| 66 | |
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| 67 | /* |
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| 68 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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| 69 | * |
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| 70 | * If TRUE, then they are inlined. |
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| 71 | * If FALSE, then a subroutine call is made. |
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| 72 | * |
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| 73 | * Basically this is an example of the classic trade-off of size |
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| 74 | * versus speed. Inlining the call (TRUE) typically increases the |
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| 75 | * size of RTEMS while speeding up the enabling of dispatching. |
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| 76 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
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| 77 | * only be 0 or 1 unless you are in an interrupt handler and that |
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| 78 | * interrupt handler invokes the executive.] When not inlined |
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| 79 | * something calls _Thread_Enable_dispatch which in turns calls |
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| 80 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
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| 81 | * one subroutine call is avoided entirely.] |
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| 82 | */ |
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| 83 | |
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| 84 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 85 | |
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| 86 | /* |
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| 87 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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| 88 | * be unrolled one time? In unrolled each iteration of the loop examines |
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| 89 | * two "nodes" on the chain being searched. Otherwise, only one node |
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| 90 | * is examined per iteration. |
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| 91 | * |
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| 92 | * If TRUE, then the loops are unrolled. |
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| 93 | * If FALSE, then the loops are not unrolled. |
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| 94 | * |
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| 95 | * The primary factor in making this decision is the cost of disabling |
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| 96 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
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| 97 | * body of the loop. On some CPUs, the flash is more expensive than |
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| 98 | * one iteration of the loop body. In this case, it might be desirable |
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| 99 | * to unroll the loop. It is important to note that on some CPUs, this |
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| 100 | * code is the longest interrupt disable period in RTEMS. So it is |
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| 101 | * necessary to strike a balance when setting this parameter. |
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| 102 | */ |
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| 103 | |
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| 104 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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| 105 | |
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| 106 | /* |
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| 107 | * Does RTEMS manage a dedicated interrupt stack in software? |
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| 108 | * |
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[8bc62aeb] | 109 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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[7908ba5b] | 110 | * If FALSE, nothing is done. |
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| 111 | * |
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| 112 | * If the CPU supports a dedicated interrupt stack in hardware, |
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| 113 | * then it is generally the responsibility of the BSP to allocate it |
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| 114 | * and set it up. |
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| 115 | * |
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| 116 | * If the CPU does not support a dedicated interrupt stack, then |
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| 117 | * the porter has two options: (1) execute interrupts on the |
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| 118 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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| 119 | * interrupt stack. |
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| 120 | * |
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| 121 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 122 | * |
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| 123 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 124 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 125 | * possible that both are FALSE for a particular CPU. Although it |
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| 126 | * is unclear what that would imply about the interrupt processing |
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| 127 | * procedure on that CPU. |
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| 128 | */ |
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| 129 | |
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| 130 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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| 131 | |
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| 132 | /* |
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| 133 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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| 134 | * |
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| 135 | * If TRUE, then it must be installed during initialization. |
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| 136 | * If FALSE, then no installation is performed. |
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| 137 | * |
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| 138 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 139 | * |
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| 140 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 141 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 142 | * possible that both are FALSE for a particular CPU. Although it |
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| 143 | * is unclear what that would imply about the interrupt processing |
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| 144 | * procedure on that CPU. |
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| 145 | */ |
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| 146 | |
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| 147 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 148 | |
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| 149 | /* |
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| 150 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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| 151 | * |
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| 152 | * If TRUE, then the memory is allocated during initialization. |
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| 153 | * If FALSE, then the memory is allocated during initialization. |
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| 154 | * |
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| 155 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE |
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| 156 | * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. |
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| 157 | */ |
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| 158 | |
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| 159 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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| 160 | |
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| 161 | /* |
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| 162 | * Does the RTEMS invoke the user's ISR with the vector number and |
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| 163 | * a pointer to the saved interrupt frame (1) or just the vector |
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| 164 | * number (0)? |
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| 165 | */ |
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| 166 | |
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| 167 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 168 | |
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| 169 | /* |
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| 170 | * Does the CPU have hardware floating point? |
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| 171 | * |
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| 172 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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| 173 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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| 174 | * |
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| 175 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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| 176 | * the answer is TRUE. |
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| 177 | * |
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| 178 | * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. |
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| 179 | * It indicates whether or not this CPU model has FP support. For |
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| 180 | * example, it would be possible to have an i386_nofp CPU model |
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| 181 | * which set this to false to indicate that you have an i386 without |
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| 182 | * an i387 and wish to leave floating point support out of RTEMS. |
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| 183 | */ |
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| 184 | |
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| 185 | #if ( A29K_HAS_FPU == 1 ) |
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| 186 | #define CPU_HARDWARE_FP TRUE |
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| 187 | #else |
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| 188 | #define CPU_HARDWARE_FP FALSE |
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| 189 | #endif |
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[17508d02] | 190 | #define CPU_SOFTWARE_FP FALSE |
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[7908ba5b] | 191 | |
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| 192 | /* |
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| 193 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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| 194 | * |
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| 195 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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| 196 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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| 197 | * |
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| 198 | * So far, the only CPU in which this option has been used is the |
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| 199 | * HP PA-RISC. The HP C compiler and gcc both implicitly use the |
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| 200 | * floating point registers to perform integer multiplies. If |
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| 201 | * a function which you would not think utilize the FP unit DOES, |
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| 202 | * then one can not easily predict which tasks will use the FP hardware. |
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| 203 | * In this case, this option should be TRUE. |
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| 204 | * |
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| 205 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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| 206 | */ |
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| 207 | |
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| 208 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 209 | |
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| 210 | /* |
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| 211 | * Should the IDLE task have a floating point context? |
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| 212 | * |
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| 213 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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| 214 | * and it has a floating point context which is switched in and out. |
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| 215 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 216 | * |
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| 217 | * Setting this to TRUE negatively impacts the time required to preempt |
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| 218 | * the IDLE task from an interrupt because the floating point context |
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| 219 | * must be saved as part of the preemption. |
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| 220 | */ |
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| 221 | |
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| 222 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 223 | |
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| 224 | /* |
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| 225 | * Should the saving of the floating point registers be deferred |
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| 226 | * until a context switch is made to another different floating point |
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| 227 | * task? |
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| 228 | * |
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| 229 | * If TRUE, then the floating point context will not be stored until |
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| 230 | * necessary. It will remain in the floating point registers and not |
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| 231 | * disturned until another floating point task is switched to. |
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| 232 | * |
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| 233 | * If FALSE, then the floating point context is saved when a floating |
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| 234 | * point task is switched out and restored when the next floating point |
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| 235 | * task is restored. The state of the floating point registers between |
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| 236 | * those two operations is not specified. |
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| 237 | * |
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| 238 | * If the floating point context does NOT have to be saved as part of |
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| 239 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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| 240 | * |
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| 241 | * Setting this flag to TRUE results in using a different algorithm |
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| 242 | * for deciding when to save and restore the floating point context. |
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| 243 | * The deferred FP switch algorithm minimizes the number of times |
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| 244 | * the FP context is saved and restored. The FP context is not saved |
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| 245 | * until a context switch is made to another, different FP task. |
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| 246 | * Thus in a system with only one FP task, the FP context will never |
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| 247 | * be saved or restored. |
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| 248 | */ |
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| 249 | |
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| 250 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 251 | |
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| 252 | /* |
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| 253 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 254 | * |
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| 255 | * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body |
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| 256 | * must be provided and is the default IDLE thread body instead of |
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| 257 | * _Internal_threads_Idle_thread_body. |
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| 258 | * |
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| 259 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 260 | * not provide one. |
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| 261 | * |
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| 262 | * This is intended to allow for supporting processors which have |
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| 263 | * a low power or idle mode. When the IDLE thread is executed, then |
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| 264 | * the CPU can be powered down. |
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| 265 | * |
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| 266 | * The order of precedence for selecting the IDLE thread body is: |
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| 267 | * |
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| 268 | * 1. BSP provided |
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| 269 | * 2. CPU dependent (if provided) |
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| 270 | * 3. generic (if no BSP and no CPU dependent) |
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| 271 | */ |
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| 272 | |
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| 273 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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| 274 | |
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| 275 | /* |
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| 276 | * Does the stack grow up (toward higher addresses) or down |
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| 277 | * (toward lower addresses)? |
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| 278 | * |
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| 279 | * If TRUE, then the grows upward. |
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| 280 | * If FALSE, then the grows toward smaller addresses. |
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| 281 | */ |
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| 282 | |
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| 283 | #define CPU_STACK_GROWS_UP FALSE |
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| 284 | |
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| 285 | /* |
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| 286 | * The following is the variable attribute used to force alignment |
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| 287 | * of critical RTEMS structures. On some processors it may make |
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| 288 | * sense to have these aligned on tighter boundaries than |
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| 289 | * the minimum requirements of the compiler in order to have as |
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| 290 | * much of the critical data area as possible in a cache line. |
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| 291 | * |
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| 292 | * The placement of this macro in the declaration of the variables |
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| 293 | * is based on the syntactically requirements of the GNU C |
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| 294 | * "__attribute__" extension. For example with GNU C, use |
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| 295 | * the following to force a structures to a 32 byte boundary. |
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| 296 | * |
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| 297 | * __attribute__ ((aligned (32))) |
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| 298 | * |
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| 299 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
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| 300 | * To benefit from using this, the data must be heavily |
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| 301 | * used so it will stay in the cache and used frequently enough |
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| 302 | * in the executive to justify turning this on. |
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| 303 | */ |
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| 304 | |
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| 305 | #define CPU_STRUCTURE_ALIGNMENT |
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| 306 | |
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| 307 | /* |
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| 308 | * Define what is required to specify how the network to host conversion |
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| 309 | * routines are handled. |
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| 310 | * |
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| 311 | */ |
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| 312 | |
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[bbfdedd] | 313 | /* #warning "Check these definitions!!!" */ |
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[7908ba5b] | 314 | |
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[6805640e] | 315 | #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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[7908ba5b] | 316 | #define CPU_BIG_ENDIAN TRUE |
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| 317 | #define CPU_LITTLE_ENDIAN FALSE |
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| 318 | |
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| 319 | /* |
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| 320 | * The following defines the number of bits actually used in the |
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| 321 | * interrupt field of the task mode. How those bits map to the |
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| 322 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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| 323 | */ |
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| 324 | |
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| 325 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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| 326 | |
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| 327 | /* |
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| 328 | * Processor defined structures |
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| 329 | * |
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| 330 | * Examples structures include the descriptor tables from the i386 |
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| 331 | * and the processor control structure on the i960ca. |
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| 332 | */ |
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| 333 | |
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| 334 | /* may need to put some structures here. */ |
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| 335 | |
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| 336 | /* |
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| 337 | * Contexts |
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| 338 | * |
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| 339 | * Generally there are 2 types of context to save. |
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| 340 | * 1. Interrupt registers to save |
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| 341 | * 2. Task level registers to save |
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| 342 | * |
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| 343 | * This means we have the following 3 context items: |
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| 344 | * 1. task level context stuff:: Context_Control |
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| 345 | * 2. floating point task stuff:: Context_Control_fp |
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| 346 | * 3. special interrupt level context :: Context_Control_interrupt |
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| 347 | * |
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| 348 | * On some processors, it is cost-effective to save only the callee |
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| 349 | * preserved registers during a task context switch. This means |
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| 350 | * that the ISR code needs to save those registers which do not |
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| 351 | * persist across function calls. It is not mandatory to make this |
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| 352 | * distinctions between the caller/callee saves registers for the |
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| 353 | * purpose of minimizing context saved during task switch and on interrupts. |
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| 354 | * If the cost of saving extra registers is minimal, simplicity is the |
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| 355 | * choice. Save the same context on interrupt entry as for tasks in |
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| 356 | * this case. |
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| 357 | * |
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| 358 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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| 359 | * care should be used in designing the context area. |
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| 360 | * |
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| 361 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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| 362 | * structure will not be used or it simply consist of an array of a |
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| 363 | * fixed number of bytes. This is done when the floating point context |
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| 364 | * is dumped by a "FP save context" type instruction and the format |
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| 365 | * is not really defined by the CPU. In this case, there is no need |
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| 366 | * to figure out the exact format -- only the size. Of course, although |
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| 367 | * this is enough information for RTEMS, it is probably not enough for |
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| 368 | * a debugger such as gdb. But that is another problem. |
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| 369 | */ |
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| 370 | |
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| 371 | typedef struct { |
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| 372 | unsigned32 signal; |
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| 373 | unsigned32 gr1; |
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| 374 | unsigned32 rab; |
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| 375 | unsigned32 PC0; |
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| 376 | unsigned32 PC1; |
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| 377 | unsigned32 PC2; |
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| 378 | unsigned32 CHA; |
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| 379 | unsigned32 CHD; |
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| 380 | unsigned32 CHC; |
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| 381 | unsigned32 ALU; |
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| 382 | unsigned32 OPS; |
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| 383 | unsigned32 tav; |
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| 384 | unsigned32 lr1; |
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| 385 | unsigned32 rfb; |
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| 386 | unsigned32 msp; |
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| 387 | |
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| 388 | unsigned32 FPStat0; |
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| 389 | unsigned32 FPStat1; |
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| 390 | unsigned32 FPStat2; |
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| 391 | unsigned32 IPA; |
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| 392 | unsigned32 IPB; |
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| 393 | unsigned32 IPC; |
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| 394 | unsigned32 Q; |
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| 395 | |
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| 396 | unsigned32 gr96; |
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| 397 | unsigned32 gr97; |
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| 398 | unsigned32 gr98; |
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| 399 | unsigned32 gr99; |
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| 400 | unsigned32 gr100; |
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| 401 | unsigned32 gr101; |
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| 402 | unsigned32 gr102; |
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| 403 | unsigned32 gr103; |
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| 404 | unsigned32 gr104; |
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| 405 | unsigned32 gr105; |
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| 406 | unsigned32 gr106; |
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| 407 | unsigned32 gr107; |
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| 408 | unsigned32 gr108; |
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| 409 | unsigned32 gr109; |
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| 410 | unsigned32 gr110; |
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| 411 | unsigned32 gr111; |
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| 412 | |
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| 413 | unsigned32 gr112; |
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| 414 | unsigned32 gr113; |
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| 415 | unsigned32 gr114; |
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| 416 | unsigned32 gr115; |
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| 417 | |
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| 418 | unsigned32 gr116; |
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| 419 | unsigned32 gr117; |
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| 420 | unsigned32 gr118; |
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| 421 | unsigned32 gr119; |
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| 422 | unsigned32 gr120; |
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| 423 | unsigned32 gr121; |
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| 424 | unsigned32 gr122; |
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| 425 | unsigned32 gr123; |
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| 426 | unsigned32 gr124; |
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| 427 | |
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| 428 | unsigned32 local_count; |
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| 429 | |
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| 430 | unsigned32 locals[128]; |
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| 431 | } Context_Control; |
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| 432 | |
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| 433 | typedef struct { |
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| 434 | double some_float_register; |
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| 435 | } Context_Control_fp; |
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| 436 | |
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| 437 | typedef struct { |
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| 438 | unsigned32 special_interrupt_register; |
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| 439 | } CPU_Interrupt_frame; |
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| 440 | |
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| 441 | |
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| 442 | /* |
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| 443 | * The following table contains the information required to configure |
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| 444 | * the XXX processor specific parameters. |
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| 445 | * |
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| 446 | * NOTE: The interrupt_stack_size field is required if |
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| 447 | * CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE. |
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| 448 | * |
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| 449 | * The pretasking_hook, predriver_hook, and postdriver_hook, |
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| 450 | * and the do_zero_of_workspace fields are required on ALL CPUs. |
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| 451 | */ |
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| 452 | |
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| 453 | typedef struct { |
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| 454 | void (*pretasking_hook)( void ); |
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| 455 | void (*predriver_hook)( void ); |
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| 456 | void (*postdriver_hook)( void ); |
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| 457 | void (*idle_task)( void ); |
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| 458 | boolean do_zero_of_workspace; |
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| 459 | unsigned32 idle_task_stack_size; |
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| 460 | unsigned32 interrupt_stack_size; |
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[bbfdedd] | 461 | unsigned32 extra_mpci_receive_server_stack; |
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| 462 | void * (*stack_allocate_hook)( unsigned32 ); |
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| 463 | void (*stack_free_hook)( void* ); |
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| 464 | /* end of fields required on all CPUs */ |
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| 465 | |
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[7908ba5b] | 466 | } rtems_cpu_table; |
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| 467 | |
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[458bd34] | 468 | /* |
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| 469 | * Macros to access required entires in the CPU Table are in |
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| 470 | * the file rtems/system.h. |
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| 471 | */ |
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| 472 | |
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| 473 | /* |
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| 474 | * Macros to access AMD A29K specific additions to the CPU Table |
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| 475 | */ |
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| 476 | |
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| 477 | /* There are no CPU specific additions to the CPU Table for this port. */ |
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| 478 | |
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[7908ba5b] | 479 | /* |
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| 480 | * This variable is optional. It is used on CPUs on which it is difficult |
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| 481 | * to generate an "uninitialized" FP context. It is filled in by |
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| 482 | * _CPU_Initialize and copied into the task's FP context area during |
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| 483 | * _CPU_Context_Initialize. |
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| 484 | */ |
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| 485 | |
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[d1c83050] | 486 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
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[7908ba5b] | 487 | |
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| 488 | /* |
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| 489 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
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| 490 | * This stack is allocated by the Interrupt Manager and the switch |
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| 491 | * is performed in _ISR_Handler. These variables contain pointers |
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| 492 | * to the lowest and highest addresses in the chunk of memory allocated |
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| 493 | * for the interrupt stack. Since it is unknown whether the stack |
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| 494 | * grows up or down (in general), this give the CPU dependent |
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| 495 | * code the option of picking the version it wants to use. |
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| 496 | * |
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| 497 | * NOTE: These two variables are required if the macro |
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| 498 | * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
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| 499 | */ |
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| 500 | |
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[d1c83050] | 501 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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| 502 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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[7908ba5b] | 503 | |
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| 504 | /* |
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| 505 | * With some compilation systems, it is difficult if not impossible to |
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| 506 | * call a high-level language routine from assembly language. This |
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| 507 | * is especially true of commercial Ada compilers and name mangling |
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| 508 | * C++ ones. This variable can be optionally defined by the CPU porter |
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| 509 | * and contains the address of the routine _Thread_Dispatch. This |
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| 510 | * can make it easier to invoke that routine at the end of the interrupt |
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| 511 | * sequence (if a dispatch is necessary). |
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| 512 | */ |
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| 513 | |
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[d1c83050] | 514 | SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); |
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[7908ba5b] | 515 | |
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| 516 | /* |
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| 517 | * Nothing prevents the porter from declaring more CPU specific variables. |
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| 518 | */ |
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| 519 | |
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| 520 | /* XXX: if needed, put more variables here */ |
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| 521 | |
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| 522 | /* |
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| 523 | * The size of the floating point context area. On some CPUs this |
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| 524 | * will not be a "sizeof" because the format of the floating point |
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| 525 | * area is not defined -- only the size is. This is usually on |
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| 526 | * CPUs with a "floating point save context" instruction. |
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| 527 | */ |
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| 528 | |
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| 529 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 530 | |
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| 531 | /* |
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| 532 | * Amount of extra stack (above minimum stack size) required by |
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| 533 | * system initialization thread. Remember that in a multiprocessor |
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| 534 | * system the system intialization thread becomes the MP server thread. |
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| 535 | */ |
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| 536 | |
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| 537 | #define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0 |
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| 538 | |
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| 539 | /* |
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| 540 | * This defines the number of entries in the ISR_Vector_table managed |
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| 541 | * by RTEMS. |
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| 542 | */ |
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| 543 | |
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| 544 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
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| 545 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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| 546 | |
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| 547 | /* |
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| 548 | * Should be large enough to run all RTEMS tests. This insures |
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| 549 | * that a "reasonable" small application should not have any problems. |
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| 550 | */ |
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| 551 | |
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| 552 | #define CPU_STACK_MINIMUM_SIZE (8192) |
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| 553 | |
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| 554 | /* |
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| 555 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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| 556 | * alignment does not take into account the requirements for the stack. |
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| 557 | */ |
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| 558 | |
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| 559 | #define CPU_ALIGNMENT 4 |
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| 560 | |
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| 561 | /* |
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| 562 | * This number corresponds to the byte alignment requirement for the |
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| 563 | * heap handler. This alignment requirement may be stricter than that |
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| 564 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
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| 565 | * common for the heap to follow the same alignment requirement as |
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| 566 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
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| 567 | * then this should be set to CPU_ALIGNMENT. |
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| 568 | * |
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| 569 | * NOTE: This does not have to be a power of 2. It does have to |
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| 570 | * be greater or equal to than CPU_ALIGNMENT. |
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| 571 | */ |
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| 572 | |
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| 573 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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| 574 | |
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| 575 | /* |
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| 576 | * This number corresponds to the byte alignment requirement for memory |
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| 577 | * buffers allocated by the partition manager. This alignment requirement |
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| 578 | * may be stricter than that for the data types alignment specified by |
---|
| 579 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
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| 580 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
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| 581 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
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| 582 | * |
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| 583 | * NOTE: This does not have to be a power of 2. It does have to |
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| 584 | * be greater or equal to than CPU_ALIGNMENT. |
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| 585 | */ |
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| 586 | |
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| 587 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 588 | |
---|
| 589 | /* |
---|
| 590 | * This number corresponds to the byte alignment requirement for the |
---|
| 591 | * stack. This alignment requirement may be stricter than that for the |
---|
| 592 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 593 | * is strict enough for the stack, then this should be set to 0. |
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| 594 | * |
---|
| 595 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
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| 596 | */ |
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| 597 | |
---|
| 598 | #define CPU_STACK_ALIGNMENT 0 |
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| 599 | |
---|
| 600 | /* ISR handler macros */ |
---|
| 601 | |
---|
| 602 | /* |
---|
| 603 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 604 | * level is returned in _level. |
---|
| 605 | */ |
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| 606 | |
---|
| 607 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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| 608 | do{ _isr_cookie = a29k_disable(); }while(0) |
---|
| 609 | |
---|
| 610 | /* |
---|
| 611 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 612 | * This indicates the end of an RTEMS critical section. The parameter |
---|
| 613 | * _level is not modified. |
---|
| 614 | */ |
---|
| 615 | |
---|
| 616 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
---|
| 617 | do{ a29k_enable(_isr_cookie) ; }while(0) |
---|
| 618 | |
---|
| 619 | /* |
---|
| 620 | * This temporarily restores the interrupt to _level before immediately |
---|
| 621 | * disabling them again. This is used to divide long RTEMS critical |
---|
| 622 | * sections into two or more parts. The parameter _level is not |
---|
| 623 | * modified. |
---|
| 624 | */ |
---|
| 625 | |
---|
| 626 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
---|
| 627 | do{ \ |
---|
| 628 | _CPU_ISR_Enable( _isr_cookie ); \ |
---|
| 629 | _CPU_ISR_Disable( _isr_cookie ); \ |
---|
| 630 | }while(0) |
---|
| 631 | |
---|
| 632 | /* |
---|
| 633 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
| 634 | * actually provides. Currently, interrupt levels which do not |
---|
| 635 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
| 636 | * it would be nice if these were "mapped" by the application |
---|
| 637 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
| 638 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
| 639 | * This could be used to manage a programmable interrupt controller |
---|
| 640 | * via the rtems_task_mode directive. |
---|
| 641 | */ |
---|
| 642 | |
---|
| 643 | #define _CPU_ISR_Set_level( new_level ) \ |
---|
| 644 | do{ \ |
---|
| 645 | if ( new_level ) a29k_disable_all(); \ |
---|
| 646 | else a29k_enable_all(); \ |
---|
| 647 | }while(0); |
---|
| 648 | |
---|
| 649 | /* end of ISR handler macros */ |
---|
| 650 | |
---|
| 651 | /* Context handler macros */ |
---|
| 652 | |
---|
| 653 | extern void _CPU_Context_save( |
---|
| 654 | Context_Control *new_context |
---|
| 655 | ); |
---|
| 656 | |
---|
| 657 | /* |
---|
| 658 | * Initialize the context to a state suitable for starting a |
---|
| 659 | * task after a context restore operation. Generally, this |
---|
| 660 | * involves: |
---|
| 661 | * |
---|
| 662 | * - setting a starting address |
---|
| 663 | * - preparing the stack |
---|
| 664 | * - preparing the stack and frame pointers |
---|
| 665 | * - setting the proper interrupt level in the context |
---|
| 666 | * - initializing the floating point context |
---|
| 667 | * |
---|
| 668 | * This routine generally does not set any unnecessary register |
---|
| 669 | * in the context. The state of the "general data" registers is |
---|
| 670 | * undefined at task start time. |
---|
| 671 | * |
---|
| 672 | * NOTE: This is_fp parameter is TRUE if the thread is to be a floating |
---|
| 673 | * point thread. This is typically only used on CPUs where the |
---|
| 674 | * FPU may be easily disabled by software such as on the SPARC |
---|
| 675 | * where the PSR contains an enable FPU bit. |
---|
| 676 | */ |
---|
| 677 | |
---|
| 678 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
---|
| 679 | _isr, _entry_point, _is_fp ) \ |
---|
| 680 | do{ /* allocate 1/4 of stack for memory stack, 3/4 of stack for register stack */ \ |
---|
| 681 | unsigned32 _mem_stack_tmp = (unsigned32)(_stack_base) + (_size); \ |
---|
| 682 | unsigned32 _reg_stack_tmp = (unsigned32)(_stack_base) + (((_size)*3)/4); \ |
---|
| 683 | _mem_stack_tmp &= ~(CPU_ALIGNMENT-1); \ |
---|
| 684 | _reg_stack_tmp &= ~(CPU_ALIGNMENT-1); \ |
---|
| 685 | _CPU_Context_save(_the_context); \ |
---|
| 686 | (_the_context)->msp = _mem_stack_tmp; /* gr125 */ \ |
---|
| 687 | (_the_context)->lr1 = \ |
---|
| 688 | (_the_context)->locals[1] = \ |
---|
| 689 | (_the_context)->rfb = _reg_stack_tmp; /* gr127 */ \ |
---|
| 690 | (_the_context)->gr1 = _reg_stack_tmp - 4 * 4; \ |
---|
| 691 | (_the_context)->rab = _reg_stack_tmp - 128 * 4; /* gr126 */ \ |
---|
| 692 | (_the_context)->local_count = 1-1; \ |
---|
| 693 | (_the_context)->PC1 = _entry_point; \ |
---|
| 694 | (_the_context)->PC0 = (unsigned32)((char *)_entry_point + 4); \ |
---|
| 695 | if (_isr) { (_the_context)->OPS |= (TD | DI); } \ |
---|
| 696 | else \ |
---|
| 697 | { (_the_context)->OPS &= ~(TD | DI); } \ |
---|
| 698 | }while(0) |
---|
| 699 | |
---|
| 700 | /* |
---|
| 701 | * This routine is responsible for somehow restarting the currently |
---|
| 702 | * executing task. If you are lucky, then all that is necessary |
---|
| 703 | * is restoring the context. Otherwise, there will need to be |
---|
| 704 | * a special assembly routine which does something special in this |
---|
| 705 | * case. Context_Restore should work most of the time. It will |
---|
| 706 | * not work if restarting self conflicts with the stack frame |
---|
| 707 | * assumptions of restoring a context. |
---|
| 708 | */ |
---|
| 709 | |
---|
| 710 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 711 | _CPU_Context_restore( (_the_context) ) |
---|
| 712 | |
---|
| 713 | /* |
---|
| 714 | * The purpose of this macro is to allow the initial pointer into |
---|
| 715 | * a floating point context area (used to save the floating point |
---|
| 716 | * context) to be at an arbitrary place in the floating point |
---|
| 717 | * context area. |
---|
| 718 | * |
---|
| 719 | * This is necessary because some FP units are designed to have |
---|
| 720 | * their context saved as a stack which grows into lower addresses. |
---|
| 721 | * Other FP units can be saved by simply moving registers into offsets |
---|
| 722 | * from the base of the context area. Finally some FP units provide |
---|
| 723 | * a "dump context" instruction which could fill in from high to low |
---|
| 724 | * or low to high based on the whim of the CPU designers. |
---|
| 725 | */ |
---|
| 726 | |
---|
| 727 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
| 728 | ( (char *) (_base) + (_offset) ) |
---|
| 729 | |
---|
| 730 | /* |
---|
| 731 | * This routine initializes the FP context area passed to it to. |
---|
| 732 | * There are a few standard ways in which to initialize the |
---|
| 733 | * floating point context. The code included for this macro assumes |
---|
| 734 | * that this is a CPU in which a "initial" FP context was saved into |
---|
| 735 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
| 736 | * context passed to it. |
---|
| 737 | * |
---|
| 738 | * Other models include (1) not doing anything, and (2) putting |
---|
| 739 | * a "null FP status word" in the correct place in the FP context. |
---|
| 740 | */ |
---|
| 741 | |
---|
| 742 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
| 743 | do { \ |
---|
| 744 | *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ |
---|
| 745 | } while(0) |
---|
| 746 | |
---|
| 747 | /* end of Context handler macros */ |
---|
| 748 | |
---|
| 749 | /* Fatal Error manager macros */ |
---|
| 750 | |
---|
| 751 | /* |
---|
| 752 | * This routine copies _error into a known place -- typically a stack |
---|
| 753 | * location or a register, optionally disables interrupts, and |
---|
| 754 | * halts/stops the CPU. |
---|
| 755 | */ |
---|
| 756 | |
---|
| 757 | #define _CPU_Fatal_halt( _error ) \ |
---|
| 758 | a29k_fatal_error(_error) |
---|
| 759 | |
---|
| 760 | /* end of Fatal Error manager macros */ |
---|
| 761 | |
---|
| 762 | /* Bitfield handler macros */ |
---|
| 763 | |
---|
| 764 | /* |
---|
| 765 | * This routine sets _output to the bit number of the first bit |
---|
| 766 | * set in _value. _value is of CPU dependent type Priority_Bit_map_control. |
---|
| 767 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
| 768 | * least significant bits will be used. |
---|
| 769 | * |
---|
| 770 | * There are a number of variables in using a "find first bit" type |
---|
| 771 | * instruction. |
---|
| 772 | * |
---|
| 773 | * (1) What happens when run on a value of zero? |
---|
| 774 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 775 | * (3) The numbering may be zero or one based. |
---|
| 776 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
| 777 | * |
---|
| 778 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
| 779 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
| 780 | * _CPU_Priority_bits_index(). These three form a set of routines |
---|
| 781 | * which must logically operate together. Bits in the _value are |
---|
| 782 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
| 783 | * The basic major and minor values calculated by _Priority_Major() |
---|
| 784 | * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() |
---|
| 785 | * to properly range between the values returned by the "find first bit" |
---|
| 786 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
| 787 | * calculate the major and directly index into the minor table. |
---|
| 788 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 789 | * is the first bit found. |
---|
| 790 | * |
---|
| 791 | * This entire "find first bit" and mapping process depends heavily |
---|
| 792 | * on the manner in which a priority is broken into a major and minor |
---|
| 793 | * components with the major being the 4 MSB of a priority and minor |
---|
| 794 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 795 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 796 | * to the lowest priority. |
---|
| 797 | * |
---|
| 798 | * If your CPU does not have a "find first bit" instruction, then |
---|
| 799 | * there are ways to make do without it. Here are a handful of ways |
---|
| 800 | * to implement this in software: |
---|
| 801 | * |
---|
| 802 | * - a series of 16 bit test instructions |
---|
| 803 | * - a "binary search using if's" |
---|
| 804 | * - _number = 0 |
---|
| 805 | * if _value > 0x00ff |
---|
| 806 | * _value >>=8 |
---|
| 807 | * _number = 8; |
---|
| 808 | * |
---|
| 809 | * if _value > 0x0000f |
---|
| 810 | * _value >=8 |
---|
| 811 | * _number += 4 |
---|
| 812 | * |
---|
| 813 | * _number += bit_set_table[ _value ] |
---|
| 814 | * |
---|
| 815 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
| 816 | * bit set |
---|
| 817 | */ |
---|
| 818 | |
---|
| 819 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
| 820 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
| 821 | |
---|
| 822 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 823 | |
---|
| 824 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 825 | { \ |
---|
| 826 | (_output) = 0; /* do something to prevent warnings */ \ |
---|
| 827 | } |
---|
| 828 | |
---|
| 829 | #endif |
---|
| 830 | |
---|
| 831 | /* end of Bitfield handler macros */ |
---|
| 832 | |
---|
| 833 | /* |
---|
| 834 | * This routine builds the mask which corresponds to the bit fields |
---|
| 835 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
---|
| 836 | * for that routine. |
---|
| 837 | */ |
---|
| 838 | |
---|
| 839 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 840 | |
---|
| 841 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
| 842 | ( 1 << (_bit_number) ) |
---|
| 843 | |
---|
| 844 | #endif |
---|
| 845 | |
---|
| 846 | /* |
---|
| 847 | * This routine translates the bit numbers returned by |
---|
| 848 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
---|
| 849 | * a major or minor component of a priority. See the discussion |
---|
| 850 | * for that routine. |
---|
| 851 | */ |
---|
| 852 | |
---|
| 853 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 854 | |
---|
| 855 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
| 856 | (_priority) |
---|
| 857 | |
---|
| 858 | #endif |
---|
| 859 | |
---|
| 860 | /* end of Priority handler macros */ |
---|
| 861 | |
---|
| 862 | /* functions */ |
---|
| 863 | |
---|
| 864 | /* |
---|
| 865 | * _CPU_Initialize |
---|
| 866 | * |
---|
| 867 | * This routine performs CPU dependent initialization. |
---|
| 868 | */ |
---|
| 869 | |
---|
| 870 | void _CPU_Initialize( |
---|
| 871 | rtems_cpu_table *cpu_table, |
---|
| 872 | void (*thread_dispatch)() |
---|
| 873 | ); |
---|
| 874 | |
---|
| 875 | /* |
---|
| 876 | * _CPU_ISR_install_raw_handler |
---|
| 877 | * |
---|
| 878 | * This routine installs a "raw" interrupt handler directly into the |
---|
| 879 | * processor's vector table. |
---|
| 880 | */ |
---|
| 881 | |
---|
| 882 | void _CPU_ISR_install_raw_handler( |
---|
| 883 | unsigned32 vector, |
---|
| 884 | proc_ptr new_handler, |
---|
| 885 | proc_ptr *old_handler |
---|
| 886 | ); |
---|
| 887 | |
---|
| 888 | /* |
---|
| 889 | * _CPU_ISR_install_vector |
---|
| 890 | * |
---|
| 891 | * This routine installs an interrupt vector. |
---|
| 892 | */ |
---|
| 893 | |
---|
| 894 | void _CPU_ISR_install_vector( |
---|
| 895 | unsigned32 vector, |
---|
| 896 | proc_ptr new_handler, |
---|
| 897 | proc_ptr *old_handler |
---|
| 898 | ); |
---|
| 899 | |
---|
| 900 | /* |
---|
| 901 | * _CPU_Install_interrupt_stack |
---|
| 902 | * |
---|
| 903 | * This routine installs the hardware interrupt stack pointer. |
---|
| 904 | * |
---|
| 905 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
| 906 | * is TRUE. |
---|
| 907 | */ |
---|
| 908 | |
---|
| 909 | void _CPU_Install_interrupt_stack( void ); |
---|
| 910 | |
---|
| 911 | /* |
---|
[bbfdedd] | 912 | * _CPU_Thread_Idle_body |
---|
[7908ba5b] | 913 | * |
---|
| 914 | * This routine is the CPU dependent IDLE thread body. |
---|
| 915 | * |
---|
| 916 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
---|
| 917 | * is TRUE. |
---|
| 918 | */ |
---|
| 919 | |
---|
[bbfdedd] | 920 | void _CPU_Thread_Idle_body( void ); |
---|
[7908ba5b] | 921 | |
---|
| 922 | /* |
---|
| 923 | * _CPU_Context_switch |
---|
| 924 | * |
---|
| 925 | * This routine switches from the run context to the heir context. |
---|
| 926 | */ |
---|
| 927 | |
---|
| 928 | void _CPU_Context_switch( |
---|
| 929 | Context_Control *run, |
---|
| 930 | Context_Control *heir |
---|
| 931 | ); |
---|
| 932 | |
---|
| 933 | /* |
---|
| 934 | * _CPU_Context_restore |
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| 935 | * |
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| 936 | * This routine is generally used only to restart self in an |
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| 937 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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| 938 | * |
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| 939 | * NOTE: May be unnecessary to reload some registers. |
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| 940 | */ |
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| 941 | |
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| 942 | void _CPU_Context_restore( |
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| 943 | Context_Control *new_context |
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| 944 | ); |
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| 945 | |
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| 946 | /* |
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| 947 | * _CPU_Context_save_fp |
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| 948 | * |
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| 949 | * This routine saves the floating point context passed to it. |
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| 950 | */ |
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| 951 | |
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| 952 | void _CPU_Context_save_fp( |
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| 953 | void **fp_context_ptr |
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| 954 | ); |
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| 955 | |
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| 956 | /* |
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| 957 | * _CPU_Context_restore_fp |
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| 958 | * |
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| 959 | * This routine restores the floating point context passed to it. |
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| 960 | */ |
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| 961 | |
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| 962 | void _CPU_Context_restore_fp( |
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| 963 | void **fp_context_ptr |
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| 964 | ); |
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| 965 | |
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| 966 | /* The following routine swaps the endian format of an unsigned int. |
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| 967 | * It must be static because it is referenced indirectly. |
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| 968 | * |
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| 969 | * This version will work on any processor, but if there is a better |
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| 970 | * way for your CPU PLEASE use it. The most common way to do this is to: |
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| 971 | * |
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| 972 | * swap least significant two bytes with 16-bit rotate |
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| 973 | * swap upper and lower 16-bits |
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| 974 | * swap most significant two bytes with 16-bit rotate |
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| 975 | * |
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| 976 | * Some CPUs have special instructions which swap a 32-bit quantity in |
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| 977 | * a single instruction (e.g. i486). It is probably best to avoid |
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| 978 | * an "endian swapping control bit" in the CPU. One good reason is |
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| 979 | * that interrupts would probably have to be disabled to insure that |
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| 980 | * an interrupt does not try to access the same "chunk" with the wrong |
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| 981 | * endian. Another good reason is that on some CPUs, the endian bit |
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| 982 | * endianness for ALL fetches -- both code and data -- so the code |
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| 983 | * will be fetched incorrectly. |
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| 984 | */ |
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| 985 | |
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| 986 | #define CPU_swap_u32( value ) \ |
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| 987 | ((value&0xff) << 24) | (((value >> 8)&0xff) << 16) | \ |
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| 988 | (((value >> 16)&0xff) << 8) | ((value>>24)&0xff) |
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| 989 | |
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| 990 | #define CPU_swap_u16( value ) \ |
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| 991 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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| 992 | |
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| 993 | #ifdef __cplusplus |
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| 994 | } |
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| 995 | #endif |
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| 996 | |
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| 997 | #endif |
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