source: rtems/c/src/exec/score/cpu/a29k/cpu_asm.s @ a4d97d94

4.104.114.84.95
Last change on this file since a4d97d94 was a4d97d94, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 18, 1996 at 8:45:27 PM

new files submitted by Craig Lebakken (lebakken@…) and Derrick Ostertag
(ostertag@…).

  • Property mode set to 100644
File size: 12.1 KB
Line 
1;/*  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
2; *
3; *  Author:  Craig Lebakken <craigl@transition.com>
4; *
5; *  COPYRIGHT (c) 1996 by Transition Networks Inc.
6; *
7; *  To anyone who acknowledges that this file is provided "AS IS"
8; *  without any express or implied warranty:
9; *   permission to use, copy, modify, and distribute this file
10; *   for any purpose is hereby granted without fee, provided that
11; *   the above copyright notice and this notice appears in all
12; *   copies, and that the name of Transition Networks not be used in
13; *   advertising or publicity pertaining to distribution of the
14; *   software without specific, written prior permission.
15; *   Transition Networks makes no representations about the suitability
16; *   of this software for any purpose.
17; *
18; *
19; *  This file contains the basic algorithms for all assembly code used
20; *  in an specific CPU port of RTEMS.  These algorithms must be implemented
21; *  in assembly language
22; *
23; *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
24; *
25; *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
26; *  On-Line Applications Research Corporation (OAR).
27; *  All rights assigned to U.S. Government, 1994.
28; *
29; *  This material may be reproduced by or for the U.S. Government pursuant
30; *  to the copyright license under the clause at DFARS 252.227-7013.  This
31; *  notice must appear in all copies of this file and its derivatives.
32; *
33; *  $Id$
34; */
35
36;/*
37; *  This is supposed to be an assembly file.  This means that system.h
38; *  and cpu.h should not be included in a "real" cpu_asm file.  An
39; *  implementation in assembly should include "cpu_asm.h>
40; */
41
42;#include <cpu_asm.h>
43        .include "register.ah"
44        .include "amd.ah"
45        .include "pswmacro.ah"
46;       .extern _bsp_exit
47;
48; push a register onto the struct
49        .macro  spush, sp, reg
50        store   0, 0, reg, sp           ; push register
51        add     sp, sp, 4               ; adjust stack pointer
52        .endm
53; push a register onto the struct
54        .macro  spushsr, sp, reg, sr
55        mfsr    reg, sr
56        store   0, 0, reg, sp           ; push register
57        add     sp, sp, 4               ; adjust stack pointer
58        .endm
59; pop a register from the struct
60        .macro  spop, reg, sp
61        load    0, 0, reg, sp
62        add     sp,sp,4
63        .endm
64; pop a special register from the struct
65        .macro  spopsr, sreg, reg, sp
66        load    0, 0, reg, sp
67        mtsr    sreg, reg
68        add     sp,sp,4
69        .endm
70;
71;/*
72; *  _CPU_Context_save_fp_context
73; *
74; *  This routine is responsible for saving the FP context
75; *  at *fp_context_ptr.  If the point to load the FP context
76; *  from is changed then the pointer is modified by this routine.
77; *
78; *  Sometimes a macro implementation of this is in cpu.h which dereferences
79; *  the ** and a similarly named routine in this file is passed something
80; *  like a (Context_Control_fp *).  The general rule on making this decision
81; *  is to avoid writing assembly language.
82; */
83
84;#if 0
85;void _CPU_Context_save_fp(
86;  void **fp_context_ptr
87;)
88;{
89;}
90;#endif
91        .global _CPU_Context_save_fp
92_CPU_Context_save_fp:
93        jmpi    lr0
94        nop
95
96;/*
97; *  _CPU_Context_restore_fp_context
98; *
99; *  This routine is responsible for restoring the FP context
100; *  at *fp_context_ptr.  If the point to load the FP context
101; *  from is changed then the pointer is modified by this routine.
102; *
103; *  Sometimes a macro implementation of this is in cpu.h which dereferences
104; *  the ** and a similarly named routine in this file is passed something
105; *  like a (Context_Control_fp *).  The general rule on making this decision
106; *  is to avoid writing assembly language.
107; */
108
109;#if 0
110;void _CPU_Context_restore_fp(
111;  void **fp_context_ptr
112;)
113;{
114;}
115;#endif
116        .global __CPU_Context_restore_fp
117__CPU_Context_restore_fp:
118        jmpi    lr0
119        nop
120
121;/*  _CPU_Context_switch
122; *
123; *  This routine performs a normal non-FP context switch.
124; */
125;#if 0
126;void _CPU_Context_switch(
127;  Context_Control  *run,
128;  Context_Control  *heir
129;)
130;{
131;}
132;#endif
133        .global __CPU_Context_switch
134__CPU_Context_switch:
135        asneq   106, gr1, gr1                           ; syscall
136        jmpi    lr0                                     ;
137        nop                                             ;
138
139
140
141        .global _a29k_context_switch_sup
142_a29k_context_switch_sup:
143        add     pcb,lr2,0
144        add     kt1,lr3,0       ;move heir pointer to safe location
145        constn  it0,SIG_SYNC
146        spush   pcb,it0
147        spush   pcb,gr1
148        spush   pcb,rab         ;push rab
149        spushsr pcb,it0,pc0     ;push specials
150        spushsr pcb,it0,pc1
151        add     pcb,pcb,1*4     ;space pc2
152        spushsr pcb,it0,CHA     ;push CHA
153        spushsr pcb,it0,CHD     ;push CHD
154        spushsr pcb,it0,CHC     ;push CHC
155        add     pcb,pcb,1*4     ;space for alu
156        spushsr pcb,it0,ops     ;push OPS
157        mfsr    kt0,cps         ;current status
158        const   it1,FZ          ;FZ constant
159        andn    it1,kt0,it1     ;clear FZ bit
160        mtsr    cps,it1         ;cps without FZ
161        add     pcb,pcb,1*4     ;space for tav
162        mtsrim  chc,0           ;possible DERR
163;
164        spush   pcb,lr1         ;push R-stack
165        spush   pcb,rfb         ; support
166        spush   pcb,msp         ;push M-stack pnt.
167;
168        add     pcb,pcb,3*4     ;space for floating point
169;       spush   pcb,FPStat0     ;floating point
170;       spush   pcb,FPStat1
171;       spush   pcb,FPStat2
172;
173        add     pcb,pcb,4*4     ;space for IPA..Q
174;
175        mtsrim  cr,29-1
176        storem  0,0,gr96,pcb    ;push gr96-124, optional
177        add     pcb,pcb,29*4    ;space for gr96-124
178;
179        sub     it0,rfb,gr1     ;get bytes in cache
180        srl     it0,it0,2       ;adjust to words
181        sub     it0,it0,1
182        spush   pcb,it0
183        mtsr    cr,it0
184        storem  0,0,lr0,pcb     ;save lr0-rfb
185;
186context_restore:
187        add     pcb,kt1,0       ;pcb=heir
188        add     pcb,pcb,4       ;space for signal num
189        spop    gr1,pcb         ;restore freeze registers
190        add     gr1,gr1,0       ;alu op
191        add     pcb,pcb,9*4     ;move past freeze registers
192        add     pcb,pcb,1*4     ;space for tav
193        spop    lr1,pcb
194        spop    rfb,pcb
195        spop    msp,pcb
196;       spop    FPStat0,pcb
197;       spop    FPStat1,pcb
198;       spop    FPStat2,pcb
199        add     pcb,pcb,3*4     ;space for floating point
200        add     pcb,pcb,4*4     ;space for IPA..Q
201        mtsrim  cr,29-1
202        loadm   0,0,gr96,pcb    ;pop gr96-gr124
203        add     pcb,pcb,29*4    ;space for gr96-124
204
205        spop    it1,pcb         ;pop locals count
206        mtsr    cr,it1
207        loadm   0,0,lr0,pcb     ;load locals
208       
209        add     pcb,kt1,0       ;pcb=heir
210        mtsr    cps,kt0         ;cps with FZ
211        nop
212        add     pcb,pcb,4       ;space for signal num
213        spop    gr1,pcb         ;restore freeze registers
214        add     gr1,gr1,0       ;alu op
215        spop    rab,pcb
216        spopsr  pc0,it1,pcb
217        spopsr  pc1,it1,pcb
218        add     pcb,pcb,4       ;space for pc2
219        spopsr  CHA,it1,pcb
220        spopsr  CHD,it1,pcb
221        spopsr  CHC,it1,pcb
222        add     pcb,pcb,4       ;space for alu
223        spopsr  ops,it1,pcb
224        nop
225        iret
226
227
228;/*
229; *  _CPU_Context_restore
230; *
231; *  This routine is generallu used only to restart self in an
232; *  efficient manner.  It may simply be a label in _CPU_Context_switch.
233; *
234; *  NOTE: May be unnecessary to reload some registers.
235; */
236;#if 0
237;void _CPU_Context_restore(
238;  Context_Control *new_context
239;)
240;{
241;}
242;#endif
243
244        .global __CPU_Context_restore
245__CPU_Context_restore:
246        asneq   107, gr1, gr1                   ; syscall
247        jmpi    lr0                                     ;
248        nop                                             ;
249
250        .global _a29k_context_restore_sup
251_a29k_context_restore_sup:
252        add     kt1,lr2,0       ;kt1 = restore context
253        mfsr    kt0,cps         ;current status
254        const   it1,FZ          ;FZ constant
255        andn    it1,kt0,it1     ;clear FZ bit
256        mtsr    cps,it1         ;cps without FZ
257        jmp     context_restore
258        nop
259
260        .global _a29k_context_save_sup
261_a29k_context_save_sup:
262        add     pcb,lr2,0
263        constn  it0,SIG_SYNC
264        spush   pcb,it0
265        spush   pcb,gr1
266        spush   pcb,rab         ;push rab
267        spushsr pcb,it0,pc0     ;push specials
268        spushsr pcb,it0,pc1
269        add     pcb,pcb,1*4     ;space pc2
270        spushsr pcb,it0,CHA     ;push CHA
271        spushsr pcb,it0,CHD     ;push CHD
272        spushsr pcb,it0,CHC     ;push CHC
273        add     pcb,pcb,1*4     ;space for alu
274        spushsr pcb,it0,ops     ;push OPS
275        mfsr    it0,cps         ;current status
276SaveFZState     it1,it2
277        add     pcb,pcb,1*4     ;space for tav
278        mtsrim  chc,0           ;possible DERR
279;
280        spush   pcb,lr1         ;push R-stack
281        spush   pcb,rfb         ; support
282        spush   pcb,msp         ;push M-stack pnt.
283;
284        spush   pcb,FPStat0     ;floating point
285        spush   pcb,FPStat1     
286        spush   pcb,FPStat2
287;
288        add     pcb,pcb,4*4     ;space for IPA..Q
289;
290        mtsrim  cr,29-1
291        storem  0,0,gr96,pcb    ;push gr96-124, optional
292        add     pcb,pcb,29*4    ;space for gr96-124
293;
294        sub     kt0,rfb,gr1     ;get bytes in cache
295        srl     kt0,kt0,2       ;adjust to words
296        sub     kt0,kt0,1       
297        spush   pcb,kt0         ;push number of words
298        mtsr    cr,kt0
299        storem  0,0,lr0,pcb     ;save lr0-rfb
300;
301        mtsr    cps,it0         ;cps with FZ
302RestoreFZState  it1,it2
303
304        nop
305        nop
306        nop
307;
308        iret
309;
310
311        .global __CPU_Context_save
312__CPU_Context_save:
313        asneq   108, gr1, gr1                   ; syscall
314        jmpi    lr0                                     ;
315        nop                                             ;
316
317
318;/*  void __ISR_Handler()
319; *
320; *  This routine provides the RTEMS interrupt management.
321; *
322; */
323
324;#if 0
325;void _ISR_Handler()
326;{
327;   /*
328;    *  This discussion ignores a lot of the ugly details in a real
329;    *  implementation such as saving enough registers/state to be
330;    *  able to do something real.  Keep in mind that the goal is
331;    *  to invoke a user's ISR handler which is written in C and
332;    *  uses a certain set of registers.
333;    *
334;    *  Also note that the exact order is to a large extent flexible.
335;    *  Hardware will dictate a sequence for a certain subset of
336;    *  _ISR_Handler while requirements for setting
337;    */
338
339;  /*
340;   *  At entry to "common" _ISR_Handler, the vector number must be
341;   *  available.  On some CPUs the hardware puts either the vector
342;   *  number or the offset into the vector table for this ISR in a
343;   *  known place.  If the hardware does not give us this information,
344;   *  then the assembly portion of RTEMS for this port will contain
345;   *  a set of distinct interrupt entry points which somehow place
346;   *  the vector number in a known place (which is safe if another
347;   *  interrupt nests this one) and branches to _ISR_Handler.
348;   *
349;   *  save some or all context on stack
350;   *  may need to save some special interrupt information for exit
351;   *
352;   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
353;   *    if ( _ISR_Nest_level == 0 )
354;   *      switch to software interrupt stack
355;   *  #endif
356;   *
357;   *  _ISR_Nest_level++;
358;   *
359;   *  _Thread_Dispatch_disable_level++;
360;   *
361;   *  (*_ISR_Vector_table[ vector ])( vector );
362;   *
363;   *  --_ISR_Nest_level;
364;   *
365;   *  if ( _ISR_Nest_level )
366;   *    goto the label "exit interrupt (simple case)"
367;   *
368;   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
369;   *    restore stack
370;   *  #endif
371;   * 
372;   *  if ( !_Context_Switch_necessary )
373;   *    goto the label "exit interrupt (simple case)"
374;   * 
375;   *  if ( !_ISR_Signals_to_thread_executing )
376;   *    goto the label "exit interrupt (simple case)"
377;   *
378;   *  call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
379;   *
380;   *  prepare to get out of interrupt
381;   *  return from interrupt  (maybe to _ISR_Dispatch)
382;   *
383;   *  LABEL "exit interrupt (simple case):
384;   *  prepare to get out of interrupt
385;   *  return from interrupt
386;   */
387;}
388;#endif
389;        .global __ISR_Handler
390;__ISR_Handler:
391;       jmpi lr0
392;        nop
393
394        .global _a29k_disable
395_a29k_disable:
396        asneq 110, gr96, gr96
397        jmpi lr0
398        nop
399
400        .global _a29k_disable_sup
401_a29k_disable_sup:
402        mfsr    kt0, ops
403        const   kt1, (DI | TD)
404        consth  kt1, (DI | TD)
405        or      kt1, kt0, kt1
406        mtsr    ops, kt1
407        iret
408        nop
409
410        .global _a29k_disable_all
411_a29k_disable_all:
412        asneq 112, gr96, gr96
413        jmpi lr0
414        nop
415
416        .global _a29k_disable_all_sup
417_a29k_disable_all_sup:
418        mfsr    kt0, ops
419        const   kt1, DA
420        consth  kt1, DA
421        or      kt1, kt0, kt1
422        mtsr    ops, kt1
423        iret
424        nop
425
426        .global _a29k_enable_all
427_a29k_enable_all:
428        asneq 111, gr96, gr96
429        jmpi lr0
430        nop
431
432        .global _a29k_enable_all_sup
433_a29k_enable_all_sup:
434        mfsr    kt0, ops
435        const   kt1, DA
436        consth  kt1, DA
437        andn    kt1, kt0, kt1
438        mtsr    ops, kt1
439        iret
440        nop
441
442        .global _a29k_enable
443_a29k_enable:
444        asneq 109, gr96, gr96
445        jmpi lr0
446        nop
447
448        .global _a29k_enable_sup
449_a29k_enable_sup:
450        mfsr    kt0, ops
451        const   kt1, (DI | TD)
452        consth  kt1, (DI | TD)
453        andn    kt1, kt0, kt1
454        mtsr    ops, kt1
455        iret
456        nop
457
458        .global _a29k_halt
459_a29k_halt:
460        halt
461        jmp _a29k_halt
462        nop
463
464        .global _a29k_super_mode
465_a29k_super_mode:
466        mfsr gr96, ops
467        or gr96, gr96, 0x10
468        mtsr ops, gr96
469        iret
470        nop
471
472        .global _a29k_as70
473_a29k_as70:
474        asneq 70,gr96,gr96
475        jmpi lr0
476        nop
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