1 | ;/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s |
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2 | ; * |
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3 | ; * Author: Craig Lebakken <craigl@transition.com> |
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4 | ; * |
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5 | ; * COPYRIGHT (c) 1996 by Transition Networks Inc. |
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6 | ; * |
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7 | ; * To anyone who acknowledges that this file is provided "AS IS" |
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8 | ; * without any express or implied warranty: |
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9 | ; * permission to use, copy, modify, and distribute this file |
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10 | ; * for any purpose is hereby granted without fee, provided that |
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11 | ; * the above copyright notice and this notice appears in all |
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12 | ; * copies, and that the name of Transition Networks not be used in |
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13 | ; * advertising or publicity pertaining to distribution of the |
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14 | ; * software without specific, written prior permission. |
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15 | ; * Transition Networks makes no representations about the suitability |
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16 | ; * of this software for any purpose. |
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17 | ; * |
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18 | ; * |
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19 | ; * This file contains the basic algorithms for all assembly code used |
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20 | ; * in an specific CPU port of RTEMS. These algorithms must be implemented |
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21 | ; * in assembly language |
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22 | ; * |
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23 | ; * NOTE: This is supposed to be a .S or .s file NOT a C file. |
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24 | ; * |
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25 | ; * COPYRIGHT (c) 1989-1997. |
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26 | ; * On-Line Applications Research Corporation (OAR). |
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27 | ; * Copyright assigned to U.S. Government, 1994. |
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28 | ; * |
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29 | ; * The license and distribution terms for this file may be |
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30 | ; * found in the file LICENSE in this distribution or at |
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31 | ; * http://www.OARcorp.com/rtems/license.html. |
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32 | ; * |
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33 | ; * $Id$ |
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34 | ; */ |
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35 | |
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36 | ;/* |
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37 | ; * This is supposed to be an assembly file. This means that system.h |
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38 | ; * and cpu.h should not be included in a "real" cpu_asm file. An |
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39 | ; * implementation in assembly should include "cpu_asm.h> |
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40 | ; */ |
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41 | |
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42 | ;#include <cpu_asm.h> |
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43 | .include "register.ah" |
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44 | .include "amd.ah" |
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45 | .include "pswmacro.ah" |
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46 | ; .extern _bsp_exit |
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47 | ; |
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48 | ; push a register onto the struct |
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49 | .macro spush, sp, reg |
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50 | store 0, 0, reg, sp ; push register |
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51 | add sp, sp, 4 ; adjust stack pointer |
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52 | .endm |
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53 | ; push a register onto the struct |
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54 | .macro spushsr, sp, reg, sr |
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55 | mfsr reg, sr |
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56 | store 0, 0, reg, sp ; push register |
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57 | add sp, sp, 4 ; adjust stack pointer |
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58 | .endm |
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59 | ; pop a register from the struct |
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60 | .macro spop, reg, sp |
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61 | load 0, 0, reg, sp |
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62 | add sp,sp,4 |
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63 | .endm |
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64 | ; pop a special register from the struct |
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65 | .macro spopsr, sreg, reg, sp |
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66 | load 0, 0, reg, sp |
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67 | mtsr sreg, reg |
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68 | add sp,sp,4 |
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69 | .endm |
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70 | ; |
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71 | ;/* |
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72 | ; * _CPU_Context_save_fp_context |
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73 | ; * |
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74 | ; * This routine is responsible for saving the FP context |
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75 | ; * at *fp_context_ptr. If the point to load the FP context |
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76 | ; * from is changed then the pointer is modified by this routine. |
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77 | ; * |
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78 | ; * Sometimes a macro implementation of this is in cpu.h which dereferences |
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79 | ; * the ** and a similarly named routine in this file is passed something |
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80 | ; * like a (Context_Control_fp *). The general rule on making this decision |
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81 | ; * is to avoid writing assembly language. |
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82 | ; */ |
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83 | |
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84 | ;#if 0 |
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85 | ;void _CPU_Context_save_fp( |
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86 | ; void **fp_context_ptr |
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87 | ;) |
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88 | ;{ |
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89 | ;} |
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90 | ;#endif |
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91 | .global _CPU_Context_save_fp |
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92 | _CPU_Context_save_fp: |
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93 | jmpi lr0 |
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94 | nop |
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95 | |
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96 | ;/* |
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97 | ; * _CPU_Context_restore_fp_context |
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98 | ; * |
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99 | ; * This routine is responsible for restoring the FP context |
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100 | ; * at *fp_context_ptr. If the point to load the FP context |
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101 | ; * from is changed then the pointer is modified by this routine. |
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102 | ; * |
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103 | ; * Sometimes a macro implementation of this is in cpu.h which dereferences |
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104 | ; * the ** and a similarly named routine in this file is passed something |
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105 | ; * like a (Context_Control_fp *). The general rule on making this decision |
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106 | ; * is to avoid writing assembly language. |
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107 | ; */ |
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108 | |
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109 | ;#if 0 |
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110 | ;void _CPU_Context_restore_fp( |
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111 | ; void **fp_context_ptr |
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112 | ;) |
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113 | ;{ |
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114 | ;} |
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115 | ;#endif |
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116 | .global __CPU_Context_restore_fp |
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117 | __CPU_Context_restore_fp: |
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118 | jmpi lr0 |
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119 | nop |
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120 | |
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121 | ;/* _CPU_Context_switch |
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122 | ; * |
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123 | ; * This routine performs a normal non-FP context switch. |
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124 | ; */ |
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125 | ;#if 0 |
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126 | ;void _CPU_Context_switch( |
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127 | ; Context_Control *run, |
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128 | ; Context_Control *heir |
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129 | ;) |
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130 | ;{ |
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131 | ;} |
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132 | ;#endif |
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133 | .global __CPU_Context_switch |
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134 | __CPU_Context_switch: |
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135 | asneq 106, gr1, gr1 ; syscall |
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136 | jmpi lr0 ; |
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137 | nop ; |
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138 | |
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139 | |
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140 | |
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141 | .global _a29k_context_switch_sup |
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142 | _a29k_context_switch_sup: |
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143 | add pcb,lr2,0 |
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144 | add kt1,lr3,0 ;move heir pointer to safe location |
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145 | constn it0,SIG_SYNC |
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146 | spush pcb,it0 |
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147 | spush pcb,gr1 |
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148 | spush pcb,rab ;push rab |
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149 | spushsr pcb,it0,pc0 ;push specials |
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150 | spushsr pcb,it0,pc1 |
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151 | add pcb,pcb,1*4 ;space pc2 |
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152 | spushsr pcb,it0,CHA ;push CHA |
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153 | spushsr pcb,it0,CHD ;push CHD |
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154 | spushsr pcb,it0,CHC ;push CHC |
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155 | add pcb,pcb,1*4 ;space for alu |
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156 | spushsr pcb,it0,ops ;push OPS |
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157 | mfsr kt0,cps ;current status |
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158 | const it1,FZ ;FZ constant |
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159 | andn it1,kt0,it1 ;clear FZ bit |
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160 | mtsr cps,it1 ;cps without FZ |
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161 | add pcb,pcb,1*4 ;space for tav |
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162 | mtsrim chc,0 ;possible DERR |
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163 | ; |
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164 | spush pcb,lr1 ;push R-stack |
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165 | spush pcb,rfb ; support |
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166 | spush pcb,msp ;push M-stack pnt. |
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167 | ; |
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168 | add pcb,pcb,3*4 ;space for floating point |
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169 | ; spush pcb,FPStat0 ;floating point |
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170 | ; spush pcb,FPStat1 |
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171 | ; spush pcb,FPStat2 |
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172 | ; |
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173 | add pcb,pcb,4*4 ;space for IPA..Q |
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174 | ; |
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175 | mtsrim cr,29-1 |
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176 | storem 0,0,gr96,pcb ;push gr96-124, optional |
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177 | add pcb,pcb,29*4 ;space for gr96-124 |
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178 | ; |
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179 | sub it0,rfb,gr1 ;get bytes in cache |
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180 | srl it0,it0,2 ;adjust to words |
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181 | sub it0,it0,1 |
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182 | spush pcb,it0 |
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183 | mtsr cr,it0 |
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184 | storem 0,0,lr0,pcb ;save lr0-rfb |
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185 | ; |
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186 | context_restore: |
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187 | add pcb,kt1,0 ;pcb=heir |
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188 | add pcb,pcb,4 ;space for signal num |
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189 | spop gr1,pcb ;restore freeze registers |
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190 | add gr1,gr1,0 ;alu op |
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191 | add pcb,pcb,9*4 ;move past freeze registers |
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192 | add pcb,pcb,1*4 ;space for tav |
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193 | spop lr1,pcb |
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194 | spop rfb,pcb |
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195 | spop msp,pcb |
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196 | ; spop FPStat0,pcb |
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197 | ; spop FPStat1,pcb |
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198 | ; spop FPStat2,pcb |
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199 | add pcb,pcb,3*4 ;space for floating point |
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200 | add pcb,pcb,4*4 ;space for IPA..Q |
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201 | mtsrim cr,29-1 |
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202 | loadm 0,0,gr96,pcb ;pop gr96-gr124 |
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203 | add pcb,pcb,29*4 ;space for gr96-124 |
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204 | |
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205 | spop it1,pcb ;pop locals count |
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206 | mtsr cr,it1 |
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207 | loadm 0,0,lr0,pcb ;load locals |
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208 | |
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209 | add pcb,kt1,0 ;pcb=heir |
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210 | mtsr cps,kt0 ;cps with FZ |
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211 | nop |
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212 | add pcb,pcb,4 ;space for signal num |
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213 | spop gr1,pcb ;restore freeze registers |
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214 | add gr1,gr1,0 ;alu op |
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215 | spop rab,pcb |
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216 | spopsr pc0,it1,pcb |
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217 | spopsr pc1,it1,pcb |
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218 | add pcb,pcb,4 ;space for pc2 |
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219 | spopsr CHA,it1,pcb |
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220 | spopsr CHD,it1,pcb |
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221 | spopsr CHC,it1,pcb |
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222 | add pcb,pcb,4 ;space for alu |
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223 | spopsr ops,it1,pcb |
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224 | nop |
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225 | iret |
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226 | |
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227 | |
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228 | ;/* |
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229 | ; * _CPU_Context_restore |
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230 | ; * |
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231 | ; * This routine is generally used only to restart self in an |
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232 | ; * efficient manner. It may simply be a label in _CPU_Context_switch. |
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233 | ; * |
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234 | ; * NOTE: May be unnecessary to reload some registers. |
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235 | ; */ |
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236 | ;#if 0 |
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237 | ;void _CPU_Context_restore( |
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238 | ; Context_Control *new_context |
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239 | ;) |
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240 | ;{ |
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241 | ;} |
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242 | ;#endif |
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243 | |
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244 | .global __CPU_Context_restore |
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245 | __CPU_Context_restore: |
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246 | asneq 107, gr1, gr1 ; syscall |
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247 | jmpi lr0 ; |
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248 | nop ; |
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249 | |
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250 | .global _a29k_context_restore_sup |
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251 | _a29k_context_restore_sup: |
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252 | add kt1,lr2,0 ;kt1 = restore context |
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253 | mfsr kt0,cps ;current status |
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254 | const it1,FZ ;FZ constant |
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255 | andn it1,kt0,it1 ;clear FZ bit |
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256 | mtsr cps,it1 ;cps without FZ |
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257 | jmp context_restore |
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258 | nop |
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259 | |
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260 | .global _a29k_context_save_sup |
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261 | _a29k_context_save_sup: |
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262 | add pcb,lr2,0 |
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263 | constn it0,SIG_SYNC |
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264 | spush pcb,it0 |
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265 | spush pcb,gr1 |
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266 | spush pcb,rab ;push rab |
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267 | spushsr pcb,it0,pc0 ;push specials |
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268 | spushsr pcb,it0,pc1 |
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269 | add pcb,pcb,1*4 ;space pc2 |
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270 | spushsr pcb,it0,CHA ;push CHA |
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271 | spushsr pcb,it0,CHD ;push CHD |
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272 | spushsr pcb,it0,CHC ;push CHC |
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273 | add pcb,pcb,1*4 ;space for alu |
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274 | spushsr pcb,it0,ops ;push OPS |
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275 | mfsr it0,cps ;current status |
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276 | SaveFZState it1,it2 |
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277 | add pcb,pcb,1*4 ;space for tav |
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278 | mtsrim chc,0 ;possible DERR |
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279 | ; |
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280 | spush pcb,lr1 ;push R-stack |
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281 | spush pcb,rfb ; support |
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282 | spush pcb,msp ;push M-stack pnt. |
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283 | ; |
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284 | spush pcb,FPStat0 ;floating point |
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285 | spush pcb,FPStat1 |
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286 | spush pcb,FPStat2 |
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287 | ; |
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288 | add pcb,pcb,4*4 ;space for IPA..Q |
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289 | ; |
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290 | mtsrim cr,29-1 |
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291 | storem 0,0,gr96,pcb ;push gr96-124, optional |
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292 | add pcb,pcb,29*4 ;space for gr96-124 |
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293 | ; |
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294 | sub kt0,rfb,gr1 ;get bytes in cache |
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295 | srl kt0,kt0,2 ;adjust to words |
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296 | sub kt0,kt0,1 |
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297 | spush pcb,kt0 ;push number of words |
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298 | mtsr cr,kt0 |
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299 | storem 0,0,lr0,pcb ;save lr0-rfb |
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300 | ; |
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301 | mtsr cps,it0 ;cps with FZ |
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302 | RestoreFZState it1,it2 |
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303 | |
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304 | nop |
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305 | nop |
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306 | nop |
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307 | ; |
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308 | iret |
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309 | ; |
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310 | |
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311 | .global __CPU_Context_save |
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312 | __CPU_Context_save: |
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313 | asneq 108, gr1, gr1 ; syscall |
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314 | jmpi lr0 ; |
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315 | nop ; |
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316 | |
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317 | |
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318 | ;/* void __ISR_Handler() |
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319 | ; * |
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320 | ; * This routine provides the RTEMS interrupt management. |
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321 | ; * |
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322 | ; */ |
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323 | |
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324 | ;#if 0 |
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325 | ;void _ISR_Handler() |
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326 | ;{ |
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327 | ; /* |
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328 | ; * This discussion ignores a lot of the ugly details in a real |
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329 | ; * implementation such as saving enough registers/state to be |
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330 | ; * able to do something real. Keep in mind that the goal is |
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331 | ; * to invoke a user's ISR handler which is written in C and |
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332 | ; * uses a certain set of registers. |
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333 | ; * |
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334 | ; * Also note that the exact order is to a large extent flexible. |
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335 | ; * Hardware will dictate a sequence for a certain subset of |
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336 | ; * _ISR_Handler while requirements for setting |
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337 | ; */ |
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338 | |
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339 | ; /* |
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340 | ; * At entry to "common" _ISR_Handler, the vector number must be |
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341 | ; * available. On some CPUs the hardware puts either the vector |
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342 | ; * number or the offset into the vector table for this ISR in a |
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343 | ; * known place. If the hardware does not give us this information, |
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344 | ; * then the assembly portion of RTEMS for this port will contain |
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345 | ; * a set of distinct interrupt entry points which somehow place |
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346 | ; * the vector number in a known place (which is safe if another |
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347 | ; * interrupt nests this one) and branches to _ISR_Handler. |
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348 | ; * |
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349 | ; * save some or all context on stack |
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350 | ; * may need to save some special interrupt information for exit |
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351 | ; * |
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352 | ; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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353 | ; * if ( _ISR_Nest_level == 0 ) |
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354 | ; * switch to software interrupt stack |
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355 | ; * #endif |
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356 | ; * |
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357 | ; * _ISR_Nest_level++; |
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358 | ; * |
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359 | ; * _Thread_Dispatch_disable_level++; |
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360 | ; * |
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361 | ; * (*_ISR_Vector_table[ vector ])( vector ); |
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362 | ; * |
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363 | ; * --_ISR_Nest_level; |
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364 | ; * |
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365 | ; * if ( _ISR_Nest_level ) |
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366 | ; * goto the label "exit interrupt (simple case)" |
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367 | ; * |
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368 | ; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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369 | ; * restore stack |
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370 | ; * #endif |
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371 | ; * |
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372 | ; * if ( !_Context_Switch_necessary ) |
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373 | ; * goto the label "exit interrupt (simple case)" |
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374 | ; * |
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375 | ; * if ( !_ISR_Signals_to_thread_executing ) |
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376 | ; * goto the label "exit interrupt (simple case)" |
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377 | ; * |
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378 | ; * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch |
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379 | ; * |
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380 | ; * prepare to get out of interrupt |
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381 | ; * return from interrupt (maybe to _ISR_Dispatch) |
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382 | ; * |
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383 | ; * LABEL "exit interrupt (simple case): |
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384 | ; * prepare to get out of interrupt |
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385 | ; * return from interrupt |
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386 | ; */ |
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387 | ;} |
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388 | ;#endif |
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389 | ; .global __ISR_Handler |
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390 | ;__ISR_Handler: |
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391 | ; jmpi lr0 |
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392 | ; nop |
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393 | |
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394 | .global _a29k_getops |
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395 | _a29k_getops: |
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396 | asneq 113, gr96, gr96 |
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397 | jmpi lr0 |
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398 | nop |
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399 | |
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400 | .global _a29k_getops_sup |
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401 | _a29k_getops_sup: |
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402 | mfsr gr96, ops ; caller wants ops |
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403 | iret |
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404 | nop |
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405 | |
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406 | .global _a29k_disable |
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407 | _a29k_disable: |
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408 | asneq 110, gr96, gr96 |
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409 | jmpi lr0 |
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410 | nop |
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411 | |
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412 | .global _a29k_disable_sup |
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413 | _a29k_disable_sup: |
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414 | mfsr kt0, ops |
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415 | add gr96, kt0, 0 ; return ops to caller |
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416 | const kt1, (DI | TD) |
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417 | consth kt1, (DI | TD) |
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418 | or kt1, kt0, kt1 |
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419 | mtsr ops, kt1 |
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420 | iret |
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421 | nop |
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422 | |
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423 | .global _a29k_disable_all |
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424 | _a29k_disable_all: |
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425 | asneq 112, gr96, gr96 |
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426 | jmpi lr0 |
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427 | nop |
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428 | |
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429 | .global _a29k_disable_all_sup |
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430 | _a29k_disable_all_sup: |
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431 | mfsr kt0, ops |
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432 | const kt1, (DI | TD) |
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433 | consth kt1, (DI | TD) |
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434 | or kt1, kt0, kt1 |
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435 | mtsr ops, kt1 |
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436 | iret |
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437 | nop |
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438 | |
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439 | .global _a29k_enable_all |
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440 | _a29k_enable_all: |
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441 | asneq 111, gr96, gr96 |
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442 | jmpi lr0 |
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443 | nop |
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444 | |
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445 | .global _a29k_enable_all_sup |
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446 | _a29k_enable_all_sup: |
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447 | mfsr kt0, ops |
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448 | const kt1, (DI | TD) |
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449 | consth kt1, (DI | TD) |
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450 | andn kt1, kt0, kt1 |
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451 | mtsr ops, kt1 |
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452 | iret |
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453 | nop |
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454 | |
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455 | .global _a29k_enable |
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456 | _a29k_enable: |
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457 | asneq 109, gr96, gr96 |
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458 | jmpi lr0 |
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459 | nop |
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460 | |
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461 | .global _a29k_enable_sup |
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462 | _a29k_enable_sup: |
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463 | mfsr kt0, ops |
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464 | const kt1, (DI | TD) |
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465 | consth kt1, (DI | TD) |
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466 | and kt3, lr2, kt1 |
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467 | andn kt0, kt0, kt1 |
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468 | or kt1, kt0, kt3 |
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469 | mtsr ops, kt1 |
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470 | iret |
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471 | nop |
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472 | |
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473 | .global _a29k_halt |
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474 | _a29k_halt: |
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475 | halt |
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476 | jmp _a29k_halt |
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477 | nop |
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478 | |
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479 | .global _a29k_super_mode |
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480 | _a29k_super_mode: |
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481 | mfsr gr96, ops |
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482 | or gr96, gr96, 0x10 |
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483 | mtsr ops, gr96 |
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484 | iret |
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485 | nop |
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486 | |
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487 | .global _a29k_as70 |
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488 | _a29k_as70: |
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489 | asneq 70,gr96,gr96 |
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490 | jmpi lr0 |
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491 | nop |
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