Context Navigation

cpu_asm.S @ d1c83050

4.104.114.84.95

Last change on this file since d1c83050 was d1c83050, checked in by Joel Sherrill <joel.sherrill@…>, on 09/22/00 at 13:59:42

2000-09-22 Joel Sherrill <joel@…>

Makefile.am, cpu_asm.S, psmacro.ah, rtems/score/cpu.h: First attempt to compile with GNU tools. Minor modifications to compile enough to get to assembler errors.

Property mode set to 100644

File size: 12.2 KB

Rev	Line
[a4d97d94]	1	;/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s
	2	; *
	3	; * Author: Craig Lebakken <craigl@transition.com>
	4	; *
	5	; * COPYRIGHT (c) 1996 by Transition Networks Inc.
	6	; *
	7	; * To anyone who acknowledges that this file is provided "AS IS"
	8	; * without any express or implied warranty:
	9	; * permission to use, copy, modify, and distribute this file
	10	; * for any purpose is hereby granted without fee, provided that
	11	; * the above copyright notice and this notice appears in all
	12	; * copies, and that the name of Transition Networks not be used in
	13	; * advertising or publicity pertaining to distribution of the
	14	; * software without specific, written prior permission.
	15	; * Transition Networks makes no representations about the suitability
	16	; * of this software for any purpose.
	17	; *
	18	; *
	19	; * This file contains the basic algorithms for all assembly code used
	20	; * in an specific CPU port of RTEMS. These algorithms must be implemented
	21	; * in assembly language
	22	; *
	23	; * NOTE: This is supposed to be a .S or .s file NOT a C file.
	24	; *
[08311cc3]	25	; * COPYRIGHT (c) 1989-1999.
[a4d97d94]	26	; * On-Line Applications Research Corporation (OAR).
	27	; *
[98e4ebf5]	28	; * The license and distribution terms for this file may be
	29	; * found in the file LICENSE in this distribution or at
[03f2154e]	30	; * http://www.OARcorp.com/rtems/license.html.
[a4d97d94]	31	; *
	32	; * $Id$
	33	; */
	34
	35	;/*
	36	; * This is supposed to be an assembly file. This means that system.h
	37	; * and cpu.h should not be included in a "real" cpu_asm file. An
	38	; * implementation in assembly should include "cpu_asm.h>
	39	; */
	40
	41	;#include <cpu_asm.h>
[d1c83050]	42	#include <register.ah>
	43	#include <amd.ah>
	44	#include <pswmacro.ah>
[a4d97d94]	45	; .extern _bsp_exit
	46	;
	47	; push a register onto the struct
	48	.macro spush, sp, reg
	49	store 0, 0, reg, sp ; push register
	50	add sp, sp, 4 ; adjust stack pointer
	51	.endm
	52	; push a register onto the struct
	53	.macro spushsr, sp, reg, sr
	54	mfsr reg, sr
	55	store 0, 0, reg, sp ; push register
	56	add sp, sp, 4 ; adjust stack pointer
	57	.endm
	58	; pop a register from the struct
	59	.macro spop, reg, sp
	60	load 0, 0, reg, sp
	61	add sp,sp,4
	62	.endm
	63	; pop a special register from the struct
	64	.macro spopsr, sreg, reg, sp
	65	load 0, 0, reg, sp
	66	mtsr sreg, reg
	67	add sp,sp,4
	68	.endm
	69	;
	70	;/*
	71	; * _CPU_Context_save_fp_context
	72	; *
	73	; * This routine is responsible for saving the FP context
	74	; * at *fp_context_ptr. If the point to load the FP context
	75	; * from is changed then the pointer is modified by this routine.
	76	; *
	77	; * Sometimes a macro implementation of this is in cpu.h which dereferences
	78	; * the ** and a similarly named routine in this file is passed something
	79	; * like a (Context_Control_fp *). The general rule on making this decision
	80	; * is to avoid writing assembly language.
	81	; */
	82
	83	;#if 0
	84	;void _CPU_Context_save_fp(
	85	; void **fp_context_ptr
	86	;)
	87	;{
	88	;}
	89	;#endif
	90	.global _CPU_Context_save_fp
	91	_CPU_Context_save_fp:
	92	jmpi lr0
	93	nop
	94
	95	;/*
	96	; * _CPU_Context_restore_fp_context
	97	; *
	98	; * This routine is responsible for restoring the FP context
	99	; * at *fp_context_ptr. If the point to load the FP context
	100	; * from is changed then the pointer is modified by this routine.
	101	; *
	102	; * Sometimes a macro implementation of this is in cpu.h which dereferences
	103	; * the ** and a similarly named routine in this file is passed something
	104	; * like a (Context_Control_fp *). The general rule on making this decision
	105	; * is to avoid writing assembly language.
	106	; */
	107
	108	;#if 0
	109	;void _CPU_Context_restore_fp(
	110	; void **fp_context_ptr
	111	;)
	112	;{
	113	;}
	114	;#endif
	115	.global __CPU_Context_restore_fp
	116	__CPU_Context_restore_fp:
	117	jmpi lr0
	118	nop
	119
	120	;/* _CPU_Context_switch
	121	; *
	122	; * This routine performs a normal non-FP context switch.
	123	; */
	124	;#if 0
	125	;void _CPU_Context_switch(
	126	; Context_Control *run,
	127	; Context_Control *heir
	128	;)
	129	;{
	130	;}
	131	;#endif
	132	.global __CPU_Context_switch
	133	__CPU_Context_switch:
	134	asneq 106, gr1, gr1 ; syscall
	135	jmpi lr0 ;
	136	nop ;
	137
	138
	139
	140	.global _a29k_context_switch_sup
	141	_a29k_context_switch_sup:
	142	add pcb,lr2,0
	143	add kt1,lr3,0 ;move heir pointer to safe location
	144	constn it0,SIG_SYNC
	145	spush pcb,it0
	146	spush pcb,gr1
	147	spush pcb,rab ;push rab
	148	spushsr pcb,it0,pc0 ;push specials
	149	spushsr pcb,it0,pc1
	150	add pcb,pcb,1*4 ;space pc2
	151	spushsr pcb,it0,CHA ;push CHA
	152	spushsr pcb,it0,CHD ;push CHD
	153	spushsr pcb,it0,CHC ;push CHC
	154	add pcb,pcb,1*4 ;space for alu
	155	spushsr pcb,it0,ops ;push OPS
	156	mfsr kt0,cps ;current status
	157	const it1,FZ ;FZ constant
	158	andn it1,kt0,it1 ;clear FZ bit
	159	mtsr cps,it1 ;cps without FZ
	160	add pcb,pcb,1*4 ;space for tav
	161	mtsrim chc,0 ;possible DERR
	162	;
	163	spush pcb,lr1 ;push R-stack
	164	spush pcb,rfb ; support
	165	spush pcb,msp ;push M-stack pnt.
	166	;
	167	add pcb,pcb,3*4 ;space for floating point
	168	; spush pcb,FPStat0 ;floating point
	169	; spush pcb,FPStat1
	170	; spush pcb,FPStat2
	171	;
	172	add pcb,pcb,4*4 ;space for IPA..Q
	173	;
	174	mtsrim cr,29-1
	175	storem 0,0,gr96,pcb ;push gr96-124, optional
	176	add pcb,pcb,29*4 ;space for gr96-124
	177	;
	178	sub it0,rfb,gr1 ;get bytes in cache
	179	srl it0,it0,2 ;adjust to words
	180	sub it0,it0,1
	181	spush pcb,it0
	182	mtsr cr,it0
	183	storem 0,0,lr0,pcb ;save lr0-rfb
	184	;
	185	context_restore:
	186	add pcb,kt1,0 ;pcb=heir
	187	add pcb,pcb,4 ;space for signal num
	188	spop gr1,pcb ;restore freeze registers
	189	add gr1,gr1,0 ;alu op
	190	add pcb,pcb,9*4 ;move past freeze registers
	191	add pcb,pcb,1*4 ;space for tav
	192	spop lr1,pcb
	193	spop rfb,pcb
	194	spop msp,pcb
	195	; spop FPStat0,pcb
	196	; spop FPStat1,pcb
	197	; spop FPStat2,pcb
	198	add pcb,pcb,3*4 ;space for floating point
	199	add pcb,pcb,4*4 ;space for IPA..Q
	200	mtsrim cr,29-1
	201	loadm 0,0,gr96,pcb ;pop gr96-gr124
	202	add pcb,pcb,29*4 ;space for gr96-124
	203
	204	spop it1,pcb ;pop locals count
	205	mtsr cr,it1
	206	loadm 0,0,lr0,pcb ;load locals
	207
	208	add pcb,kt1,0 ;pcb=heir
	209	mtsr cps,kt0 ;cps with FZ
	210	nop
	211	add pcb,pcb,4 ;space for signal num
	212	spop gr1,pcb ;restore freeze registers
	213	add gr1,gr1,0 ;alu op
	214	spop rab,pcb
	215	spopsr pc0,it1,pcb
	216	spopsr pc1,it1,pcb
	217	add pcb,pcb,4 ;space for pc2
	218	spopsr CHA,it1,pcb
	219	spopsr CHD,it1,pcb
	220	spopsr CHC,it1,pcb
	221	add pcb,pcb,4 ;space for alu
	222	spopsr ops,it1,pcb
	223	nop
	224	iret
	225
	226
	227	;/*
	228	; * _CPU_Context_restore
	229	; *
[77ea27fc]	230	; * This routine is generally used only to restart self in an
[a4d97d94]	231	; * efficient manner. It may simply be a label in _CPU_Context_switch.
	232	; *
	233	; * NOTE: May be unnecessary to reload some registers.
	234	; */
	235	;#if 0
	236	;void _CPU_Context_restore(
	237	; Context_Control *new_context
	238	;)
	239	;{
	240	;}
	241	;#endif
	242
	243	.global __CPU_Context_restore
	244	__CPU_Context_restore:
	245	asneq 107, gr1, gr1 ; syscall
	246	jmpi lr0 ;
	247	nop ;
	248
	249	.global _a29k_context_restore_sup
	250	_a29k_context_restore_sup:
	251	add kt1,lr2,0 ;kt1 = restore context
	252	mfsr kt0,cps ;current status
	253	const it1,FZ ;FZ constant
	254	andn it1,kt0,it1 ;clear FZ bit
	255	mtsr cps,it1 ;cps without FZ
	256	jmp context_restore
	257	nop
	258
	259	.global _a29k_context_save_sup
	260	_a29k_context_save_sup:
	261	add pcb,lr2,0
	262	constn it0,SIG_SYNC
	263	spush pcb,it0
	264	spush pcb,gr1
	265	spush pcb,rab ;push rab
	266	spushsr pcb,it0,pc0 ;push specials
	267	spushsr pcb,it0,pc1
	268	add pcb,pcb,1*4 ;space pc2
	269	spushsr pcb,it0,CHA ;push CHA
	270	spushsr pcb,it0,CHD ;push CHD
	271	spushsr pcb,it0,CHC ;push CHC
	272	add pcb,pcb,1*4 ;space for alu
	273	spushsr pcb,it0,ops ;push OPS
	274	mfsr it0,cps ;current status
	275	SaveFZState it1,it2
	276	add pcb,pcb,1*4 ;space for tav
	277	mtsrim chc,0 ;possible DERR
	278	;
	279	spush pcb,lr1 ;push R-stack
	280	spush pcb,rfb ; support
	281	spush pcb,msp ;push M-stack pnt.
	282	;
	283	spush pcb,FPStat0 ;floating point
	284	spush pcb,FPStat1
	285	spush pcb,FPStat2
	286	;
	287	add pcb,pcb,4*4 ;space for IPA..Q
	288	;
	289	mtsrim cr,29-1
	290	storem 0,0,gr96,pcb ;push gr96-124, optional
	291	add pcb,pcb,29*4 ;space for gr96-124
	292	;
	293	sub kt0,rfb,gr1 ;get bytes in cache
	294	srl kt0,kt0,2 ;adjust to words
	295	sub kt0,kt0,1
	296	spush pcb,kt0 ;push number of words
	297	mtsr cr,kt0
	298	storem 0,0,lr0,pcb ;save lr0-rfb
	299	;
	300	mtsr cps,it0 ;cps with FZ
	301	RestoreFZState it1,it2
	302
	303	nop
	304	nop
	305	nop
	306	;
	307	iret
	308	;
	309
	310	.global __CPU_Context_save
	311	__CPU_Context_save:
	312	asneq 108, gr1, gr1 ; syscall
	313	jmpi lr0 ;
	314	nop ;
	315
	316
	317	;/* void __ISR_Handler()
	318	; *
	319	; * This routine provides the RTEMS interrupt management.
	320	; *
	321	; */
	322
	323	;#if 0
	324	;void _ISR_Handler()
	325	;{
	326	; /*
	327	; * This discussion ignores a lot of the ugly details in a real
	328	; * implementation such as saving enough registers/state to be
	329	; * able to do something real. Keep in mind that the goal is
	330	; * to invoke a user's ISR handler which is written in C and
	331	; * uses a certain set of registers.
	332	; *
	333	; * Also note that the exact order is to a large extent flexible.
	334	; * Hardware will dictate a sequence for a certain subset of
	335	; * _ISR_Handler while requirements for setting
	336	; */
	337
	338	; /*
	339	; * At entry to "common" _ISR_Handler, the vector number must be
	340	; * available. On some CPUs the hardware puts either the vector
	341	; * number or the offset into the vector table for this ISR in a
	342	; * known place. If the hardware does not give us this information,
	343	; * then the assembly portion of RTEMS for this port will contain
	344	; * a set of distinct interrupt entry points which somehow place
	345	; * the vector number in a known place (which is safe if another
	346	; * interrupt nests this one) and branches to _ISR_Handler.
	347	; *
	348	; * save some or all context on stack
	349	; * may need to save some special interrupt information for exit
	350	; *
	351	; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
	352	; * if ( _ISR_Nest_level == 0 )
	353	; * switch to software interrupt stack
	354	; * #endif
	355	; *
	356	; * _ISR_Nest_level++;
	357	; *
	358	; * _Thread_Dispatch_disable_level++;
	359	; *
	360	; * (*_ISR_Vector_table[ vector ])( vector );
	361	; *
	362	; * --_ISR_Nest_level;
	363	; *
	364	; * if ( _ISR_Nest_level )
	365	; * goto the label "exit interrupt (simple case)"
	366	; *
	367	; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
	368	; * restore stack
	369	; * #endif
	370	; *
	371	; * if ( !_Context_Switch_necessary )
	372	; * goto the label "exit interrupt (simple case)"
	373	; *
	374	; * if ( !_ISR_Signals_to_thread_executing )
	375	; * goto the label "exit interrupt (simple case)"
	376	; *
	377	; * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
	378	; *
	379	; * prepare to get out of interrupt
	380	; * return from interrupt (maybe to _ISR_Dispatch)
	381	; *
	382	; * LABEL "exit interrupt (simple case):
	383	; * prepare to get out of interrupt
	384	; * return from interrupt
	385	; */
	386	;}
	387	;#endif
	388	; .global __ISR_Handler
	389	;__ISR_Handler:
	390	; jmpi lr0
	391	; nop
	392
[29d8227e]	393	.global _a29k_getops
	394	_a29k_getops:
	395	asneq 113, gr96, gr96
	396	jmpi lr0
	397	nop
	398
	399	.global _a29k_getops_sup
	400	_a29k_getops_sup:
	401	mfsr gr96, ops ; caller wants ops
	402	iret
	403	nop
	404
[a4d97d94]	405	.global _a29k_disable
	406	_a29k_disable:
	407	asneq 110, gr96, gr96
	408	jmpi lr0
	409	nop
	410
	411	.global _a29k_disable_sup
	412	_a29k_disable_sup:
	413	mfsr kt0, ops
[29d8227e]	414	add gr96, kt0, 0 ; return ops to caller
[a4d97d94]	415	const kt1, (DI \| TD)
	416	consth kt1, (DI \| TD)
	417	or kt1, kt0, kt1
	418	mtsr ops, kt1
	419	iret
	420	nop
	421
	422	.global _a29k_disable_all
	423	_a29k_disable_all:
	424	asneq 112, gr96, gr96
	425	jmpi lr0
	426	nop
	427
	428	.global _a29k_disable_all_sup
	429	_a29k_disable_all_sup:
	430	mfsr kt0, ops
[29d8227e]	431	const kt1, (DI \| TD)
	432	consth kt1, (DI \| TD)
[a4d97d94]	433	or kt1, kt0, kt1
	434	mtsr ops, kt1
	435	iret
	436	nop
	437
	438	.global _a29k_enable_all
	439	_a29k_enable_all:
	440	asneq 111, gr96, gr96
	441	jmpi lr0
	442	nop
	443
	444	.global _a29k_enable_all_sup
	445	_a29k_enable_all_sup:
	446	mfsr kt0, ops
[29d8227e]	447	const kt1, (DI \| TD)
	448	consth kt1, (DI \| TD)
[a4d97d94]	449	andn kt1, kt0, kt1
	450	mtsr ops, kt1
	451	iret
	452	nop
	453
	454	.global _a29k_enable
	455	_a29k_enable:
	456	asneq 109, gr96, gr96
	457	jmpi lr0
	458	nop
	459
	460	.global _a29k_enable_sup
	461	_a29k_enable_sup:
	462	mfsr kt0, ops
	463	const kt1, (DI \| TD)
	464	consth kt1, (DI \| TD)
[29d8227e]	465	and kt3, lr2, kt1
	466	andn kt0, kt0, kt1
	467	or kt1, kt0, kt3
[a4d97d94]	468	mtsr ops, kt1
	469	iret
	470	nop
	471
	472	.global _a29k_halt
	473	_a29k_halt:
	474	halt
	475	jmp _a29k_halt
	476	nop
	477
	478	.global _a29k_super_mode
	479	_a29k_super_mode:
	480	mfsr gr96, ops
	481	or gr96, gr96, 0x10
	482	mtsr ops, gr96
	483	iret
	484	nop
	485
	486	.global _a29k_as70
	487	_a29k_as70:
	488	asneq 70,gr96,gr96
	489	jmpi lr0
	490	nop

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Original Format